[PATCH] D101990: [AArch64][SVE] Improve SVE codegen for fixed length BITCAST

[David Sherwood via Phabricator via llvm-commits]

david-arm added a comment.

LGTM!



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17705
+
+  Op = convertToScalableVector(DAG, ContainerSrcVT, SrcOp);
+  Op = DAG.getNode(ISD::BITCAST, DL, ContainerDstVT, Op);
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nit: Not sure what others think, but I personally found this a little confusing. I realise you're reusing Op here, but I'd kind of expected something like this:

  SrcOp = convertToScalableVector(DAG, ContainerSrcVT, SrcOp);
  Op = DAG.getNode(ISD::BITCAST, DL, ContainerDstVT, SrcOp);


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  https://reviews.llvm.org/D101990/new/

https://reviews.llvm.org/D101990