[PATCH] D101826: [RISCV][VP] Lower VP ISD nodes to RVV instructions

Roger Ferrer Ibanez via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu May 6 06:00:53 PDT 2021


rogfer01 added a comment.

> Yeah exactly. I'm using `zeroext` mostly because it means we can use the same IR and get the same output on both RV32 and RV64 (the zero-extension is not required on RV32 and is eliminated on RV64). Otherwise I think we'd need separated RV32 and RV64 tests. In the real world I don't think we'd get the VL from a function parameter very often so it's a contrived example.

Well I envision a future in which when we vectorize function calls (say via `#pragma omp simd`) and in some cases they'll be able to receive `vl`. But given that we'll control them (as in they are not 100% user-provided code) we can always add the `zeroext` if needed (or whatever makes sense). There is still some time before we can do that though, so not a concern now.


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