[llvm] e723b51 - GlobalISel: Update documentation

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2021-05-05T17:35:02-04:00
New Revision: e723b511e6e951444d2a646a23fc2e9cf4faecd4

URL: https://github.com/llvm/llvm-project/commit/e723b511e6e951444d2a646a23fc2e9cf4faecd4
DIFF: https://github.com/llvm/llvm-project/commit/e723b511e6e951444d2a646a23fc2e9cf4faecd4.diff

LOG: GlobalISel: Update documentation

Added: 
    

Modified: 
    llvm/docs/GlobalISel/IRTranslator.rst

Removed: 
    


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diff  --git a/llvm/docs/GlobalISel/IRTranslator.rst b/llvm/docs/GlobalISel/IRTranslator.rst
index 9e12fdcbcbe5b..6268ebb4f4a1d 100644
--- a/llvm/docs/GlobalISel/IRTranslator.rst
+++ b/llvm/docs/GlobalISel/IRTranslator.rst
@@ -66,8 +66,8 @@ Aggregates
   worked much in this part of the codebase and it should have attention from
   someone more knowledgeable about it.
 
-Aggregates are lowered to a single scalar vreg.
-This 
diff ers from SelectionDAG's multiple vregs via ``GetValueVTs``.
+Aggregates are lowered into multiple virtual registers, similar to
+SelectionDAG's multiple vregs via ``GetValueVTs``.
 
 ``TODO``:
 As some of the bits are undef (padding), we should consider augmenting the