[PATCH] D101939: [AMDGPU] Disable the SIFormMemoryClauses pass at -O1
Baptiste Saleil via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed May 5 13:09:40 PDT 2021
bsaleil created this revision.
bsaleil added reviewers: piotr, rampitec, foad, arsenm.
bsaleil added projects: LLVM, AMDGPU.
Herald added subscribers: nikic, kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl.
bsaleil requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
This patch disables the SIFormMemoryClauses pass at -O1. This pass has a significant impact on compilation time, so we only want it to be enabled starting from -O2.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D101939
Files:
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
Index: llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
+++ llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
@@ -349,7 +349,6 @@
; GCN-O1-NEXT: Live Register Matrix
; GCN-O1-NEXT: SI Pre-allocate WWM Registers
; GCN-O1-NEXT: SI optimize exec mask operations pre-RA
-; GCN-O1-NEXT: SI Form memory clauses
; GCN-O1-NEXT: Machine Natural Loop Construction
; GCN-O1-NEXT: Machine Block Frequency Analysis
; GCN-O1-NEXT: Debug Variable Analysis
Index: llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1169,7 +1169,9 @@
if (OptExecMaskPreRA)
insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
- insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
+
+ if (TM->getOptLevel() > CodeGenOpt::Less)
+ insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
// This must be run immediately after phi elimination and before
// TwoAddressInstructions, otherwise the processing of the tied operand of
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