[llvm] a3d273c - [GlobalISel] Fix buildZExtInReg creating new register.

[Vang Thao via llvm-commits]

Author: Vang Thao
Date: 2021-05-05T08:19:52-07:00
New Revision: a3d273c9ff4c789aec0dc743fa2dc846b5987312

URL: https://github.com/llvm/llvm-project/commit/a3d273c9ff4c789aec0dc743fa2dc846b5987312
DIFF: https://github.com/llvm/llvm-project/commit/a3d273c9ff4c789aec0dc743fa2dc846b5987312.diff

LOG: [GlobalISel] Fix buildZExtInReg creating new register.

Fix a bug where buildZExtInReg will create and use a new register instead of using the register from parameter DstOp Res.

Reviewed By: arsenm, foad

Differential Revision: https://reviews.llvm.org/D101871

Added: 
    

Modified: 
    llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index bde442ae0429e..1f86bfaaebb6b 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -492,7 +492,7 @@ MachineInstrBuilder MachineIRBuilder::buildZExtInReg(const DstOp &Res,
   LLT ResTy = Res.getLLTTy(*getMRI());
   auto Mask = buildConstant(
       ResTy, APInt::getLowBitsSet(ResTy.getScalarSizeInBits(), ImmOp));
-  return buildAnd(ResTy, Op, Mask);
+  return buildAnd(Res, Op, Mask);
 }
 
 MachineInstrBuilder MachineIRBuilder::buildCast(const DstOp &Dst,