[llvm] 0f97afe - [MIPS][MSA] Regenerate immediates tests. NFCI.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Wed May 5 08:03:34 PDT 2021
Author: Simon Pilgrim
Date: 2021-05-05T16:03:19+01:00
New Revision: 0f97afe32044ab5b7e4d20090952143d8a5547e5
URL: https://github.com/llvm/llvm-project/commit/0f97afe32044ab5b7e4d20090952143d8a5547e5
DIFF: https://github.com/llvm/llvm-project/commit/0f97afe32044ab5b7e4d20090952143d8a5547e5.diff
LOG: [MIPS][MSA] Regenerate immediates tests. NFCI.
Simplifies an upcoming patch diff
Added:
Modified:
llvm/test/CodeGen/Mips/msa/immediates.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/Mips/msa/immediates.ll b/llvm/test/CodeGen/Mips/msa/immediates.ll
index 9876bb5dc935..db1eb17cf4a1 100644
--- a/llvm/test/CodeGen/Mips/msa/immediates.ll
+++ b/llvm/test/CodeGen/Mips/msa/immediates.ll
@@ -1,18 +1,31 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \
-; RUN: | FileCheck %s -check-prefixes=CHECK,MSA32
+; RUN: | FileCheck %s -check-prefixes=MSA,MSA32
; RUN: llc -march=mips64 -mattr=+msa,+fp64 -relocation-model=pic -target-abi n32 < %s \
-; RUN: | FileCheck %s -check-prefixes=CHECK,MSA64,MSA64N32
+; RUN: | FileCheck %s -check-prefix=MSA64N32
; RUN: llc -march=mips64 -mattr=+msa,+fp64 -relocation-model=pic -target-abi n64 < %s \
-; RUN: | FileCheck %s -check-prefixes=CHECK,MSA64,MSA64N64
+; RUN: | FileCheck %s -check-prefixes=MSA,MSA64N64
; Test that the immediate intrinsics don't crash LLVM.
; Some of the intrinsics lower to equivalent forms.
define void @addvi_b(<16 x i8> * %ptr) {
+; MSA-LABEL: addvi_b:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.b $w0, 0($4)
+; MSA-NEXT: addvi.b $w0, $w0, 25
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.b $w0, 0($4)
+;
+; MSA64N32-LABEL: addvi_b:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.b $w0, 0($1)
+; MSA64N32-NEXT: addvi.b $w0, $w0, 25
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.b $w0, 0($1)
entry:
-; CHECK-LABEL: addvi_b:
-; CHECK: addvi.b
%a = load <16 x i8>, <16 x i8> * %ptr, align 16
%r = call <16 x i8> @llvm.mips.addvi.b(<16 x i8> %a, i32 25)
store <16 x i8> %r, <16 x i8> * %ptr, align 16
@@ -20,9 +33,21 @@ entry:
}
define void @andi_b(<16 x i8> * %ptr) {
+; MSA-LABEL: andi_b:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.b $w0, 0($4)
+; MSA-NEXT: andi.b $w0, $w0, 25
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.b $w0, 0($4)
+;
+; MSA64N32-LABEL: andi_b:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.b $w0, 0($1)
+; MSA64N32-NEXT: andi.b $w0, $w0, 25
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.b $w0, 0($1)
entry:
-; CHECK-LABEL: andi_b:
-; CHECK: andi.b
%a = load <16 x i8>, <16 x i8> * %ptr, align 16
%r = call <16 x i8> @llvm.mips.andi.b(<16 x i8> %a, i32 25)
store <16 x i8> %r, <16 x i8> * %ptr, align 16
@@ -30,9 +55,21 @@ entry:
}
define void @bclri_b(<16 x i8> * %ptr) {
+; MSA-LABEL: bclri_b:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.b $w0, 0($4)
+; MSA-NEXT: andi.b $w0, $w0, 247
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.b $w0, 0($4)
+;
+; MSA64N32-LABEL: bclri_b:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.b $w0, 0($1)
+; MSA64N32-NEXT: andi.b $w0, $w0, 247
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.b $w0, 0($1)
entry:
-; CHECK-LABEL: bclri_b:
-; CHECK: andi.b
%a = load <16 x i8>, <16 x i8> * %ptr, align 16
%r = call <16 x i8> @llvm.mips.bclri.b(<16 x i8> %a, i32 3)
store <16 x i8> %r, <16 x i8> * %ptr, align 16
@@ -40,9 +77,24 @@ entry:
}
define void @binsli_b(<16 x i8> * %ptr, <16 x i8> * %ptr2) {
+; MSA-LABEL: binsli_b:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.b $w0, 0($5)
+; MSA-NEXT: ld.b $w1, 0($4)
+; MSA-NEXT: binsli.b $w1, $w0, 3
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.b $w1, 0($4)
+;
+; MSA64N32-LABEL: binsli_b:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: sll $2, $5, 0
+; MSA64N32-NEXT: ld.b $w0, 0($2)
+; MSA64N32-NEXT: ld.b $w1, 0($1)
+; MSA64N32-NEXT: binsli.b $w1, $w0, 3
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.b $w1, 0($1)
entry:
-; CHECK-LABEL: binsli_b:
-; CHECK: binsli.b
%a = load <16 x i8>, <16 x i8> * %ptr, align 16
%b = load <16 x i8>, <16 x i8> * %ptr2, align 16
%r = call <16 x i8> @llvm.mips.binsli.b(<16 x i8> %a, <16 x i8> %b, i32 3)
@@ -51,9 +103,24 @@ entry:
}
define void @binsri_b(<16 x i8> * %ptr, <16 x i8> * %ptr2) {
+; MSA-LABEL: binsri_b:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.b $w0, 0($5)
+; MSA-NEXT: ld.b $w1, 0($4)
+; MSA-NEXT: binsri.b $w1, $w0, 5
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.b $w1, 0($4)
+;
+; MSA64N32-LABEL: binsri_b:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: sll $2, $5, 0
+; MSA64N32-NEXT: ld.b $w0, 0($2)
+; MSA64N32-NEXT: ld.b $w1, 0($1)
+; MSA64N32-NEXT: binsri.b $w1, $w0, 5
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.b $w1, 0($1)
entry:
-; CHECK-LABEL: binsri_b:
-; CHECK: binsri.b
%a = load <16 x i8>, <16 x i8> * %ptr, align 16
%b = load <16 x i8>, <16 x i8> * %ptr2, align 16
%r = call <16 x i8> @llvm.mips.binsri.b(<16 x i8> %a, <16 x i8> %b, i32 5)
@@ -62,9 +129,24 @@ entry:
}
define void @bmnzi_b(<16 x i8> * %ptr, <16 x i8> * %ptr2) {
+; MSA-LABEL: bmnzi_b:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.b $w0, 0($5)
+; MSA-NEXT: ld.b $w1, 0($4)
+; MSA-NEXT: bmnzi.b $w1, $w0, 25
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.b $w1, 0($4)
+;
+; MSA64N32-LABEL: bmnzi_b:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: sll $2, $5, 0
+; MSA64N32-NEXT: ld.b $w0, 0($2)
+; MSA64N32-NEXT: ld.b $w1, 0($1)
+; MSA64N32-NEXT: bmnzi.b $w1, $w0, 25
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.b $w1, 0($1)
entry:
-; CHECK-LABEL: bmnzi_b:
-; CHECK: bmnzi.b
%a = load <16 x i8>, <16 x i8> * %ptr, align 16
%b = load <16 x i8>, <16 x i8> * %ptr2, align 16
%r = call <16 x i8> @llvm.mips.bmnzi.b(<16 x i8> %a, <16 x i8> %b, i32 25)
@@ -73,9 +155,24 @@ entry:
}
define void @bmzi_b(<16 x i8> * %ptr, <16 x i8> * %ptr2) {
+; MSA-LABEL: bmzi_b:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.b $w0, 0($4)
+; MSA-NEXT: ld.b $w1, 0($5)
+; MSA-NEXT: bmnzi.b $w1, $w0, 25
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.b $w1, 0($4)
+;
+; MSA64N32-LABEL: bmzi_b:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $5, 0
+; MSA64N32-NEXT: sll $2, $4, 0
+; MSA64N32-NEXT: ld.b $w0, 0($2)
+; MSA64N32-NEXT: ld.b $w1, 0($1)
+; MSA64N32-NEXT: bmnzi.b $w1, $w0, 25
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.b $w1, 0($2)
entry:
-; CHECK-LABEL: bmzi_b:
-; CHECK: bmnzi.b
%a = load <16 x i8>, <16 x i8> * %ptr, align 16
%b = load <16 x i8>, <16 x i8> * %ptr2, align 16
%r = call <16 x i8> @llvm.mips.bmzi.b(<16 x i8> %a, <16 x i8> %b, i32 25)
@@ -84,9 +181,21 @@ entry:
}
define void @bnegi_b(<16 x i8> * %ptr) {
+; MSA-LABEL: bnegi_b:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.b $w0, 0($4)
+; MSA-NEXT: bnegi.b $w0, $w0, 6
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.b $w0, 0($4)
+;
+; MSA64N32-LABEL: bnegi_b:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.b $w0, 0($1)
+; MSA64N32-NEXT: bnegi.b $w0, $w0, 6
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.b $w0, 0($1)
entry:
-; CHECK-LABEL: bnegi_b:
-; CHECK: bnegi.b
%a = load <16 x i8>, <16 x i8> * %ptr, align 16
%r = call <16 x i8> @llvm.mips.bnegi.b(<16 x i8> %a, i32 6)
store <16 x i8> %r, <16 x i8> * %ptr, align 16
@@ -94,9 +203,21 @@ entry:
}
define void @bseli_b(<16 x i8> * %ptr) {
+; MSA-LABEL: bseli_b:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.b $w0, 0($4)
+; MSA-NEXT: bseli.b $w0, $w0, 25
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.b $w0, 0($4)
+;
+; MSA64N32-LABEL: bseli_b:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.b $w0, 0($1)
+; MSA64N32-NEXT: bseli.b $w0, $w0, 25
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.b $w0, 0($1)
entry:
-; CHECK-LABEL: bseli_b:
-; CHECK: bseli.b
%a = load <16 x i8>, <16 x i8> * %ptr, align 16
%r = call <16 x i8> @llvm.mips.bseli.b(<16 x i8> %a, <16 x i8> %a, i32 25)
store <16 x i8> %r, <16 x i8> * %ptr, align 16
@@ -104,9 +225,21 @@ entry:
}
define void @bseti_b(<16 x i8> * %ptr) {
+; MSA-LABEL: bseti_b:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.b $w0, 0($4)
+; MSA-NEXT: bseti.b $w0, $w0, 5
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.b $w0, 0($4)
+;
+; MSA64N32-LABEL: bseti_b:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.b $w0, 0($1)
+; MSA64N32-NEXT: bseti.b $w0, $w0, 5
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.b $w0, 0($1)
entry:
-; CHECK-LABEL: bseti_b:
-; CHECK: bseti.b
%a = load <16 x i8>, <16 x i8> * %ptr, align 16
%r = call <16 x i8> @llvm.mips.bseti.b(<16 x i8> %a, i32 5)
store <16 x i8> %r, <16 x i8> * %ptr, align 16
@@ -114,9 +247,21 @@ entry:
}
define void @clei_s_b(<16 x i8> * %ptr) {
+; MSA-LABEL: clei_s_b:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.b $w0, 0($4)
+; MSA-NEXT: clei_s.b $w0, $w0, 12
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.b $w0, 0($4)
+;
+; MSA64N32-LABEL: clei_s_b:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.b $w0, 0($1)
+; MSA64N32-NEXT: clei_s.b $w0, $w0, 12
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.b $w0, 0($1)
entry:
-; CHECK-LABEL: clei_s_b:
-; CHECK: clei_s.b
%a = load <16 x i8>, <16 x i8> * %ptr, align 16
%r = call <16 x i8> @llvm.mips.clei.s.b(<16 x i8> %a, i32 12)
store <16 x i8> %r, <16 x i8> * %ptr, align 16
@@ -124,9 +269,21 @@ entry:
}
define void @clei_u_b(<16 x i8> * %ptr) {
+; MSA-LABEL: clei_u_b:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.b $w0, 0($4)
+; MSA-NEXT: clei_u.b $w0, $w0, 25
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.b $w0, 0($4)
+;
+; MSA64N32-LABEL: clei_u_b:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.b $w0, 0($1)
+; MSA64N32-NEXT: clei_u.b $w0, $w0, 25
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.b $w0, 0($1)
entry:
-; CHECK-LABEL: clei_u_b:
-; CHECK: clei_u.b
%a = load <16 x i8>, <16 x i8> * %ptr, align 16
%r = call <16 x i8> @llvm.mips.clei.u.b(<16 x i8> %a, i32 25)
store <16 x i8> %r, <16 x i8> * %ptr, align 16
@@ -134,9 +291,21 @@ entry:
}
define void @clti_s_b(<16 x i8> * %ptr) {
+; MSA-LABEL: clti_s_b:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.b $w0, 0($4)
+; MSA-NEXT: clti_s.b $w0, $w0, 15
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.b $w0, 0($4)
+;
+; MSA64N32-LABEL: clti_s_b:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.b $w0, 0($1)
+; MSA64N32-NEXT: clti_s.b $w0, $w0, 15
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.b $w0, 0($1)
entry:
-; CHECK-LABEL: clti_s_b:
-; CHECK: clti_s.b
%a = load <16 x i8>, <16 x i8> * %ptr, align 16
%r = call <16 x i8> @llvm.mips.clti.s.b(<16 x i8> %a, i32 15)
store <16 x i8> %r, <16 x i8> * %ptr, align 16
@@ -144,9 +313,21 @@ entry:
}
define void @clti_u_b(<16 x i8> * %ptr) {
+; MSA-LABEL: clti_u_b:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.b $w0, 0($4)
+; MSA-NEXT: clti_u.b $w0, $w0, 25
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.b $w0, 0($4)
+;
+; MSA64N32-LABEL: clti_u_b:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.b $w0, 0($1)
+; MSA64N32-NEXT: clti_u.b $w0, $w0, 25
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.b $w0, 0($1)
entry:
-; CHECK-LABEL: clti_u_b:
-; CHECK: clti_u.b
%a = load <16 x i8>, <16 x i8> * %ptr, align 16
%r = call <16 x i8> @llvm.mips.clti.u.b(<16 x i8> %a, i32 25)
store <16 x i8> %r, <16 x i8> * %ptr, align 16
@@ -154,18 +335,40 @@ entry:
}
define void @ldi_b(<16 x i8> * %ptr) {
+; MSA-LABEL: ldi_b:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ldi.b $w0, 3
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.b $w0, 0($4)
+;
+; MSA64N32-LABEL: ldi_b:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ldi.b $w0, 3
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.b $w0, 0($1)
entry:
-; CHECK-LABEL: ldi_b:
-; CHECK: ldi.b
%r = call <16 x i8> @llvm.mips.ldi.b(i32 3)
store <16 x i8> %r, <16 x i8> * %ptr, align 16
ret void
}
define void @maxi_s_b(<16 x i8> * %ptr) {
+; MSA-LABEL: maxi_s_b:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.b $w0, 0($4)
+; MSA-NEXT: maxi_s.b $w0, $w0, 2
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.b $w0, 0($4)
+;
+; MSA64N32-LABEL: maxi_s_b:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.b $w0, 0($1)
+; MSA64N32-NEXT: maxi_s.b $w0, $w0, 2
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.b $w0, 0($1)
entry:
-; CHECK-LABEL: maxi_s_b:
-; CHECK: maxi_s.b
%a = load <16 x i8>, <16 x i8> * %ptr, align 16
%r = call <16 x i8> @llvm.mips.maxi.s.b(<16 x i8> %a, i32 2)
store <16 x i8> %r, <16 x i8> * %ptr, align 16
@@ -173,9 +376,21 @@ entry:
}
define void @maxi_u_b(<16 x i8> * %ptr) {
+; MSA-LABEL: maxi_u_b:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.b $w0, 0($4)
+; MSA-NEXT: maxi_u.b $w0, $w0, 2
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.b $w0, 0($4)
+;
+; MSA64N32-LABEL: maxi_u_b:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.b $w0, 0($1)
+; MSA64N32-NEXT: maxi_u.b $w0, $w0, 2
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.b $w0, 0($1)
entry:
-; CHECK-LABEL: maxi_u_b:
-; CHECK: maxi_u.b
%a = load <16 x i8>, <16 x i8> * %ptr, align 16
%r = call <16 x i8> @llvm.mips.maxi.u.b(<16 x i8> %a, i32 2)
store <16 x i8> %r, <16 x i8> * %ptr, align 16
@@ -183,9 +398,21 @@ entry:
}
define void @mini_s_b(<16 x i8> * %ptr) {
+; MSA-LABEL: mini_s_b:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.b $w0, 0($4)
+; MSA-NEXT: mini_s.b $w0, $w0, 2
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.b $w0, 0($4)
+;
+; MSA64N32-LABEL: mini_s_b:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.b $w0, 0($1)
+; MSA64N32-NEXT: mini_s.b $w0, $w0, 2
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.b $w0, 0($1)
entry:
-; CHECK-LABEL: mini_s_b:
-; CHECK: mini_s.b
%a = load <16 x i8>, <16 x i8> * %ptr, align 16
%r = call <16 x i8> @llvm.mips.mini.s.b(<16 x i8> %a, i32 2)
store <16 x i8> %r, <16 x i8> * %ptr, align 16
@@ -193,9 +420,21 @@ entry:
}
define void @mini_u_b(<16 x i8> * %ptr) {
+; MSA-LABEL: mini_u_b:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.b $w0, 0($4)
+; MSA-NEXT: mini_u.b $w0, $w0, 2
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.b $w0, 0($4)
+;
+; MSA64N32-LABEL: mini_u_b:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.b $w0, 0($1)
+; MSA64N32-NEXT: mini_u.b $w0, $w0, 2
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.b $w0, 0($1)
entry:
-; CHECK-LABEL: mini_u_b:
-; CHECK: mini_u.b
%a = load <16 x i8>, <16 x i8> * %ptr, align 16
%r = call <16 x i8> @llvm.mips.mini.u.b(<16 x i8> %a, i32 2)
store <16 x i8> %r, <16 x i8> * %ptr, align 16
@@ -203,9 +442,21 @@ entry:
}
define void @nori_b(<16 x i8> * %ptr) {
+; MSA-LABEL: nori_b:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.b $w0, 0($4)
+; MSA-NEXT: nori.b $w0, $w0, 25
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.b $w0, 0($4)
+;
+; MSA64N32-LABEL: nori_b:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.b $w0, 0($1)
+; MSA64N32-NEXT: nori.b $w0, $w0, 25
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.b $w0, 0($1)
entry:
-; CHECK-LABEL: nori_b:
-; CHECK: nori.b
%a = load <16 x i8>, <16 x i8> * %ptr, align 16
%r = call <16 x i8> @llvm.mips.nori.b(<16 x i8> %a, i32 25)
store <16 x i8> %r, <16 x i8> * %ptr, align 16
@@ -213,9 +464,21 @@ entry:
}
define void @ori_b(<16 x i8> * %ptr) {
+; MSA-LABEL: ori_b:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.b $w0, 0($4)
+; MSA-NEXT: ori.b $w0, $w0, 25
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.b $w0, 0($4)
+;
+; MSA64N32-LABEL: ori_b:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.b $w0, 0($1)
+; MSA64N32-NEXT: ori.b $w0, $w0, 25
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.b $w0, 0($1)
entry:
-; CHECK-LABEL: ori_b:
-; CHECK: ori.b
%a = load <16 x i8>, <16 x i8> * %ptr, align 16
%r = call <16 x i8> @llvm.mips.ori.b(<16 x i8> %a, i32 25)
store <16 x i8> %r, <16 x i8> * %ptr, align 16
@@ -223,9 +486,21 @@ entry:
}
define void @sldi_b(<16 x i8> * %ptr) {
+; MSA-LABEL: sldi_b:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.b $w0, 0($4)
+; MSA-NEXT: sldi.b $w0, $w0[7]
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.b $w0, 0($4)
+;
+; MSA64N32-LABEL: sldi_b:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.b $w0, 0($1)
+; MSA64N32-NEXT: sldi.b $w0, $w0[7]
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.b $w0, 0($1)
entry:
-; CHECK-LABEL: sldi_b:
-; CHECK: sldi.b
%a = load <16 x i8>, <16 x i8> * %ptr, align 16
%r = call <16 x i8> @llvm.mips.sldi.b(<16 x i8> %a, <16 x i8> %a, i32 7)
store <16 x i8> %r, <16 x i8> * %ptr, align 16
@@ -233,9 +508,21 @@ entry:
}
define void @slli_b(<16 x i8> * %ptr) {
+; MSA-LABEL: slli_b:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.b $w0, 0($4)
+; MSA-NEXT: slli.b $w0, $w0, 3
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.b $w0, 0($4)
+;
+; MSA64N32-LABEL: slli_b:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.b $w0, 0($1)
+; MSA64N32-NEXT: slli.b $w0, $w0, 3
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.b $w0, 0($1)
entry:
-; CHECK-LABEL: slli_b:
-; CHECK: slli.b
%a = load <16 x i8>, <16 x i8> * %ptr, align 16
%r = call <16 x i8> @llvm.mips.slli.b(<16 x i8> %a, i32 3)
store <16 x i8> %r, <16 x i8> * %ptr, align 16
@@ -243,9 +530,21 @@ entry:
}
define void @splati_b(<16 x i8> * %ptr) {
+; MSA-LABEL: splati_b:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.b $w0, 0($4)
+; MSA-NEXT: splati.b $w0, $w0[3]
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.b $w0, 0($4)
+;
+; MSA64N32-LABEL: splati_b:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.b $w0, 0($1)
+; MSA64N32-NEXT: splati.b $w0, $w0[3]
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.b $w0, 0($1)
entry:
-; CHECK-LABEL: splati_b:
-; CHECK: splati.b
%a = load <16 x i8>, <16 x i8> * %ptr, align 16
%r = call <16 x i8> @llvm.mips.splati.b(<16 x i8> %a, i32 3)
store <16 x i8> %r, <16 x i8> * %ptr, align 16
@@ -253,9 +552,21 @@ entry:
}
define void @srai_b(<16 x i8> * %ptr) {
+; MSA-LABEL: srai_b:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.b $w0, 0($4)
+; MSA-NEXT: srai.b $w0, $w0, 3
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.b $w0, 0($4)
+;
+; MSA64N32-LABEL: srai_b:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.b $w0, 0($1)
+; MSA64N32-NEXT: srai.b $w0, $w0, 3
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.b $w0, 0($1)
entry:
-; CHECK-LABEL: srai_b:
-; CHECK: srai.b
%a = load <16 x i8>, <16 x i8> * %ptr, align 16
%r = call <16 x i8> @llvm.mips.srai.b(<16 x i8> %a, i32 3)
store <16 x i8> %r, <16 x i8> * %ptr, align 16
@@ -263,9 +574,21 @@ entry:
}
define void @srari_b(<16 x i8> * %ptr) {
+; MSA-LABEL: srari_b:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.b $w0, 0($4)
+; MSA-NEXT: srari.b $w0, $w0, 3
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.b $w0, 0($4)
+;
+; MSA64N32-LABEL: srari_b:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.b $w0, 0($1)
+; MSA64N32-NEXT: srari.b $w0, $w0, 3
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.b $w0, 0($1)
entry:
-; CHECK-LABEL: srari_b:
-; CHECK: srari.b
%a = load <16 x i8>, <16 x i8> * %ptr, align 16
%r = call <16 x i8> @llvm.mips.srari.b(<16 x i8> %a, i32 3)
store <16 x i8> %r, <16 x i8> * %ptr, align 16
@@ -273,9 +596,21 @@ entry:
}
define void @srli_b(<16 x i8> * %ptr) {
+; MSA-LABEL: srli_b:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.b $w0, 0($4)
+; MSA-NEXT: srli.b $w0, $w0, 3
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.b $w0, 0($4)
+;
+; MSA64N32-LABEL: srli_b:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.b $w0, 0($1)
+; MSA64N32-NEXT: srli.b $w0, $w0, 3
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.b $w0, 0($1)
entry:
-; CHECK-LABEL: srli_b:
-; CHECK: srli.b
%a = load <16 x i8>, <16 x i8> * %ptr, align 16
%r = call <16 x i8> @llvm.mips.srli.b(<16 x i8> %a, i32 3)
store <16 x i8> %r, <16 x i8> * %ptr, align 16
@@ -283,9 +618,21 @@ entry:
}
define void @srlri_b(<16 x i8> * %ptr) {
+; MSA-LABEL: srlri_b:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.b $w0, 0($4)
+; MSA-NEXT: srlri.b $w0, $w0, 3
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.b $w0, 0($4)
+;
+; MSA64N32-LABEL: srlri_b:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.b $w0, 0($1)
+; MSA64N32-NEXT: srlri.b $w0, $w0, 3
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.b $w0, 0($1)
entry:
-; CHECK-LABEL: srlri_b:
-; CHECK: srlri.b
%a = load <16 x i8>, <16 x i8> * %ptr, align 16
%r = call <16 x i8> @llvm.mips.srlri.b(<16 x i8> %a, i32 3)
store <16 x i8> %r, <16 x i8> * %ptr, align 16
@@ -293,9 +640,21 @@ entry:
}
define void @addvi_w(<4 x i32> * %ptr) {
+; MSA-LABEL: addvi_w:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.w $w0, 0($4)
+; MSA-NEXT: addvi.w $w0, $w0, 25
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.w $w0, 0($4)
+;
+; MSA64N32-LABEL: addvi_w:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.w $w0, 0($1)
+; MSA64N32-NEXT: addvi.w $w0, $w0, 25
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.w $w0, 0($1)
entry:
-; CHECK-LABEL: addvi_w:
-; CHECK: addvi.w
%a = load <4 x i32>, <4 x i32> * %ptr, align 16
%r = call <4 x i32> @llvm.mips.addvi.w(<4 x i32> %a, i32 25)
store <4 x i32> %r, <4 x i32> * %ptr, align 16
@@ -303,9 +662,21 @@ entry:
}
define void @bclri_w(<4 x i32> * %ptr) {
+; MSA-LABEL: bclri_w:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.w $w0, 0($4)
+; MSA-NEXT: bclri.w $w0, $w0, 25
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.w $w0, 0($4)
+;
+; MSA64N32-LABEL: bclri_w:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.w $w0, 0($1)
+; MSA64N32-NEXT: bclri.w $w0, $w0, 25
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.w $w0, 0($1)
entry:
-; CHECK-LABEL: bclri_w:
-; CHECK: bclri.w
%a = load <4 x i32>, <4 x i32> * %ptr, align 16
%r = call <4 x i32> @llvm.mips.bclri.w(<4 x i32> %a, i32 25)
store <4 x i32> %r, <4 x i32> * %ptr, align 16
@@ -313,9 +684,24 @@ entry:
}
define void @binsli_w(<4 x i32> * %ptr, <4 x i32> * %ptr2) {
+; MSA-LABEL: binsli_w:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.w $w0, 0($5)
+; MSA-NEXT: ld.w $w1, 0($4)
+; MSA-NEXT: binsli.w $w1, $w0, 25
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.w $w1, 0($4)
+;
+; MSA64N32-LABEL: binsli_w:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: sll $2, $5, 0
+; MSA64N32-NEXT: ld.w $w0, 0($2)
+; MSA64N32-NEXT: ld.w $w1, 0($1)
+; MSA64N32-NEXT: binsli.w $w1, $w0, 25
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.w $w1, 0($1)
entry:
-; CHECK-LABEL: binsli_w:
-; CHECK: binsli.w
%a = load <4 x i32>, <4 x i32> * %ptr, align 16
%b = load <4 x i32>, <4 x i32> * %ptr2, align 16
%r = call <4 x i32> @llvm.mips.binsli.w(<4 x i32> %a, <4 x i32> %b, i32 25)
@@ -324,9 +710,24 @@ entry:
}
define void @binsri_w(<4 x i32> * %ptr, <4 x i32> * %ptr2) {
+; MSA-LABEL: binsri_w:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.w $w0, 0($5)
+; MSA-NEXT: ld.w $w1, 0($4)
+; MSA-NEXT: binsri.w $w1, $w0, 25
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.w $w1, 0($4)
+;
+; MSA64N32-LABEL: binsri_w:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: sll $2, $5, 0
+; MSA64N32-NEXT: ld.w $w0, 0($2)
+; MSA64N32-NEXT: ld.w $w1, 0($1)
+; MSA64N32-NEXT: binsri.w $w1, $w0, 25
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.w $w1, 0($1)
entry:
-; CHECK-LABEL: binsri_w:
-; CHECK: binsri.w
%a = load <4 x i32>, <4 x i32> * %ptr, align 16
%b = load <4 x i32>, <4 x i32> * %ptr2, align 16
%r = call <4 x i32> @llvm.mips.binsri.w(<4 x i32> %a, <4 x i32> %b, i32 25)
@@ -335,9 +736,21 @@ entry:
}
define void @bnegi_w(<4 x i32> * %ptr) {
+; MSA-LABEL: bnegi_w:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.w $w0, 0($4)
+; MSA-NEXT: bnegi.w $w0, $w0, 25
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.w $w0, 0($4)
+;
+; MSA64N32-LABEL: bnegi_w:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.w $w0, 0($1)
+; MSA64N32-NEXT: bnegi.w $w0, $w0, 25
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.w $w0, 0($1)
entry:
-; CHECK-LABEL: bnegi_w:
-; CHECK: bnegi.w
%a = load <4 x i32>, <4 x i32> * %ptr, align 16
%r = call <4 x i32> @llvm.mips.bnegi.w(<4 x i32> %a, i32 25)
store <4 x i32> %r, <4 x i32> * %ptr, align 16
@@ -345,9 +758,21 @@ entry:
}
define void @bseti_w(<4 x i32> * %ptr) {
+; MSA-LABEL: bseti_w:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.w $w0, 0($4)
+; MSA-NEXT: bseti.w $w0, $w0, 25
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.w $w0, 0($4)
+;
+; MSA64N32-LABEL: bseti_w:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.w $w0, 0($1)
+; MSA64N32-NEXT: bseti.w $w0, $w0, 25
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.w $w0, 0($1)
entry:
-; CHECK-LABEL: bseti_w:
-; CHECK: bseti.w
%a = load <4 x i32>, <4 x i32> * %ptr, align 16
%r = call <4 x i32> @llvm.mips.bseti.w(<4 x i32> %a, i32 25)
store <4 x i32> %r, <4 x i32> * %ptr, align 16
@@ -355,9 +780,21 @@ entry:
}
define void @clei_s_w(<4 x i32> * %ptr) {
+; MSA-LABEL: clei_s_w:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.w $w0, 0($4)
+; MSA-NEXT: clei_s.w $w0, $w0, 14
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.w $w0, 0($4)
+;
+; MSA64N32-LABEL: clei_s_w:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.w $w0, 0($1)
+; MSA64N32-NEXT: clei_s.w $w0, $w0, 14
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.w $w0, 0($1)
entry:
-; CHECK-LABEL: clei_s_w:
-; CHECK: clei_s.w
%a = load <4 x i32>, <4 x i32> * %ptr, align 16
%r = call <4 x i32> @llvm.mips.clei.s.w(<4 x i32> %a, i32 14)
store <4 x i32> %r, <4 x i32> * %ptr, align 16
@@ -365,9 +802,21 @@ entry:
}
define void @clei_u_w(<4 x i32> * %ptr) {
+; MSA-LABEL: clei_u_w:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.w $w0, 0($4)
+; MSA-NEXT: clei_u.w $w0, $w0, 25
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.w $w0, 0($4)
+;
+; MSA64N32-LABEL: clei_u_w:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.w $w0, 0($1)
+; MSA64N32-NEXT: clei_u.w $w0, $w0, 25
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.w $w0, 0($1)
entry:
-; CHECK-LABEL: clei_u_w:
-; CHECK: clei_u.w
%a = load <4 x i32>, <4 x i32> * %ptr, align 16
%r = call <4 x i32> @llvm.mips.clei.u.w(<4 x i32> %a, i32 25)
store <4 x i32> %r, <4 x i32> * %ptr, align 16
@@ -375,9 +824,21 @@ entry:
}
define void @clti_s_w(<4 x i32> * %ptr) {
+; MSA-LABEL: clti_s_w:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.w $w0, 0($4)
+; MSA-NEXT: clti_s.w $w0, $w0, 15
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.w $w0, 0($4)
+;
+; MSA64N32-LABEL: clti_s_w:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.w $w0, 0($1)
+; MSA64N32-NEXT: clti_s.w $w0, $w0, 15
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.w $w0, 0($1)
entry:
-; CHECK-LABEL: clti_s_w:
-; CHECK: clti_s.w
%a = load <4 x i32>, <4 x i32> * %ptr, align 16
%r = call <4 x i32> @llvm.mips.clti.s.w(<4 x i32> %a, i32 15)
store <4 x i32> %r, <4 x i32> * %ptr, align 16
@@ -385,9 +846,21 @@ entry:
}
define void @clti_u_w(<4 x i32> * %ptr) {
+; MSA-LABEL: clti_u_w:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.w $w0, 0($4)
+; MSA-NEXT: clti_u.w $w0, $w0, 25
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.w $w0, 0($4)
+;
+; MSA64N32-LABEL: clti_u_w:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.w $w0, 0($1)
+; MSA64N32-NEXT: clti_u.w $w0, $w0, 25
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.w $w0, 0($1)
entry:
-; CHECK-LABEL: clti_u_w:
-; CHECK: clti_u.w
%a = load <4 x i32>, <4 x i32> * %ptr, align 16
%r = call <4 x i32> @llvm.mips.clti.u.w(<4 x i32> %a, i32 25)
store <4 x i32> %r, <4 x i32> * %ptr, align 16
@@ -395,9 +868,21 @@ entry:
}
define void @maxi_s_w(<4 x i32> * %ptr) {
+; MSA-LABEL: maxi_s_w:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.w $w0, 0($4)
+; MSA-NEXT: maxi_s.w $w0, $w0, 2
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.w $w0, 0($4)
+;
+; MSA64N32-LABEL: maxi_s_w:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.w $w0, 0($1)
+; MSA64N32-NEXT: maxi_s.w $w0, $w0, 2
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.w $w0, 0($1)
entry:
-; CHECK-LABEL: maxi_s_w:
-; CHECK: maxi_s.w
%a = load <4 x i32>, <4 x i32> * %ptr, align 16
%r = call <4 x i32> @llvm.mips.maxi.s.w(<4 x i32> %a, i32 2)
store <4 x i32> %r, <4 x i32> * %ptr, align 16
@@ -405,9 +890,21 @@ entry:
}
define void @maxi_u_w(<4 x i32> * %ptr) {
+; MSA-LABEL: maxi_u_w:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.w $w0, 0($4)
+; MSA-NEXT: maxi_u.w $w0, $w0, 2
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.w $w0, 0($4)
+;
+; MSA64N32-LABEL: maxi_u_w:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.w $w0, 0($1)
+; MSA64N32-NEXT: maxi_u.w $w0, $w0, 2
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.w $w0, 0($1)
entry:
-; CHECK-LABEL: maxi_u_w:
-; CHECK: maxi_u.w
%a = load <4 x i32>, <4 x i32> * %ptr, align 16
%r = call <4 x i32> @llvm.mips.maxi.u.w(<4 x i32> %a, i32 2)
store <4 x i32> %r, <4 x i32> * %ptr, align 16
@@ -415,9 +912,21 @@ entry:
}
define void @mini_s_w(<4 x i32> * %ptr) {
+; MSA-LABEL: mini_s_w:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.w $w0, 0($4)
+; MSA-NEXT: mini_s.w $w0, $w0, 2
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.w $w0, 0($4)
+;
+; MSA64N32-LABEL: mini_s_w:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.w $w0, 0($1)
+; MSA64N32-NEXT: mini_s.w $w0, $w0, 2
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.w $w0, 0($1)
entry:
-; CHECK-LABEL: mini_s_w:
-; CHECK: mini_s.w
%a = load <4 x i32>, <4 x i32> * %ptr, align 16
%r = call <4 x i32> @llvm.mips.mini.s.w(<4 x i32> %a, i32 2)
store <4 x i32> %r, <4 x i32> * %ptr, align 16
@@ -425,9 +934,21 @@ entry:
}
define void @mini_u_w(<4 x i32> * %ptr) {
+; MSA-LABEL: mini_u_w:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.w $w0, 0($4)
+; MSA-NEXT: mini_u.w $w0, $w0, 2
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.w $w0, 0($4)
+;
+; MSA64N32-LABEL: mini_u_w:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.w $w0, 0($1)
+; MSA64N32-NEXT: mini_u.w $w0, $w0, 2
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.w $w0, 0($1)
entry:
-; CHECK-LABEL: mini_u_w:
-; CHECK: mini_u.w
%a = load <4 x i32>, <4 x i32> * %ptr, align 16
%r = call <4 x i32> @llvm.mips.mini.u.w(<4 x i32> %a, i32 2)
store <4 x i32> %r, <4 x i32> * %ptr, align 16
@@ -435,18 +956,40 @@ entry:
}
define void @ldi_w(<4 x i32> * %ptr) {
+; MSA-LABEL: ldi_w:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ldi.w $w0, 3
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.w $w0, 0($4)
+;
+; MSA64N32-LABEL: ldi_w:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ldi.w $w0, 3
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.w $w0, 0($1)
entry:
-; CHECK-LABEL: ldi_w:
-; CHECK: ldi.w
%r = call <4 x i32> @llvm.mips.ldi.w(i32 3)
store <4 x i32> %r, <4 x i32> * %ptr, align 16
ret void
}
define void @sldi_w(<4 x i32> * %ptr) {
+; MSA-LABEL: sldi_w:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.w $w0, 0($4)
+; MSA-NEXT: sldi.w $w0, $w0[2]
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.w $w0, 0($4)
+;
+; MSA64N32-LABEL: sldi_w:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.w $w0, 0($1)
+; MSA64N32-NEXT: sldi.w $w0, $w0[2]
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.w $w0, 0($1)
entry:
-; CHECK-LABEL: sldi_w:
-; CHECK: sldi.w
%a = load <4 x i32>, <4 x i32> * %ptr, align 16
%r = call <4 x i32> @llvm.mips.sldi.w(<4 x i32> %a, <4 x i32> %a, i32 2)
store <4 x i32> %r, <4 x i32> * %ptr, align 16
@@ -454,9 +997,21 @@ entry:
}
define void @slli_w(<4 x i32> * %ptr) {
+; MSA-LABEL: slli_w:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.w $w0, 0($4)
+; MSA-NEXT: slli.w $w0, $w0, 3
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.w $w0, 0($4)
+;
+; MSA64N32-LABEL: slli_w:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.w $w0, 0($1)
+; MSA64N32-NEXT: slli.w $w0, $w0, 3
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.w $w0, 0($1)
entry:
-; CHECK-LABEL: slli_w:
-; CHECK: slli.w
%a = load <4 x i32>, <4 x i32> * %ptr, align 16
%r = call <4 x i32> @llvm.mips.slli.w(<4 x i32> %a, i32 3)
store <4 x i32> %r, <4 x i32> * %ptr, align 16
@@ -464,9 +1019,21 @@ entry:
}
define void @splati_w(<4 x i32> * %ptr) {
+; MSA-LABEL: splati_w:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.w $w0, 0($4)
+; MSA-NEXT: splati.w $w0, $w0[3]
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.w $w0, 0($4)
+;
+; MSA64N32-LABEL: splati_w:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.w $w0, 0($1)
+; MSA64N32-NEXT: splati.w $w0, $w0[3]
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.w $w0, 0($1)
entry:
-; CHECK-LABEL: splati_w:
-; CHECK: splati.w
%a = load <4 x i32>, <4 x i32> * %ptr, align 16
%r = call <4 x i32> @llvm.mips.splati.w(<4 x i32> %a, i32 3)
store <4 x i32> %r, <4 x i32> * %ptr, align 16
@@ -474,9 +1041,21 @@ entry:
}
define void @srai_w(<4 x i32> * %ptr) {
+; MSA-LABEL: srai_w:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.w $w0, 0($4)
+; MSA-NEXT: srai.w $w0, $w0, 3
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.w $w0, 0($4)
+;
+; MSA64N32-LABEL: srai_w:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.w $w0, 0($1)
+; MSA64N32-NEXT: srai.w $w0, $w0, 3
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.w $w0, 0($1)
entry:
-; CHECK-LABEL: srai_w:
-; CHECK: srai.w
%a = load <4 x i32>, <4 x i32> * %ptr, align 16
%r = call <4 x i32> @llvm.mips.srai.w(<4 x i32> %a, i32 3)
store <4 x i32> %r, <4 x i32> * %ptr, align 16
@@ -484,9 +1063,21 @@ entry:
}
define void @srari_w(<4 x i32> * %ptr) {
+; MSA-LABEL: srari_w:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.w $w0, 0($4)
+; MSA-NEXT: srari.w $w0, $w0, 3
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.w $w0, 0($4)
+;
+; MSA64N32-LABEL: srari_w:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.w $w0, 0($1)
+; MSA64N32-NEXT: srari.w $w0, $w0, 3
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.w $w0, 0($1)
entry:
-; CHECK-LABEL: srari_w:
-; CHECK: srari.w
%a = load <4 x i32>, <4 x i32> * %ptr, align 16
%r = call <4 x i32> @llvm.mips.srari.w(<4 x i32> %a, i32 3)
store <4 x i32> %r, <4 x i32> * %ptr, align 16
@@ -494,9 +1085,21 @@ entry:
}
define void @srli_w(<4 x i32> * %ptr) {
+; MSA-LABEL: srli_w:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.w $w0, 0($4)
+; MSA-NEXT: srli.w $w0, $w0, 3
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.w $w0, 0($4)
+;
+; MSA64N32-LABEL: srli_w:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.w $w0, 0($1)
+; MSA64N32-NEXT: srli.w $w0, $w0, 3
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.w $w0, 0($1)
entry:
-; CHECK-LABEL: srli_w:
-; CHECK: srli.w
%a = load <4 x i32>, <4 x i32> * %ptr, align 16
%r = call <4 x i32> @llvm.mips.srli.w(<4 x i32> %a, i32 3)
store <4 x i32> %r, <4 x i32> * %ptr, align 16
@@ -504,9 +1107,21 @@ entry:
}
define void @srlri_w(<4 x i32> * %ptr) {
+; MSA-LABEL: srlri_w:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.w $w0, 0($4)
+; MSA-NEXT: srlri.w $w0, $w0, 3
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.w $w0, 0($4)
+;
+; MSA64N32-LABEL: srlri_w:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.w $w0, 0($1)
+; MSA64N32-NEXT: srlri.w $w0, $w0, 3
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.w $w0, 0($1)
entry:
-; CHECK-LABEL: srlri_w:
-; CHECK: srlri.w
%a = load <4 x i32>, <4 x i32> * %ptr, align 16
%r = call <4 x i32> @llvm.mips.srlri.w(<4 x i32> %a, i32 3)
store <4 x i32> %r, <4 x i32> * %ptr, align 16
@@ -514,9 +1129,21 @@ entry:
}
define void @addvi_h(<8 x i16> * %ptr) {
+; MSA-LABEL: addvi_h:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.h $w0, 0($4)
+; MSA-NEXT: addvi.h $w0, $w0, 25
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.h $w0, 0($4)
+;
+; MSA64N32-LABEL: addvi_h:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.h $w0, 0($1)
+; MSA64N32-NEXT: addvi.h $w0, $w0, 25
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.h $w0, 0($1)
entry:
-; CHECK-LABEL: addvi_h:
-; CHECK: addvi.h
%a = load <8 x i16>, <8 x i16> * %ptr, align 16
%r = call <8 x i16> @llvm.mips.addvi.h(<8 x i16> %a, i32 25)
store <8 x i16> %r, <8 x i16> * %ptr, align 16
@@ -524,9 +1151,21 @@ entry:
}
define void @bclri_h(<8 x i16> * %ptr) {
+; MSA-LABEL: bclri_h:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.h $w0, 0($4)
+; MSA-NEXT: bclri.h $w0, $w0, 8
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.h $w0, 0($4)
+;
+; MSA64N32-LABEL: bclri_h:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.h $w0, 0($1)
+; MSA64N32-NEXT: bclri.h $w0, $w0, 8
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.h $w0, 0($1)
entry:
-; CHECK-LABEL: bclri_h:
-; CHECK: bclri.h
%a = load <8 x i16>, <8 x i16> * %ptr, align 16
%r = call <8 x i16> @llvm.mips.bclri.h(<8 x i16> %a, i32 8)
store <8 x i16> %r, <8 x i16> * %ptr, align 16
@@ -534,9 +1173,24 @@ entry:
}
define void @binsli_h(<8 x i16> * %ptr, <8 x i16> * %ptr2) {
+; MSA-LABEL: binsli_h:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.h $w0, 0($5)
+; MSA-NEXT: ld.h $w1, 0($4)
+; MSA-NEXT: binsli.h $w1, $w0, 8
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.h $w1, 0($4)
+;
+; MSA64N32-LABEL: binsli_h:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: sll $2, $5, 0
+; MSA64N32-NEXT: ld.h $w0, 0($2)
+; MSA64N32-NEXT: ld.h $w1, 0($1)
+; MSA64N32-NEXT: binsli.h $w1, $w0, 8
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.h $w1, 0($1)
entry:
-; CHECK-LABEL: binsli_h:
-; CHECK: binsli.h
%a = load <8 x i16>, <8 x i16> * %ptr, align 16
%b = load <8 x i16>, <8 x i16> * %ptr2, align 16
%r = call <8 x i16> @llvm.mips.binsli.h(<8 x i16> %a, <8 x i16> %b, i32 8)
@@ -545,9 +1199,24 @@ entry:
}
define void @binsri_h(<8 x i16> * %ptr, <8 x i16> * %ptr2) {
+; MSA-LABEL: binsri_h:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.h $w0, 0($5)
+; MSA-NEXT: ld.h $w1, 0($4)
+; MSA-NEXT: binsri.h $w1, $w0, 14
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.h $w1, 0($4)
+;
+; MSA64N32-LABEL: binsri_h:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: sll $2, $5, 0
+; MSA64N32-NEXT: ld.h $w0, 0($2)
+; MSA64N32-NEXT: ld.h $w1, 0($1)
+; MSA64N32-NEXT: binsri.h $w1, $w0, 14
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.h $w1, 0($1)
entry:
-; CHECK-LABEL: binsri_h:
-; CHECK: binsri.h
%a = load <8 x i16>, <8 x i16> * %ptr, align 16
%b = load <8 x i16>, <8 x i16> * %ptr2, align 16
%r = call <8 x i16> @llvm.mips.binsri.h(<8 x i16> %a, <8 x i16> %b, i32 14)
@@ -556,9 +1225,21 @@ entry:
}
define void @bnegi_h(<8 x i16> * %ptr) {
+; MSA-LABEL: bnegi_h:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.h $w0, 0($4)
+; MSA-NEXT: bnegi.h $w0, $w0, 14
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.h $w0, 0($4)
+;
+; MSA64N32-LABEL: bnegi_h:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.h $w0, 0($1)
+; MSA64N32-NEXT: bnegi.h $w0, $w0, 14
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.h $w0, 0($1)
entry:
-; CHECK-LABEL: bnegi_h:
-; CHECK: bnegi.h
%a = load <8 x i16>, <8 x i16> * %ptr, align 16
%r = call <8 x i16> @llvm.mips.bnegi.h(<8 x i16> %a, i32 14)
store <8 x i16> %r, <8 x i16> * %ptr, align 16
@@ -566,9 +1247,21 @@ entry:
}
define void @bseti_h(<8 x i16> * %ptr) {
+; MSA-LABEL: bseti_h:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.h $w0, 0($4)
+; MSA-NEXT: bseti.h $w0, $w0, 15
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.h $w0, 0($4)
+;
+; MSA64N32-LABEL: bseti_h:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.h $w0, 0($1)
+; MSA64N32-NEXT: bseti.h $w0, $w0, 15
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.h $w0, 0($1)
entry:
-; CHECK-LABEL: bseti_h:
-; CHECK: bseti.h
%a = load <8 x i16>, <8 x i16> * %ptr, align 16
%r = call <8 x i16> @llvm.mips.bseti.h(<8 x i16> %a, i32 15)
store <8 x i16> %r, <8 x i16> * %ptr, align 16
@@ -576,9 +1269,21 @@ entry:
}
define void @clei_s_h(<8 x i16> * %ptr) {
+; MSA-LABEL: clei_s_h:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.h $w0, 0($4)
+; MSA-NEXT: clei_s.h $w0, $w0, 13
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.h $w0, 0($4)
+;
+; MSA64N32-LABEL: clei_s_h:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.h $w0, 0($1)
+; MSA64N32-NEXT: clei_s.h $w0, $w0, 13
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.h $w0, 0($1)
entry:
-; CHECK-LABEL: clei_s_h:
-; CHECK: clei_s.h
%a = load <8 x i16>, <8 x i16> * %ptr, align 16
%r = call <8 x i16> @llvm.mips.clei.s.h(<8 x i16> %a, i32 13)
store <8 x i16> %r, <8 x i16> * %ptr, align 16
@@ -586,9 +1291,21 @@ entry:
}
define void @clei_u_h(<8 x i16> * %ptr) {
+; MSA-LABEL: clei_u_h:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.h $w0, 0($4)
+; MSA-NEXT: clei_u.h $w0, $w0, 25
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.h $w0, 0($4)
+;
+; MSA64N32-LABEL: clei_u_h:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.h $w0, 0($1)
+; MSA64N32-NEXT: clei_u.h $w0, $w0, 25
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.h $w0, 0($1)
entry:
-; CHECK-LABEL: clei_u_h:
-; CHECK: clei_u.h
%a = load <8 x i16>, <8 x i16> * %ptr, align 16
%r = call <8 x i16> @llvm.mips.clei.u.h(<8 x i16> %a, i32 25)
store <8 x i16> %r, <8 x i16> * %ptr, align 16
@@ -596,9 +1313,21 @@ entry:
}
define void @clti_s_h(<8 x i16> * %ptr) {
+; MSA-LABEL: clti_s_h:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.h $w0, 0($4)
+; MSA-NEXT: clti_s.h $w0, $w0, 15
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.h $w0, 0($4)
+;
+; MSA64N32-LABEL: clti_s_h:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.h $w0, 0($1)
+; MSA64N32-NEXT: clti_s.h $w0, $w0, 15
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.h $w0, 0($1)
entry:
-; CHECK-LABEL: clti_s_h:
-; CHECK: clti_s.h
%a = load <8 x i16>, <8 x i16> * %ptr, align 16
%r = call <8 x i16> @llvm.mips.clti.s.h(<8 x i16> %a, i32 15)
store <8 x i16> %r, <8 x i16> * %ptr, align 16
@@ -606,9 +1335,21 @@ entry:
}
define void @clti_u_h(<8 x i16> * %ptr) {
+; MSA-LABEL: clti_u_h:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.h $w0, 0($4)
+; MSA-NEXT: clti_u.h $w0, $w0, 25
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.h $w0, 0($4)
+;
+; MSA64N32-LABEL: clti_u_h:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.h $w0, 0($1)
+; MSA64N32-NEXT: clti_u.h $w0, $w0, 25
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.h $w0, 0($1)
entry:
-; CHECK-LABEL: clti_u_h:
-; CHECK: clti_u.h
%a = load <8 x i16>, <8 x i16> * %ptr, align 16
%r = call <8 x i16> @llvm.mips.clti.u.h(<8 x i16> %a, i32 25)
store <8 x i16> %r, <8 x i16> * %ptr, align 16
@@ -616,9 +1357,21 @@ entry:
}
define void @maxi_s_h(<8 x i16> * %ptr) {
+; MSA-LABEL: maxi_s_h:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.h $w0, 0($4)
+; MSA-NEXT: maxi_s.h $w0, $w0, 2
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.h $w0, 0($4)
+;
+; MSA64N32-LABEL: maxi_s_h:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.h $w0, 0($1)
+; MSA64N32-NEXT: maxi_s.h $w0, $w0, 2
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.h $w0, 0($1)
entry:
-; CHECK-LABEL: maxi_s_h:
-; CHECK: maxi_s.h
%a = load <8 x i16>, <8 x i16> * %ptr, align 16
%r = call <8 x i16> @llvm.mips.maxi.s.h(<8 x i16> %a, i32 2)
store <8 x i16> %r, <8 x i16> * %ptr, align 16
@@ -626,9 +1379,21 @@ entry:
}
define void @maxi_u_h(<8 x i16> * %ptr) {
+; MSA-LABEL: maxi_u_h:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.h $w0, 0($4)
+; MSA-NEXT: maxi_u.h $w0, $w0, 2
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.h $w0, 0($4)
+;
+; MSA64N32-LABEL: maxi_u_h:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.h $w0, 0($1)
+; MSA64N32-NEXT: maxi_u.h $w0, $w0, 2
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.h $w0, 0($1)
entry:
-; CHECK-LABEL: maxi_u_h:
-; CHECK: maxi_u.h
%a = load <8 x i16>, <8 x i16> * %ptr, align 16
%r = call <8 x i16> @llvm.mips.maxi.u.h(<8 x i16> %a, i32 2)
store <8 x i16> %r, <8 x i16> * %ptr, align 16
@@ -636,9 +1401,21 @@ entry:
}
define void @mini_s_h(<8 x i16> * %ptr) {
+; MSA-LABEL: mini_s_h:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.h $w0, 0($4)
+; MSA-NEXT: mini_s.h $w0, $w0, 2
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.h $w0, 0($4)
+;
+; MSA64N32-LABEL: mini_s_h:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.h $w0, 0($1)
+; MSA64N32-NEXT: mini_s.h $w0, $w0, 2
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.h $w0, 0($1)
entry:
-; CHECK-LABEL: mini_s_h:
-; CHECK: mini_s.h
%a = load <8 x i16>, <8 x i16> * %ptr, align 16
%r = call <8 x i16> @llvm.mips.mini.s.h(<8 x i16> %a, i32 2)
store <8 x i16> %r, <8 x i16> * %ptr, align 16
@@ -646,9 +1423,21 @@ entry:
}
define void @mini_u_h(<8 x i16> * %ptr) {
+; MSA-LABEL: mini_u_h:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.h $w0, 0($4)
+; MSA-NEXT: mini_u.h $w0, $w0, 2
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.h $w0, 0($4)
+;
+; MSA64N32-LABEL: mini_u_h:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.h $w0, 0($1)
+; MSA64N32-NEXT: mini_u.h $w0, $w0, 2
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.h $w0, 0($1)
entry:
-; CHECK-LABEL: mini_u_h:
-; CHECK: mini_u.h
%a = load <8 x i16>, <8 x i16> * %ptr, align 16
%r = call <8 x i16> @llvm.mips.mini.u.h(<8 x i16> %a, i32 2)
store <8 x i16> %r, <8 x i16> * %ptr, align 16
@@ -656,18 +1445,40 @@ entry:
}
define void @ldi_h(<8 x i16> * %ptr) {
+; MSA-LABEL: ldi_h:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ldi.h $w0, 3
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.h $w0, 0($4)
+;
+; MSA64N32-LABEL: ldi_h:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ldi.h $w0, 3
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.h $w0, 0($1)
entry:
-; CHECK-LABEL: ldi_h:
-; CHECK: ldi.h
%r = call <8 x i16> @llvm.mips.ldi.h(i32 3)
store <8 x i16> %r, <8 x i16> * %ptr, align 16
ret void
}
define void @sldi_h(<8 x i16> * %ptr) {
+; MSA-LABEL: sldi_h:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.h $w0, 0($4)
+; MSA-NEXT: sldi.h $w0, $w0[3]
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.h $w0, 0($4)
+;
+; MSA64N32-LABEL: sldi_h:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.h $w0, 0($1)
+; MSA64N32-NEXT: sldi.h $w0, $w0[3]
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.h $w0, 0($1)
entry:
-; CHECK-LABEL: sldi_h:
-; CHECK: sldi.h
%a = load <8 x i16>, <8 x i16> * %ptr, align 16
%r = call <8 x i16> @llvm.mips.sldi.h(<8 x i16> %a, <8 x i16> %a, i32 3)
store <8 x i16> %r, <8 x i16> * %ptr, align 16
@@ -675,9 +1486,21 @@ entry:
}
define void @slli_h(<8 x i16> * %ptr) {
+; MSA-LABEL: slli_h:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.h $w0, 0($4)
+; MSA-NEXT: slli.h $w0, $w0, 3
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.h $w0, 0($4)
+;
+; MSA64N32-LABEL: slli_h:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.h $w0, 0($1)
+; MSA64N32-NEXT: slli.h $w0, $w0, 3
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.h $w0, 0($1)
entry:
-; CHECK-LABEL: slli_h:
-; CHECK: slli.h
%a = load <8 x i16>, <8 x i16> * %ptr, align 16
%r = call <8 x i16> @llvm.mips.slli.h(<8 x i16> %a, i32 3)
store <8 x i16> %r, <8 x i16> * %ptr, align 16
@@ -685,9 +1508,21 @@ entry:
}
define void @splati_h(<8 x i16> * %ptr) {
+; MSA-LABEL: splati_h:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.h $w0, 0($4)
+; MSA-NEXT: splati.h $w0, $w0[3]
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.h $w0, 0($4)
+;
+; MSA64N32-LABEL: splati_h:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.h $w0, 0($1)
+; MSA64N32-NEXT: splati.h $w0, $w0[3]
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.h $w0, 0($1)
entry:
-; CHECK-LABEL: splati_h:
-; CHECK: splati.h
%a = load <8 x i16>, <8 x i16> * %ptr, align 16
%r = call <8 x i16> @llvm.mips.splati.h(<8 x i16> %a, i32 3)
store <8 x i16> %r, <8 x i16> * %ptr, align 16
@@ -695,9 +1530,21 @@ entry:
}
define void @srai_h(<8 x i16> * %ptr) {
+; MSA-LABEL: srai_h:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.h $w0, 0($4)
+; MSA-NEXT: srai.h $w0, $w0, 3
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.h $w0, 0($4)
+;
+; MSA64N32-LABEL: srai_h:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.h $w0, 0($1)
+; MSA64N32-NEXT: srai.h $w0, $w0, 3
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.h $w0, 0($1)
entry:
-; CHECK-LABEL: srai_h:
-; CHECK: srai.h
%a = load <8 x i16>, <8 x i16> * %ptr, align 16
%r = call <8 x i16> @llvm.mips.srai.h(<8 x i16> %a, i32 3)
store <8 x i16> %r, <8 x i16> * %ptr, align 16
@@ -705,9 +1552,21 @@ entry:
}
define void @srari_h(<8 x i16> * %ptr) {
+; MSA-LABEL: srari_h:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.h $w0, 0($4)
+; MSA-NEXT: srari.h $w0, $w0, 3
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.h $w0, 0($4)
+;
+; MSA64N32-LABEL: srari_h:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.h $w0, 0($1)
+; MSA64N32-NEXT: srari.h $w0, $w0, 3
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.h $w0, 0($1)
entry:
-; CHECK-LABEL: srari_h:
-; CHECK: srari.h
%a = load <8 x i16>, <8 x i16> * %ptr, align 16
%r = call <8 x i16> @llvm.mips.srari.h(<8 x i16> %a, i32 3)
store <8 x i16> %r, <8 x i16> * %ptr, align 16
@@ -715,9 +1574,21 @@ entry:
}
define void @srli_h(<8 x i16> * %ptr) {
+; MSA-LABEL: srli_h:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.h $w0, 0($4)
+; MSA-NEXT: srli.h $w0, $w0, 3
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.h $w0, 0($4)
+;
+; MSA64N32-LABEL: srli_h:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.h $w0, 0($1)
+; MSA64N32-NEXT: srli.h $w0, $w0, 3
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.h $w0, 0($1)
entry:
-; CHECK-LABEL: srli_h:
-; CHECK: srli.h
%a = load <8 x i16>, <8 x i16> * %ptr, align 16
%r = call <8 x i16> @llvm.mips.srli.h(<8 x i16> %a, i32 3)
store <8 x i16> %r, <8 x i16> * %ptr, align 16
@@ -725,9 +1596,21 @@ entry:
}
define void @srlri_h(<8 x i16> * %ptr) {
+; MSA-LABEL: srlri_h:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.h $w0, 0($4)
+; MSA-NEXT: srlri.h $w0, $w0, 3
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.h $w0, 0($4)
+;
+; MSA64N32-LABEL: srlri_h:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.h $w0, 0($1)
+; MSA64N32-NEXT: srlri.h $w0, $w0, 3
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.h $w0, 0($1)
entry:
-; CHECK-LABEL: srlri_h:
-; CHECK: srlri.h
%a = load <8 x i16>, <8 x i16> * %ptr, align 16
%r = call <8 x i16> @llvm.mips.srlri.h(<8 x i16> %a, i32 3)
store <8 x i16> %r, <8 x i16> * %ptr, align 16
@@ -735,81 +1618,188 @@ entry:
}
define i32 @copy_s_b(<16 x i8> * %ptr) {
+; MSA-LABEL: copy_s_b:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.b $w0, 0($4)
+; MSA-NEXT: jr $ra
+; MSA-NEXT: copy_s.b $2, $w0[1]
+;
+; MSA64N32-LABEL: copy_s_b:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.b $w0, 0($1)
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: copy_s.b $2, $w0[1]
entry:
-; CHECK-LABEL: copy_s_b:
-; CHECK: copy_s.b
%a = load <16 x i8>, <16 x i8> * %ptr, align 16
%r = call i32 @llvm.mips.copy.s.b(<16 x i8> %a, i32 1)
ret i32 %r
}
define i32 @copy_s_h(<8 x i16> * %ptr) {
+; MSA-LABEL: copy_s_h:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.h $w0, 0($4)
+; MSA-NEXT: jr $ra
+; MSA-NEXT: copy_s.h $2, $w0[1]
+;
+; MSA64N32-LABEL: copy_s_h:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.h $w0, 0($1)
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: copy_s.h $2, $w0[1]
entry:
-; CHECK-LABEL: copy_s_h:
-; CHECK: copy_s.h
%a = load <8 x i16>, <8 x i16> * %ptr, align 16
%r = call i32 @llvm.mips.copy.s.h(<8 x i16> %a, i32 1)
ret i32 %r
}
define i32 @copy_s_w(<4 x i32> * %ptr) {
+; MSA-LABEL: copy_s_w:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.w $w0, 0($4)
+; MSA-NEXT: jr $ra
+; MSA-NEXT: copy_s.w $2, $w0[1]
+;
+; MSA64N32-LABEL: copy_s_w:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.w $w0, 0($1)
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: copy_s.w $2, $w0[1]
entry:
-; CHECK-LABEL: copy_s_w:
-; CHECK: copy_s.w
%a = load <4 x i32>, <4 x i32> * %ptr, align 16
%r = call i32 @llvm.mips.copy.s.w(<4 x i32> %a, i32 1)
ret i32 %r
}
define i32 @copy_u_b(<16 x i8> * %ptr) {
+; MSA-LABEL: copy_u_b:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.b $w0, 0($4)
+; MSA-NEXT: jr $ra
+; MSA-NEXT: copy_u.b $2, $w0[1]
+;
+; MSA64N32-LABEL: copy_u_b:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.b $w0, 0($1)
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: copy_u.b $2, $w0[1]
entry:
-; CHECK-LABEL: copy_u_b:
-; CHECK: copy_u.b
%a = load <16 x i8>, <16 x i8> * %ptr, align 16
%r = call i32 @llvm.mips.copy.u.b(<16 x i8> %a, i32 1)
ret i32 %r
}
define i32 @copy_u_h(<8 x i16> * %ptr) {
+; MSA-LABEL: copy_u_h:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.h $w0, 0($4)
+; MSA-NEXT: jr $ra
+; MSA-NEXT: copy_u.h $2, $w0[1]
+;
+; MSA64N32-LABEL: copy_u_h:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.h $w0, 0($1)
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: copy_u.h $2, $w0[1]
entry:
-; CHECK-LABEL: copy_u_h:
-; CHECK: copy_u.h
%a = load <8 x i16>, <8 x i16> * %ptr, align 16
%r = call i32 @llvm.mips.copy.u.h(<8 x i16> %a, i32 1)
ret i32 %r
}
define i32 @copy_u_w(<4 x i32> * %ptr) {
+; MSA32-LABEL: copy_u_w:
+; MSA32: # %bb.0: # %entry
+; MSA32-NEXT: ld.w $w0, 0($4)
+; MSA32-NEXT: jr $ra
+; MSA32-NEXT: copy_s.w $2, $w0[1]
+;
+; MSA64N32-LABEL: copy_u_w:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.w $w0, 0($1)
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: copy_u.w $2, $w0[1]
+;
+; MSA64N64-LABEL: copy_u_w:
+; MSA64N64: # %bb.0: # %entry
+; MSA64N64-NEXT: ld.w $w0, 0($4)
+; MSA64N64-NEXT: jr $ra
+; MSA64N64-NEXT: copy_u.w $2, $w0[1]
entry:
-; CHECK-LABEL: copy_u_w:
-; MSA32: copy_s.w
-; MSA64: copy_u.w
%a = load <4 x i32>, <4 x i32> * %ptr, align 16
%r = call i32 @llvm.mips.copy.u.w(<4 x i32> %a, i32 1)
ret i32 %r
}
define i64 @copy_s_d(<2 x i64> * %ptr) {
+; MSA32-LABEL: copy_s_d:
+; MSA32: # %bb.0: # %entry
+; MSA32-NEXT: ld.w $w0, 0($4)
+; MSA32-NEXT: copy_s.w $2, $w0[2]
+; MSA32-NEXT: jr $ra
+; MSA32-NEXT: copy_s.w $3, $w0[3]
+;
+; MSA64N32-LABEL: copy_s_d:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.d $w0, 0($1)
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: copy_s.d $2, $w0[1]
+;
+; MSA64N64-LABEL: copy_s_d:
+; MSA64N64: # %bb.0: # %entry
+; MSA64N64-NEXT: ld.d $w0, 0($4)
+; MSA64N64-NEXT: jr $ra
+; MSA64N64-NEXT: copy_s.d $2, $w0[1]
entry:
-; CHECK-LABEL: copy_s_d:
-; MSA32: copy_s.w
-; MSA32: copy_s.w
-; MSA64: copy_s.d
%a = load <2 x i64>, <2 x i64> * %ptr, align 16
%r = call i64 @llvm.mips.copy.s.d(<2 x i64> %a, i32 1)
ret i64 %r
}
define i64 @copy_u_d(<2 x i64> * %ptr) {
+; MSA32-LABEL: copy_u_d:
+; MSA32: # %bb.0: # %entry
+; MSA32-NEXT: ld.w $w0, 0($4)
+; MSA32-NEXT: copy_s.w $2, $w0[2]
+; MSA32-NEXT: jr $ra
+; MSA32-NEXT: copy_s.w $3, $w0[3]
+;
+; MSA64N32-LABEL: copy_u_d:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.d $w0, 0($1)
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: copy_s.d $2, $w0[1]
+;
+; MSA64N64-LABEL: copy_u_d:
+; MSA64N64: # %bb.0: # %entry
+; MSA64N64-NEXT: ld.d $w0, 0($4)
+; MSA64N64-NEXT: jr $ra
+; MSA64N64-NEXT: copy_s.d $2, $w0[1]
entry:
-; CHECK-LABEL: copy_u_d:
-; MSA32: copy_s.w
-; MSA32: copy_s.w
-; MSA64: copy_s.d
%a = load <2 x i64>, <2 x i64> * %ptr, align 16
%r = call i64 @llvm.mips.copy.u.d(<2 x i64> %a, i32 1)
ret i64 %r
}
define void @addvi_d(<2 x i64> * %ptr) {
+; MSA-LABEL: addvi_d:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.d $w0, 0($4)
+; MSA-NEXT: addvi.d $w0, $w0, 25
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.d $w0, 0($4)
+;
+; MSA64N32-LABEL: addvi_d:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.d $w0, 0($1)
+; MSA64N32-NEXT: addvi.d $w0, $w0, 25
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.d $w0, 0($1)
entry:
-; CHECK-LABEL: addvi_d:
-; CHECK: addvi.d
%a = load <2 x i64>, <2 x i64> * %ptr, align 16
%r = call <2 x i64> @llvm.mips.addvi.d(<2 x i64> %a, i32 25)
store <2 x i64> %r, <2 x i64> * %ptr, align 16
@@ -817,9 +1807,21 @@ entry:
}
define void @bclri_d(<2 x i64> * %ptr) {
+; MSA-LABEL: bclri_d:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.d $w0, 0($4)
+; MSA-NEXT: bclri.d $w0, $w0, 16
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.d $w0, 0($4)
+;
+; MSA64N32-LABEL: bclri_d:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.d $w0, 0($1)
+; MSA64N32-NEXT: bclri.d $w0, $w0, 16
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.d $w0, 0($1)
entry:
-; CHECK-LABEL: bclri_d:
-; CHECK: bclri.d
%a = load <2 x i64>, <2 x i64> * %ptr, align 16
%r = call <2 x i64> @llvm.mips.bclri.d(<2 x i64> %a, i32 16)
store <2 x i64> %r, <2 x i64> * %ptr, align 16
@@ -827,9 +1829,24 @@ entry:
}
define void @binsli_d(<2 x i64> * %ptr, <2 x i64> * %ptr2) {
+; MSA-LABEL: binsli_d:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.d $w0, 0($5)
+; MSA-NEXT: ld.d $w1, 0($4)
+; MSA-NEXT: binsli.d $w1, $w0, 4
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.d $w1, 0($4)
+;
+; MSA64N32-LABEL: binsli_d:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: sll $2, $5, 0
+; MSA64N32-NEXT: ld.d $w0, 0($2)
+; MSA64N32-NEXT: ld.d $w1, 0($1)
+; MSA64N32-NEXT: binsli.d $w1, $w0, 4
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.d $w1, 0($1)
entry:
-; CHECK-LABEL: binsli_d:
-; CHECK: binsli.d
%a = load <2 x i64>, <2 x i64> * %ptr, align 16
%b = load <2 x i64>, <2 x i64> * %ptr2, align 16
%r = call <2 x i64> @llvm.mips.binsli.d(<2 x i64> %a, <2 x i64> %b, i32 4)
@@ -838,9 +1855,24 @@ entry:
}
define void @binsri_d(<2 x i64> * %ptr, <2 x i64> * %ptr2) {
+; MSA-LABEL: binsri_d:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.d $w0, 0($5)
+; MSA-NEXT: ld.d $w1, 0($4)
+; MSA-NEXT: binsri.d $w1, $w0, 5
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.d $w1, 0($4)
+;
+; MSA64N32-LABEL: binsri_d:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: sll $2, $5, 0
+; MSA64N32-NEXT: ld.d $w0, 0($2)
+; MSA64N32-NEXT: ld.d $w1, 0($1)
+; MSA64N32-NEXT: binsri.d $w1, $w0, 5
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.d $w1, 0($1)
entry:
-; CHECK-LABEL: binsri_d:
-; CHECK: binsri.d
%a = load <2 x i64>, <2 x i64> * %ptr, align 16
%b = load <2 x i64>, <2 x i64> * %ptr2, align 16
%r = call <2 x i64> @llvm.mips.binsri.d(<2 x i64> %a, <2 x i64> %b, i32 5)
@@ -849,9 +1881,21 @@ entry:
}
define void @bnegi_d(<2 x i64> * %ptr) {
+; MSA-LABEL: bnegi_d:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.d $w0, 0($4)
+; MSA-NEXT: bnegi.d $w0, $w0, 9
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.d $w0, 0($4)
+;
+; MSA64N32-LABEL: bnegi_d:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.d $w0, 0($1)
+; MSA64N32-NEXT: bnegi.d $w0, $w0, 9
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.d $w0, 0($1)
entry:
-; CHECK-LABEL: bnegi_d:
-; CHECK: bnegi.d
%a = load <2 x i64>, <2 x i64> * %ptr, align 16
%r = call <2 x i64> @llvm.mips.bnegi.d(<2 x i64> %a, i32 9)
store <2 x i64> %r, <2 x i64> * %ptr, align 16
@@ -859,9 +1903,21 @@ entry:
}
define void @bseti_d(<2 x i64> * %ptr) {
+; MSA-LABEL: bseti_d:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.d $w0, 0($4)
+; MSA-NEXT: bseti.d $w0, $w0, 25
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.d $w0, 0($4)
+;
+; MSA64N32-LABEL: bseti_d:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.d $w0, 0($1)
+; MSA64N32-NEXT: bseti.d $w0, $w0, 25
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.d $w0, 0($1)
entry:
-; CHECK-LABEL: bseti_d:
-; CHECK: bseti.d
%a = load <2 x i64>, <2 x i64> * %ptr, align 16
%r = call <2 x i64> @llvm.mips.bseti.d(<2 x i64> %a, i32 25)
store <2 x i64> %r, <2 x i64> * %ptr, align 16
@@ -869,9 +1925,21 @@ entry:
}
define void @clei_s_d(<2 x i64> * %ptr) {
+; MSA-LABEL: clei_s_d:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.d $w0, 0($4)
+; MSA-NEXT: clei_s.d $w0, $w0, 15
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.d $w0, 0($4)
+;
+; MSA64N32-LABEL: clei_s_d:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.d $w0, 0($1)
+; MSA64N32-NEXT: clei_s.d $w0, $w0, 15
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.d $w0, 0($1)
entry:
-; CHECK-LABEL: clei_s_d:
-; CHECK: clei_s.d
%a = load <2 x i64>, <2 x i64> * %ptr, align 16
%r = call <2 x i64> @llvm.mips.clei.s.d(<2 x i64> %a, i32 15)
store <2 x i64> %r, <2 x i64> * %ptr, align 16
@@ -879,9 +1947,21 @@ entry:
}
define void @clei_u_d(<2 x i64> * %ptr) {
+; MSA-LABEL: clei_u_d:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.d $w0, 0($4)
+; MSA-NEXT: clei_u.d $w0, $w0, 25
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.d $w0, 0($4)
+;
+; MSA64N32-LABEL: clei_u_d:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.d $w0, 0($1)
+; MSA64N32-NEXT: clei_u.d $w0, $w0, 25
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.d $w0, 0($1)
entry:
-; CHECK-LABEL: clei_u_d:
-; CHECK: clei_u.d
%a = load <2 x i64>, <2 x i64> * %ptr, align 16
%r = call <2 x i64> @llvm.mips.clei.u.d(<2 x i64> %a, i32 25)
store <2 x i64> %r, <2 x i64> * %ptr, align 16
@@ -889,9 +1969,21 @@ entry:
}
define void @clti_s_d(<2 x i64> * %ptr) {
+; MSA-LABEL: clti_s_d:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.d $w0, 0($4)
+; MSA-NEXT: clti_s.d $w0, $w0, 15
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.d $w0, 0($4)
+;
+; MSA64N32-LABEL: clti_s_d:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.d $w0, 0($1)
+; MSA64N32-NEXT: clti_s.d $w0, $w0, 15
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.d $w0, 0($1)
entry:
-; CHECK-LABEL: clti_s_d:
-; CHECK: clti_s.d
%a = load <2 x i64>, <2 x i64> * %ptr, align 16
%r = call <2 x i64> @llvm.mips.clti.s.d(<2 x i64> %a, i32 15)
store <2 x i64> %r, <2 x i64> * %ptr, align 16
@@ -899,9 +1991,21 @@ entry:
}
define void @clti_u_d(<2 x i64> * %ptr) {
+; MSA-LABEL: clti_u_d:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.d $w0, 0($4)
+; MSA-NEXT: clti_u.d $w0, $w0, 25
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.d $w0, 0($4)
+;
+; MSA64N32-LABEL: clti_u_d:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.d $w0, 0($1)
+; MSA64N32-NEXT: clti_u.d $w0, $w0, 25
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.d $w0, 0($1)
entry:
-; CHECK-LABEL: clti_u_d:
-; CHECK: clti_u.d
%a = load <2 x i64>, <2 x i64> * %ptr, align 16
%r = call <2 x i64> @llvm.mips.clti.u.d(<2 x i64> %a, i32 25)
store <2 x i64> %r, <2 x i64> * %ptr, align 16
@@ -909,18 +2013,46 @@ entry:
}
define void @ldi_d(<2 x i64> * %ptr) {
+; MSA32-LABEL: ldi_d:
+; MSA32: # %bb.0: # %entry
+; MSA32-NEXT: ldi.d $w0, 3
+; MSA32-NEXT: jr $ra
+; MSA32-NEXT: st.w $w0, 0($4)
+;
+; MSA64N32-LABEL: ldi_d:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ldi.d $w0, 3
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.d $w0, 0($1)
+;
+; MSA64N64-LABEL: ldi_d:
+; MSA64N64: # %bb.0: # %entry
+; MSA64N64-NEXT: ldi.d $w0, 3
+; MSA64N64-NEXT: jr $ra
+; MSA64N64-NEXT: st.d $w0, 0($4)
entry:
-; CHECK-LABEL: ldi_d:
-; CHECK: ldi.d
%r = call <2 x i64> @llvm.mips.ldi.d(i32 3)
store <2 x i64> %r, <2 x i64> * %ptr, align 16
ret void
}
define void @maxi_s_d(<2 x i64> * %ptr) {
+; MSA-LABEL: maxi_s_d:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.d $w0, 0($4)
+; MSA-NEXT: maxi_s.d $w0, $w0, 2
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.d $w0, 0($4)
+;
+; MSA64N32-LABEL: maxi_s_d:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.d $w0, 0($1)
+; MSA64N32-NEXT: maxi_s.d $w0, $w0, 2
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.d $w0, 0($1)
entry:
-; CHECK-LABEL: maxi_s_d:
-; CHECK: maxi_s.d
%a = load <2 x i64>, <2 x i64> * %ptr, align 16
%r = call <2 x i64> @llvm.mips.maxi.s.d(<2 x i64> %a, i32 2)
store <2 x i64> %r, <2 x i64> * %ptr, align 16
@@ -928,9 +2060,21 @@ entry:
}
define void @maxi_u_d(<2 x i64> * %ptr) {
+; MSA-LABEL: maxi_u_d:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.d $w0, 0($4)
+; MSA-NEXT: maxi_u.d $w0, $w0, 2
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.d $w0, 0($4)
+;
+; MSA64N32-LABEL: maxi_u_d:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.d $w0, 0($1)
+; MSA64N32-NEXT: maxi_u.d $w0, $w0, 2
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.d $w0, 0($1)
entry:
-; CHECK-LABEL: maxi_u_d:
-; CHECK: maxi_u.d
%a = load <2 x i64>, <2 x i64> * %ptr, align 16
%r = call <2 x i64> @llvm.mips.maxi.u.d(<2 x i64> %a, i32 2)
store <2 x i64> %r, <2 x i64> * %ptr, align 16
@@ -938,9 +2082,21 @@ entry:
}
define void @mini_s_d(<2 x i64> * %ptr) {
+; MSA-LABEL: mini_s_d:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.d $w0, 0($4)
+; MSA-NEXT: mini_s.d $w0, $w0, 2
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.d $w0, 0($4)
+;
+; MSA64N32-LABEL: mini_s_d:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.d $w0, 0($1)
+; MSA64N32-NEXT: mini_s.d $w0, $w0, 2
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.d $w0, 0($1)
entry:
-; CHECK-LABEL: mini_s_d:
-; CHECK: mini_s.d
%a = load <2 x i64>, <2 x i64> * %ptr, align 16
%r = call <2 x i64> @llvm.mips.mini.s.d(<2 x i64> %a, i32 2)
store <2 x i64> %r, <2 x i64> * %ptr, align 16
@@ -948,9 +2104,21 @@ entry:
}
define void @mini_u_d(<2 x i64> * %ptr) {
+; MSA-LABEL: mini_u_d:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.d $w0, 0($4)
+; MSA-NEXT: mini_u.d $w0, $w0, 2
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.d $w0, 0($4)
+;
+; MSA64N32-LABEL: mini_u_d:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.d $w0, 0($1)
+; MSA64N32-NEXT: mini_u.d $w0, $w0, 2
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.d $w0, 0($1)
entry:
-; CHECK-LABEL: mini_u_d:
-; CHECK: mini_u.d
%a = load <2 x i64>, <2 x i64> * %ptr, align 16
%r = call <2 x i64> @llvm.mips.mini.u.d(<2 x i64> %a, i32 2)
store <2 x i64> %r, <2 x i64> * %ptr, align 16
@@ -958,9 +2126,21 @@ entry:
}
define void @sldi_d(<2 x i64> * %ptr) {
+; MSA-LABEL: sldi_d:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.d $w0, 0($4)
+; MSA-NEXT: sldi.d $w0, $w0[1]
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.d $w0, 0($4)
+;
+; MSA64N32-LABEL: sldi_d:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.d $w0, 0($1)
+; MSA64N32-NEXT: sldi.d $w0, $w0[1]
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.d $w0, 0($1)
entry:
-; CHECK-LABEL: sldi_d:
-; CHECK: sldi.d
%a = load <2 x i64>, <2 x i64> * %ptr, align 16
%r = call <2 x i64> @llvm.mips.sldi.d(<2 x i64> %a, <2 x i64> %a, i32 1)
store <2 x i64> %r, <2 x i64> * %ptr, align 16
@@ -968,9 +2148,21 @@ entry:
}
define void @slli_d(<2 x i64> * %ptr) {
+; MSA-LABEL: slli_d:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.d $w0, 0($4)
+; MSA-NEXT: slli.d $w0, $w0, 3
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.d $w0, 0($4)
+;
+; MSA64N32-LABEL: slli_d:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.d $w0, 0($1)
+; MSA64N32-NEXT: slli.d $w0, $w0, 3
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.d $w0, 0($1)
entry:
-; CHECK-LABEL: slli_d:
-; CHECK: slli.d
%a = load <2 x i64>, <2 x i64> * %ptr, align 16
%r = call <2 x i64> @llvm.mips.slli.d(<2 x i64> %a, i32 3)
store <2 x i64> %r, <2 x i64> * %ptr, align 16
@@ -978,9 +2170,21 @@ entry:
}
define void @srai_d(<2 x i64> * %ptr) {
+; MSA-LABEL: srai_d:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.d $w0, 0($4)
+; MSA-NEXT: srai.d $w0, $w0, 3
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.d $w0, 0($4)
+;
+; MSA64N32-LABEL: srai_d:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.d $w0, 0($1)
+; MSA64N32-NEXT: srai.d $w0, $w0, 3
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.d $w0, 0($1)
entry:
-; CHECK-LABEL: srai_d:
-; CHECK: srai.d
%a = load <2 x i64>, <2 x i64> * %ptr, align 16
%r = call <2 x i64> @llvm.mips.srai.d(<2 x i64> %a, i32 3)
store <2 x i64> %r, <2 x i64> * %ptr, align 16
@@ -988,9 +2192,21 @@ entry:
}
define void @srari_d(<2 x i64> * %ptr) {
+; MSA-LABEL: srari_d:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.d $w0, 0($4)
+; MSA-NEXT: srari.d $w0, $w0, 3
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.d $w0, 0($4)
+;
+; MSA64N32-LABEL: srari_d:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.d $w0, 0($1)
+; MSA64N32-NEXT: srari.d $w0, $w0, 3
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.d $w0, 0($1)
entry:
-; CHECK-LABEL: srari_d:
-; CHECK: srari.d
%a = load <2 x i64>, <2 x i64> * %ptr, align 16
%r = call <2 x i64> @llvm.mips.srari.d(<2 x i64> %a, i32 3)
store <2 x i64> %r, <2 x i64> * %ptr, align 16
@@ -998,9 +2214,21 @@ entry:
}
define void @srli_d(<2 x i64> * %ptr) {
+; MSA-LABEL: srli_d:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.d $w0, 0($4)
+; MSA-NEXT: srli.d $w0, $w0, 3
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.d $w0, 0($4)
+;
+; MSA64N32-LABEL: srli_d:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.d $w0, 0($1)
+; MSA64N32-NEXT: srli.d $w0, $w0, 3
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.d $w0, 0($1)
entry:
-; CHECK-LABEL: srli_d:
-; CHECK: srli.d
%a = load <2 x i64>, <2 x i64> * %ptr, align 16
%r = call <2 x i64> @llvm.mips.srli.d(<2 x i64> %a, i32 3)
store <2 x i64> %r, <2 x i64> * %ptr, align 16
@@ -1008,9 +2236,21 @@ entry:
}
define void @srlri_d(<2 x i64> * %ptr) {
+; MSA-LABEL: srlri_d:
+; MSA: # %bb.0: # %entry
+; MSA-NEXT: ld.d $w0, 0($4)
+; MSA-NEXT: srlri.d $w0, $w0, 3
+; MSA-NEXT: jr $ra
+; MSA-NEXT: st.d $w0, 0($4)
+;
+; MSA64N32-LABEL: srlri_d:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: ld.d $w0, 0($1)
+; MSA64N32-NEXT: srlri.d $w0, $w0, 3
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.d $w0, 0($1)
entry:
-; CHECK-LABEL: srlri_d:
-; CHECK: srlri.d
%a = load <2 x i64>, <2 x i64> * %ptr, align 16
%r = call <2 x i64> @llvm.mips.srlri.d(<2 x i64> %a, i32 3)
store <2 x i64> %r, <2 x i64> * %ptr, align 16
@@ -1018,13 +2258,29 @@ entry:
}
define void @ld_d2(<2 x i64> * %ptr, i8 * %ldptr) {
+; MSA32-LABEL: ld_d2:
+; MSA32: # %bb.0: # %entry
+; MSA32-NEXT: addiu $1, $5, 4096
+; MSA32-NEXT: ld.d $w0, 0($1)
+; MSA32-NEXT: jr $ra
+; MSA32-NEXT: st.d $w0, 0($4)
+;
+; MSA64N32-LABEL: ld_d2:
+; MSA64N32: # %bb.0: # %entry
+; MSA64N32-NEXT: sll $1, $4, 0
+; MSA64N32-NEXT: sll $2, $5, 0
+; MSA64N32-NEXT: addiu $2, $2, 4096
+; MSA64N32-NEXT: ld.d $w0, 0($2)
+; MSA64N32-NEXT: jr $ra
+; MSA64N32-NEXT: st.d $w0, 0($1)
+;
+; MSA64N64-LABEL: ld_d2:
+; MSA64N64: # %bb.0: # %entry
+; MSA64N64-NEXT: daddiu $1, $5, 4096
+; MSA64N64-NEXT: ld.d $w0, 0($1)
+; MSA64N64-NEXT: jr $ra
+; MSA64N64-NEXT: st.d $w0, 0($4)
entry:
-; CHECK-LABEL: ld_d2
-; MSA32: addiu $[[R0:[0-9]]], $5, 4096
-; MSA64N32: sll $[[R1:[0-9]]], $5, 0
-; MSA64N32: addiu $[[R0:[0-9]]], $[[R1]], 4096
-; MSA64N64: daddiu $[[R0:[0-9]]], $5, 4096
-; CHECK: ld.d $w{{[0-9]+}}, 0($[[R0]])
%a = call <2 x i64> @llvm.mips.ld.d(i8* %ldptr, i32 4096)
store <2 x i64> %a, <2 x i64> * %ptr, align 16
ret void
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