[PATCH] D101898: [ARM] Prevent spilling between ldrex/strex pairs

[Tomas Matheson via Phabricator via llvm-commits]

tmatheson created this revision.
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Based on the same for AArch64: 4751cadcca45984d7671e594ce95aed8fe030bf1 <https://reviews.llvm.org/rG4751cadcca45984d7671e594ce95aed8fe030bf1>

At -O0, the fast register allocator may insert spills between the ldrex and
strex instructions inserted by AtomicExpandPass when expanding atomicrmw
instructions in LL/SC loops. To avoid this, expand to cmpxchg loops and
therefore expand the cmpxchg pseudos after register allocation.

Required a tweak to ARMExpandPseudo::ExpandCMP_SWAP to use the 4-byte encoding
of UXT, since the pseudo instruction can be allocated a high register (R8 <https://reviews.llvm.org/source/libcxx/>-R15)
which the 2-byte encoding doesn't support.

The previously committed attempt in D101164 <https://reviews.llvm.org/D101164> had to be reverted due to runtime
failures in the test suites. Rather than spending time fixing that
implementation (adding another implementation of atomic operations and more
divergence between backends) I have chosen to follow the approach taken in
D101163 <https://reviews.llvm.org/D101163>.

Compared to D101164 <https://reviews.llvm.org/D101164>, this patch also fixes the problem for Thumb 2.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D101898

Files:
  llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/test/CodeGen/ARM/atomicrmw_exclusive_monitor_all.ll

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