[PATCH] D101826: [RISCV][VP] Lower VP ISD nodes to RVV instructions

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 added a comment.

Hi @frasercrmck, tests are using `zeroext`, is this for simpler code generation before we are able to combine this case and avoid unnecessary sign extensions?

Other than that LGTM too. Thanks!



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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td:531
 
-  // Handle vnot the same as the vnot.mm pseudoinstruction.
-  def : Pat<(mti.Mask (vnot VR:$rs)),
+  // Handle rvv_vnot the same as the vnot.mm pseudoinstruction.
+  def : Pat<(mti.Mask (rvv_vnot VR:$rs)),
----------------
Now that you're here: I'm not sure there is a `vnot.mm` (I fail to find it in the spec) I think this comment should have said `vmnot.m`, right?


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https://reviews.llvm.org/D101826