[PATCH] D101736: [WebAssembly] Allow DBG_VALUE after terminator in MachineVerifier

[Derek Schuff via Phabricator via llvm-commits]

dschuff added inline comments.


================
Comment at: llvm/lib/CodeGen/MachineVerifier.cpp:803
+  // DBG_VALUE $noreg, $noreg, !"variable", ...
+  if (TM->getTargetTriple().isWasm() && FirstTerminator && MI->isDebugValue() &&
+      MI->getOperand(0).isReg() && MI->getOperand(1).isReg() &&
----------------
aheejin wrote:
> dschuff wrote:
> > I guess the inclusion of `FirstTerminator` means that if there is a `br_if` followed by a `br` or whatever, then we only allow DBG_VALUE after the `br_if` which makes sense.
> > Would this miss the case where there is only one terminator (i.e. just a `br`, in which case it would also be the first terminator), or is `FirstTerminator` not set in that case?
> > 
> `FirstTerminator` is set whenever we've seen a terminator within a BB. There can be multiple terminators; in our case `br_if` followed by `br`, and there will be more in other targets. LLVM's verification rule is after any terminator occurs within a BB, only other terminator instructions can come after that. Does this answer your question? I'm not sure if I understood your question well.
I think it answers my question.
What I was wondering was if we have only an unconditional branch followed by a DBG_VALUE (and no other terminator), that would be still invalid but would be allowed by this code.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101736/new/

https://reviews.llvm.org/D101736