[llvm] 14ca2e5 - [WebAssembly] Mark abs of v2i64 as legal

[Thomas Lively via llvm-commits]

Author: Thomas Lively
Date: 2021-05-04T13:25:32-07:00
New Revision: 14ca2e5e22e7806c77ca3e5b126e888c9b1c4041

URL: https://github.com/llvm/llvm-project/commit/14ca2e5e22e7806c77ca3e5b126e888c9b1c4041
DIFF: https://github.com/llvm/llvm-project/commit/14ca2e5e22e7806c77ca3e5b126e888c9b1c4041.diff

LOG: [WebAssembly] Mark abs of v2i64 as legal

We previously had an ISel pattern for i64x2.abs, but because the ISDNode was not
marked legal for v2i64, the instruction was not being selected.

Differential Revision: https://reviews.llvm.org/D101803

Added: 
    

Modified: 
    llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
    llvm/test/CodeGen/WebAssembly/simd-arith.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index fd36b74e26dd..51e621dbcdc6 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -149,7 +149,7 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
         setOperationAction(Op, T, Legal);
 
     // Support integer abs
-    for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32})
+    for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64})
       setOperationAction(ISD::ABS, T, Legal);
 
     // Custom lower BUILD_VECTORs to minimize number of replace_lanes

diff  --git a/llvm/test/CodeGen/WebAssembly/simd-arith.ll b/llvm/test/CodeGen/WebAssembly/simd-arith.ll
index 0268e8eb50c9..45bf9f7c85db 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-arith.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-arith.ll
@@ -968,6 +968,18 @@ define <2 x i64> @mul_v2i64(<2 x i64> %x, <2 x i64> %y) {
   ret <2 x i64> %a
 }
 
+; CHECK-LABEL: abs_v2i64:
+; NO-SIMD128-NOT: i64x2:
+; SIMD128-NEXT: .functype abs_v2i64 (v128) -> (v128){{$}}
+; SIMD128-NEXT: i64x2.abs $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @abs_v2i64(<2 x i64> %x) {
+  %a = sub <2 x i64> zeroinitializer, %x
+  %b = icmp slt <2 x i64> %x, zeroinitializer
+  %c = select <2 x i1> %b, <2 x i64> %a, <2 x i64> %x
+  ret <2 x i64> %c
+}
+
 ; CHECK-LABEL: neg_v2i64:
 ; NO-SIMD128-NOT: i64x2
 ; SIMD128-NEXT: .functype neg_v2i64 (v128) -> (v128){{$}}