[PATCH] D100430: [AMDGPU][GlobalISel] Widen 1 and 2 byte scalar loads

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp:1180-1182
+        auto WideLoad = B.buildLoadFromOffset(S32, PtrReg, *MMO, 0);
+        auto Mask = B.buildConstant(
+            S32, APInt::getLowBitsSet(S32.getScalarSizeInBits(), MemSize));
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vangthao wrote:
> arsenm wrote:
> > MachineIRBuilder has a buildZExtInReg helper to figure out the mask and create the and for you
> I used this previously but there was an issue with the implementation in buildZExtInReg where it would create a new destination register instead of using the original destination register passed to it. Jay mentioned this bug in a previous comment.
Yes, buildZExtInReg is broken and needs to be fixed. You should fix it and continue using it


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100430/new/

https://reviews.llvm.org/D100430