[PATCH] D101234: GlobalISel: Use DAG call lowering infrastructure in a more compatible way

Tue May 4 11:30:30 PDT 2021

aemerson added inline comments.

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Comment at: llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-reductions.ll:12-14
+  ; CHECK:   [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
+  ; CHECK:   [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<2 x s64>)
+  ; CHECK:   [[VECREDUCE_SEQ_FADD:%[0-9]+]]:_(s32) = G_VECREDUCE_SEQ_FADD [[COPY]](s32), [[BITCAST]](<4 x s32>)
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arsenm wrote:
> aemerson wrote:
> > Why is this changing?
> According to the tablegen calling convention definition, <4 x s32> is supposed to be bitcasted to <2 x s64>. This was silently ignoring this before and directly assigning the physreg to the result type
Ah right, this is <4 x f32> not <4 x i32>.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101234/new/

https://reviews.llvm.org/D101234