[PATCH] D100430: [AMDGPU][GlobalISel] Widen 1 and 2 byte scalar loads

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp:1180-1182
+        auto WideLoad = B.buildLoadFromOffset(S32, PtrReg, *MMO, 0);
+        auto Mask = B.buildConstant(
+            S32, APInt::getLowBitsSet(S32.getScalarSizeInBits(), MemSize));
----------------
MachineIRBuilder has a buildZExtInReg helper to figure out the mask and create the and for you


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp:1182
+        auto Mask = B.buildConstant(
+            S32, APInt::getLowBitsSet(S32.getScalarSizeInBits(), MemSize));
+        B.buildAnd(MI.getOperand(0), WideLoad, Mask);
----------------
S32.getScalarSizeInBits() is a complicated way of just saying 32


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100430/new/

https://reviews.llvm.org/D100430