[llvm] e9edd11 - [Hexagon][test] Migrate llvm-objdump --mv6[0567]t?/--mhvx to --mcpu=hexagonv*/--mattr=+hvx
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Tue May 4 11:00:08 PDT 2021
Author: Fangrui Song
Date: 2021-05-04T11:00:01-07:00
New Revision: e9edd11cda55834cc148798b1692911a5a646ace
URL: https://github.com/llvm/llvm-project/commit/e9edd11cda55834cc148798b1692911a5a646ace
DIFF: https://github.com/llvm/llvm-project/commit/e9edd11cda55834cc148798b1692911a5a646ace.diff
LOG: [Hexagon][test] Migrate llvm-objdump --mv6[0567]t?/--mhvx to --mcpu=hexagonv*/--mattr=+hvx
Added:
Modified:
llvm/test/CodeGen/Hexagon/bug18008.ll
llvm/test/CodeGen/Hexagon/vect-regpairs.ll
llvm/test/MC/Hexagon/align.s
llvm/test/MC/Hexagon/cmpyrw.s
llvm/test/MC/Hexagon/extensions/v67_hvx.s
llvm/test/MC/Hexagon/hvx-double-implies-hvx.s
llvm/test/MC/Hexagon/hvx-swapped-regpairs.s
llvm/test/MC/Hexagon/quad_regs.s
llvm/test/MC/Hexagon/smallcore_dis.s
llvm/test/MC/Hexagon/v60-alu.s
llvm/test/MC/Hexagon/v60-misc.s
llvm/test/MC/Hexagon/v60-permute.s
llvm/test/MC/Hexagon/v60-shift.s
llvm/test/MC/Hexagon/v60-vcmp.s
llvm/test/MC/Hexagon/v60-vmem.s
llvm/test/MC/Hexagon/v60-vmpy-acc.s
llvm/test/MC/Hexagon/v60-vmpy1.s
llvm/test/MC/Hexagon/v60lookup.s
llvm/test/MC/Hexagon/v62_all.s
llvm/test/MC/Hexagon/v65_all.s
llvm/test/MC/Hexagon/v66.s
llvm/test/MC/Hexagon/v67.s
llvm/test/MC/Hexagon/v67_all.s
llvm/test/MC/Hexagon/z-instructions.s
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/Hexagon/bug18008.ll b/llvm/test/CodeGen/Hexagon/bug18008.ll
index 8e83c5e858f55..91707b713c2d9 100644
--- a/llvm/test/CodeGen/Hexagon/bug18008.ll
+++ b/llvm/test/CodeGen/Hexagon/bug18008.ll
@@ -1,4 +1,4 @@
-;RUN: llc -march=hexagon -filetype=obj < %s -o - | llvm-objdump --mv60 --mhvx -d - | FileCheck %s
+;RUN: llc -march=hexagon -filetype=obj < %s -o - | llvm-objdump --mcpu=hexagonv60 --mattr=+hvx -d - | FileCheck %s
; Should not crash! and map to vxor
diff --git a/llvm/test/CodeGen/Hexagon/vect-regpairs.ll b/llvm/test/CodeGen/Hexagon/vect-regpairs.ll
index 7ee2b7fc30c2f..d26c5f74f84de 100644
--- a/llvm/test/CodeGen/Hexagon/vect-regpairs.ll
+++ b/llvm/test/CodeGen/Hexagon/vect-regpairs.ll
@@ -1,5 +1,5 @@
-;RUN: llc -march=hexagon -mcpu=hexagonv66 -mhvx -filetype=obj < %s -o - | llvm-objdump --mv66 --mhvx -d - | FileCheck --check-prefix=CHECK-V66 %s
-;RUN: llc -march=hexagon -mcpu=hexagonv67 -mhvx -filetype=obj < %s -o - | llvm-objdump --mv67 --mhvx -d - | FileCheck --check-prefix=CHECK-V67 %s
+;RUN: llc -march=hexagon -mcpu=hexagonv66 -mhvx -filetype=obj < %s -o - | llvm-objdump --mcpu=hexagonv66 --mattr=+hvx -d - | FileCheck --check-prefix=CHECK-V66 %s
+;RUN: llc -march=hexagon -mcpu=hexagonv67 -mhvx -filetype=obj < %s -o - | llvm-objdump --mcpu=hexagonv67 --mattr=+hvx -d - | FileCheck --check-prefix=CHECK-V67 %s
; Should not attempt to use v<even>:<odd> 'reverse' vector regpairs
; on old or new arches (should not crash).
diff --git a/llvm/test/MC/Hexagon/align.s b/llvm/test/MC/Hexagon/align.s
index 3469b83c21fec..86c723c955772 100644
--- a/llvm/test/MC/Hexagon/align.s
+++ b/llvm/test/MC/Hexagon/align.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -triple=hexagon -filetype=obj -mhvx %s | llvm-objdump --mhvx -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -filetype=obj -mhvx %s | llvm-objdump --mattr=+hvx -d - | FileCheck %s
# Verify that the .align directive emits the proper insn packets.
diff --git a/llvm/test/MC/Hexagon/cmpyrw.s b/llvm/test/MC/Hexagon/cmpyrw.s
index d90739000eea8..c93205f43ab6d 100644
--- a/llvm/test/MC/Hexagon/cmpyrw.s
+++ b/llvm/test/MC/Hexagon/cmpyrw.s
@@ -1,3 +1,3 @@
-# RUN: llvm-mc -arch=hexagon -mv67t -filetype=obj %s | llvm-objdump --mv67t --mattr=+audio -d - | FileCheck %s
+# RUN: llvm-mc -arch=hexagon -mv67t -filetype=obj %s | llvm-objdump --mcpu=hexagonv67t --mattr=+audio -d - | FileCheck %s
r23:22 = cmpyrw(r15:14,r21:20*)
# CHECK: r23:22 = cmpyrw(r15:14,r21:20*)
diff --git a/llvm/test/MC/Hexagon/extensions/v67_hvx.s b/llvm/test/MC/Hexagon/extensions/v67_hvx.s
index ca046f8ae5f13..717401e97bc0c 100644
--- a/llvm/test/MC/Hexagon/extensions/v67_hvx.s
+++ b/llvm/test/MC/Hexagon/extensions/v67_hvx.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv67 -mhvx -filetype=obj %s | llvm-objdump --mcpu=hexagonv67 --mhvx -d - | FileCheck --implicit-check-not='{' %s
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv67 -mhvx -filetype=obj %s | llvm-objdump --mcpu=hexagonv67 --mattr=+hvx -d - | FileCheck --implicit-check-not='{' %s
diff --git a/llvm/test/MC/Hexagon/hvx-double-implies-hvx.s b/llvm/test/MC/Hexagon/hvx-double-implies-hvx.s
index 94d303341b9cc..a2de7e290e8e3 100644
--- a/llvm/test/MC/Hexagon/hvx-double-implies-hvx.s
+++ b/llvm/test/MC/Hexagon/hvx-double-implies-hvx.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -filetype=obj -arch=hexagon -mv65 -mattr=+hvxv65,+hvx-length128b %s | llvm-objdump -d --mhvx - | FileCheck %s
+# RUN: llvm-mc -filetype=obj -arch=hexagon -mv65 -mattr=+hvxv65,+hvx-length128b %s | llvm-objdump -d --mattr=+hvx - | FileCheck %s
# CHECK: vhist
vhist
diff --git a/llvm/test/MC/Hexagon/hvx-swapped-regpairs.s b/llvm/test/MC/Hexagon/hvx-swapped-regpairs.s
index 617b1afff0bd8..6fe66bd66a306 100644
--- a/llvm/test/MC/Hexagon/hvx-swapped-regpairs.s
+++ b/llvm/test/MC/Hexagon/hvx-swapped-regpairs.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -filetype=obj -arch=hexagon -mcpu=hexagonv67 -mhvx %s | llvm-objdump -d --mcpu=hexagonv67 --mhvx - | FileCheck %s
+# RUN: llvm-mc -filetype=obj -arch=hexagon -mcpu=hexagonv67 -mhvx %s | llvm-objdump -d --mcpu=hexagonv67 --mattr=+hvx - | FileCheck %s
# RUN: not llvm-mc -arch=hexagon -mcpu=hexagonv65 -mhvx -filetype=asm %s 2>%t; FileCheck --check-prefix=CHECK-V65 --implicit-check-not="error:" %s <%t
v1:0.w = vadd(v0.h, v1.h) // Normal
diff --git a/llvm/test/MC/Hexagon/quad_regs.s b/llvm/test/MC/Hexagon/quad_regs.s
index 7053a292c630b..3041d60307ecd 100644
--- a/llvm/test/MC/Hexagon/quad_regs.s
+++ b/llvm/test/MC/Hexagon/quad_regs.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv66 -mhvx -filetype=obj %s | llvm-objdump --mcpu=hexagonv66 --mhvx -d - | FileCheck %s
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv66 -mhvx -filetype=obj %s | llvm-objdump --mcpu=hexagonv66 --mattr=+hvx -d - | FileCheck %s
# Test for quad register parsing and printing
# CHECK: { v3:0.w = vrmpyz(v0.b,r0.b) }
diff --git a/llvm/test/MC/Hexagon/smallcore_dis.s b/llvm/test/MC/Hexagon/smallcore_dis.s
index d2b17ba1caa0a..1a61ec16e8cec 100644
--- a/llvm/test/MC/Hexagon/smallcore_dis.s
+++ b/llvm/test/MC/Hexagon/smallcore_dis.s
@@ -1,5 +1,4 @@
# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv67t -filetype=obj %s | llvm-objdump -d - | FileCheck %s
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv67t -filetype=obj %s | llvm-objdump --mv67t -d - | FileCheck %s
# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv67t -filetype=obj %s | llvm-objdump --mcpu=hexagonv67t -d - | FileCheck %s
.text
diff --git a/llvm/test/MC/Hexagon/v60-alu.s b/llvm/test/MC/Hexagon/v60-alu.s
index 7c32d86117bb1..8cd31b2b48686 100644
--- a/llvm/test/MC/Hexagon/v60-alu.s
+++ b/llvm/test/MC/Hexagon/v60-alu.s
@@ -1,5 +1,5 @@
#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \
-#RUN: llvm-objdump --triple=hexagon --mcpu=hexagonv60 --mhvx -d - | \
+#RUN: llvm-objdump --triple=hexagon --mcpu=hexagonv60 --mattr=+hvx -d - | \
#RUN: FileCheck %s
#CHECK: 1ce2cbd7 { v23.w = vavg(v11.w,{{ *}}v2.w):rnd }
diff --git a/llvm/test/MC/Hexagon/v60-misc.s b/llvm/test/MC/Hexagon/v60-misc.s
index 1e10ab17bad10..5f4bc3308f073 100644
--- a/llvm/test/MC/Hexagon/v60-misc.s
+++ b/llvm/test/MC/Hexagon/v60-misc.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 -mhvx -filetype=obj %s | llvm-objdump --arch=hexagon --mcpu=hexagonv60 --mhvx -d - | FileCheck %s
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 -mhvx -filetype=obj %s | llvm-objdump --arch=hexagon --mcpu=hexagonv60 --mattr=+hvx -d - | FileCheck %s
.L0:
diff --git a/llvm/test/MC/Hexagon/v60-permute.s b/llvm/test/MC/Hexagon/v60-permute.s
index b46d8cff847ff..be0d2d9a640b5 100644
--- a/llvm/test/MC/Hexagon/v60-permute.s
+++ b/llvm/test/MC/Hexagon/v60-permute.s
@@ -1,5 +1,5 @@
#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \
-#RUN: llvm-objdump --triple=hexagon --mcpu=hexagonv60 --mhvx -d - | \
+#RUN: llvm-objdump --triple=hexagon --mcpu=hexagonv60 --mattr=+hvx -d - | \
#RUN: FileCheck %s
#CHECK: 1fd2d5cf { v15.b = vpack(v21.h{{ *}},{{ *}}v18.h):sat }
diff --git a/llvm/test/MC/Hexagon/v60-shift.s b/llvm/test/MC/Hexagon/v60-shift.s
index ea913032e10a5..4ffde35e3fc19 100644
--- a/llvm/test/MC/Hexagon/v60-shift.s
+++ b/llvm/test/MC/Hexagon/v60-shift.s
@@ -1,5 +1,5 @@
#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \
-#RUN: llvm-objdump --triple=hexagon --mcpu=hexagonv60 --mhvx -d - | \
+#RUN: llvm-objdump --triple=hexagon --mcpu=hexagonv60 --mattr=+hvx -d - | \
#RUN: FileCheck %s
#CHECK: 198fd829 { v9.uw = vlsr(v24.uw,{{ *}}r15) }
diff --git a/llvm/test/MC/Hexagon/v60-vcmp.s b/llvm/test/MC/Hexagon/v60-vcmp.s
index 1206acceb67e9..79988c7d38f72 100644
--- a/llvm/test/MC/Hexagon/v60-vcmp.s
+++ b/llvm/test/MC/Hexagon/v60-vcmp.s
@@ -1,5 +1,5 @@
#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \
-#RUN: llvm-objdump --triple=hexagon --mcpu=hexagonv60 --mhvx -d - | \
+#RUN: llvm-objdump --triple=hexagon --mcpu=hexagonv60 --mattr=+hvx -d - | \
#RUN: FileCheck %s
#CHECK: 1c81f142 { q2 |= vcmp.eq(v17.b{{ *}},{{ *}}v1.b) }
diff --git a/llvm/test/MC/Hexagon/v60-vmem.s b/llvm/test/MC/Hexagon/v60-vmem.s
index c484c41e05ea3..1071ebf47f8f3 100644
--- a/llvm/test/MC/Hexagon/v60-vmem.s
+++ b/llvm/test/MC/Hexagon/v60-vmem.s
@@ -1,5 +1,5 @@
#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \
-#RUN: llvm-objdump --triple=hexagon --mcpu=hexagonv60 --mhvx -d - | \
+#RUN: llvm-objdump --triple=hexagon --mcpu=hexagonv60 --mattr=+hvx -d - | \
#RUN: FileCheck %s
#CHECK: 292cc11b { vmem(r12++#1) = v27 }
diff --git a/llvm/test/MC/Hexagon/v60-vmpy-acc.s b/llvm/test/MC/Hexagon/v60-vmpy-acc.s
index ae70292934012..0606bf6bd8ef3 100644
--- a/llvm/test/MC/Hexagon/v60-vmpy-acc.s
+++ b/llvm/test/MC/Hexagon/v60-vmpy-acc.s
@@ -1,5 +1,5 @@
#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \
-#RUN: llvm-objdump --triple=hexagon --mcpu=hexagonv60 --mhvx -d - | \
+#RUN: llvm-objdump --triple=hexagon --mcpu=hexagonv60 --mattr=+hvx -d - | \
#RUN: FileCheck %s
#CHECK: 1936ee37 { v23.w += vdmpy(v15:14.h,r22.uh,#1):sat }
diff --git a/llvm/test/MC/Hexagon/v60-vmpy1.s b/llvm/test/MC/Hexagon/v60-vmpy1.s
index 19d03ede0b149..7168ef5cda2d5 100644
--- a/llvm/test/MC/Hexagon/v60-vmpy1.s
+++ b/llvm/test/MC/Hexagon/v60-vmpy1.s
@@ -1,5 +1,5 @@
#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \
-#RUN: llvm-objdump --triple=hexagon --mcpu=hexagonv60 --mhvx -d - | \
+#RUN: llvm-objdump --triple=hexagon --mcpu=hexagonv60 --mattr=+hvx -d - | \
#RUN: FileCheck %s
#CHECK: 1939c223 { v3.w = vdmpy(v3:2.h,{{ *}}r25.uh,{{ *}}#1):sat }
diff --git a/llvm/test/MC/Hexagon/v60lookup.s b/llvm/test/MC/Hexagon/v60lookup.s
index dc3d7939fb768..fa241fa5bb8e4 100644
--- a/llvm/test/MC/Hexagon/v60lookup.s
+++ b/llvm/test/MC/Hexagon/v60lookup.s
@@ -1,5 +1,5 @@
#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \
-#RUN: llvm-objdump --triple=hexagon --mcpu=hexagonv60 --mhvx -d - | \
+#RUN: llvm-objdump --triple=hexagon --mcpu=hexagonv60 --mattr=+hvx -d - | \
#RUN: FileCheck %s
V31.b = vlut32(V29.b, V15.b, R1)
diff --git a/llvm/test/MC/Hexagon/v62_all.s b/llvm/test/MC/Hexagon/v62_all.s
index b34b6f919e36c..c0eae838d769e 100644
--- a/llvm/test/MC/Hexagon/v62_all.s
+++ b/llvm/test/MC/Hexagon/v62_all.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj -mhvx %s | llvm-objdump --arch=hexagon --mcpu=hexagonv62 --mhvx -d - | FileCheck %s
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj -mhvx %s | llvm-objdump --arch=hexagon --mcpu=hexagonv62 --mattr=+hvx -d - | FileCheck %s
// V6_lvsplatb
// Vd32.b=vsplat(Rt32)
diff --git a/llvm/test/MC/Hexagon/v65_all.s b/llvm/test/MC/Hexagon/v65_all.s
index 0c3412a984805..0a7331173f7fe 100644
--- a/llvm/test/MC/Hexagon/v65_all.s
+++ b/llvm/test/MC/Hexagon/v65_all.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mv65 -mhvx -filetype=obj %s | llvm-objdump --mv65 --mhvx -d - | FileCheck %s
+# RUN: llvm-mc -arch=hexagon -mv65 -mhvx -filetype=obj %s | llvm-objdump --mcpu=hexagonv65 --mattr=+hvx -d - | FileCheck %s
// Warning: This file is auto generated by mktest.py. Do not edit!
// Created on: 2016-06-01 @ 17:33:01
diff --git a/llvm/test/MC/Hexagon/v66.s b/llvm/test/MC/Hexagon/v66.s
index f02dc1ef762bd..c692a5953f7fe 100644
--- a/llvm/test/MC/Hexagon/v66.s
+++ b/llvm/test/MC/Hexagon/v66.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv66 -mhvx -filetype=obj %s | llvm-objdump --mcpu=hexagonv66 --mhvx -d - | FileCheck %s
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv66 -mhvx -filetype=obj %s | llvm-objdump --mcpu=hexagonv66 --mattr=+hvx -d - | FileCheck %s
# CHECK: 1d8362e4 { v4.w = vsatdw(v2.w,v3.w)
{
diff --git a/llvm/test/MC/Hexagon/v67.s b/llvm/test/MC/Hexagon/v67.s
index 059a08f61b64a..6ca632ed37bea 100644
--- a/llvm/test/MC/Hexagon/v67.s
+++ b/llvm/test/MC/Hexagon/v67.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mv67 -mattr=+hvx,+hvx-length128B -filetype=obj %s | llvm-objdump --mhvx=v66 -d - | FileCheck %s
+# RUN: llvm-mc -arch=hexagon -mv67 -mattr=+hvx,+hvx-length128B -filetype=obj %s | llvm-objdump --mcpu=hexagonv67 --mattr=+hvx -d - | FileCheck %s
# CHECK: 1a81e0e2 { v2.uw = vrotr(v0.uw,v1.uw) }
v2.uw=vrotr(v0.uw, v1.uw)
diff --git a/llvm/test/MC/Hexagon/v67_all.s b/llvm/test/MC/Hexagon/v67_all.s
index 065001db353c2..e7428a3a9a20f 100644
--- a/llvm/test/MC/Hexagon/v67_all.s
+++ b/llvm/test/MC/Hexagon/v67_all.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mv67 -mhvx -filetype=obj %s | llvm-objdump --mhvx=v66 -d - | FileCheck %s
+# RUN: llvm-mc -arch=hexagon -mv67 -mhvx -filetype=obj %s | llvm-objdump --mcpu=hexagonv67 --mattr=+hvx -d - | FileCheck %s
# CHECK: { v3:0.w = vrmpyz(v0.b,r0.ub) }
V3:0.w=vrmpyz(v0.b,r0.ub)
diff --git a/llvm/test/MC/Hexagon/z-instructions.s b/llvm/test/MC/Hexagon/z-instructions.s
index 308e40ccade9f..34c0fbdeafdc7 100644
--- a/llvm/test/MC/Hexagon/z-instructions.s
+++ b/llvm/test/MC/Hexagon/z-instructions.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv66 -mhvx -filetype=obj %s | llvm-objdump --mcpu=hexagonv66 --mhvx -d - | FileCheck --implicit-check-not='{' %s
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv66 -mhvx -filetype=obj %s | llvm-objdump --mcpu=hexagonv66 --mattr=+hvx -d - | FileCheck --implicit-check-not='{' %s
# CHECK: 2d00c000 { z = vmem(r0++#0) }
z = vmem(r0++#0)
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