[PATCH] D101830: AMDGPU: Correct const_index_stride for wave 32 for PAL API

[David Stuttard via Phabricator via llvm-commits]

dstuttard updated this revision to Diff 342710.
dstuttard added a comment.

API -> ABI


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101830/new/

https://reviews.llvm.org/D101830

Files:
  llvm/lib/Target/AMDGPU/SIFrameLowering.cpp


Index: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+++ llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
@@ -525,6 +525,7 @@
     // The pointer to the GIT is formed from the offset passed in and either
     // the amdgpu-git-ptr-high function attribute or the top part of the PC
     Register Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1);
+    Register Rsrc03 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3);
 
     buildGitPtr(MBB, I, DL, TII, Rsrc01);
 
@@ -546,6 +547,15 @@
       .addImm(0) // cpol
       .addReg(ScratchRsrcReg, RegState::ImplicitDefine)
       .addMemOperand(MMO);
+
+    // If we are in a wave32 shader we have to modify the const_index_stride to
+    // b10 We can't rely on the driver setting this for us since there are often
+    // multiple shaders with different wave sizes
+    // TODO: convert to using SCRATCH instructions or multiple SRD buffers
+    if (ST.isWave32()) {
+      const MCInstrDesc &SAndB32 = TII->get(AMDGPU::S_AND_B32);
+      BuildMI(MBB, I, DL, SAndB32, Rsrc03).addReg(Rsrc03).addImm(0xffdfffff);
+    }
   } else if (ST.isMesaGfxShader(Fn) || !PreloadedScratchRsrcReg) {
     assert(!ST.isAmdHsaOrMesa(Fn));
     const MCInstrDesc &SMovB32 = TII->get(AMDGPU::S_MOV_B32);


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