[PATCH] D101831: [AArch64][SVE] Add unpredicated vector BIC ISD node

[Bradley Smith via Phabricator via llvm-commits]

bsmith created this revision.
bsmith added reviewers: paulwalker-arm, peterwaller-arm, joechrisellis, sdesmalen.
Herald added subscribers: psnobl, hiraditya, kristof.beyls, tschuett.
Herald added a reviewer: efriedma.
bsmith requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Addition of this node allows us to better utilize the different forms of
the SVE BIC instructions, including using the alias to an AND (immediate).

Depends on D101828 <https://reviews.llvm.org/D101828>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D101831

Files:
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-logical-imm.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-unpred-form.ll

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