[PATCH] D101820: [AArch64][SVE] Extend svdup->insertelement instcombine pattern to support ...

[Joe Ellis via Phabricator via llvm-commits]

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ptrue patterns other other than VL1.

The current algorithm identifies svdup intrinsic calls where the
predicate is a ptrue with the pattern VL1. It is possible to also
perform this optimisation for ptrue patterns in the range VL1 to VL8
inclusive.

Suppose we have a svdup intrinsic call:

  svdup (vec, (ptrue pat), elm)

If pat is VL1, we perform the optimisation as before. Else, if pat is in
the range VL2 to VL8 inclusive, we check that the only uses of this
svdup are other svdups that overwrite every vector element except for
one -- if so, we can replace the svdup call with an insertelement
instruction. In any other case, we bail out.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D101820

Files:
  llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
  llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-dup.ll

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