[PATCH] D101687: [AArch64] Fold CSEL x, x, cc -> x
Dave Green via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon May 3 09:34:46 PDT 2021
This revision was automatically updated to reflect the committed changes.
Closed by commit rG966435daf969: [AArch64] Fold CSEL x, x, cc -> x (authored by dmgreen).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D101687/new/
https://reviews.llvm.org/D101687
Files:
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.h
llvm/test/CodeGen/AArch64/srem-seteq.ll
Index: llvm/test/CodeGen/AArch64/srem-seteq.ll
===================================================================
--- llvm/test/CodeGen/AArch64/srem-seteq.ll
+++ llvm/test/CodeGen/AArch64/srem-seteq.ll
@@ -269,10 +269,7 @@
define i32 @test_srem_allones(i32 %X) nounwind {
; CHECK-LABEL: test_srem_allones:
; CHECK: // %bb.0:
-; CHECK-NEXT: cmp w0, #0 // =0
-; CHECK-NEXT: csel w8, w0, w0, lt
-; CHECK-NEXT: cmp w0, w8
-; CHECK-NEXT: cset w0, eq
+; CHECK-NEXT: mov w0, #1
; CHECK-NEXT: ret
%srem = srem i32 %X, 4294967295
%cmp = icmp eq i32 %srem, 0
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.h
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -66,7 +66,6 @@
RET_FLAG, // Return with a flag operand. Operand 0 is the chain operand.
BRCOND, // Conditional branch instruction; "b.cond".
CSEL,
- FCSEL, // Conditional move instruction.
CSINV, // Conditional select invert.
CSNEG, // Conditional select negate.
CSINC, // Conditional select increment.
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1806,7 +1806,6 @@
MAKE_CASE(AArch64ISD::RET_FLAG)
MAKE_CASE(AArch64ISD::BRCOND)
MAKE_CASE(AArch64ISD::CSEL)
- MAKE_CASE(AArch64ISD::FCSEL)
MAKE_CASE(AArch64ISD::CSINV)
MAKE_CASE(AArch64ISD::CSNEG)
MAKE_CASE(AArch64ISD::CSINC)
@@ -15156,6 +15155,17 @@
return SDValue();
}
+// Optimize CSEL instructions
+static SDValue performCSELCombine(SDNode *N,
+ TargetLowering::DAGCombinerInfo &DCI,
+ SelectionDAG &DAG) {
+ // CSEL x, x, cc -> x
+ if (N->getOperand(0) == N->getOperand(1))
+ return N->getOperand(0);
+
+ return performCONDCombine(N, DCI, DAG, 2, 3);
+}
+
// Optimize some simple tbz/tbnz cases. Returns the new operand and bit to test
// as well as whether the test should be inverted. This code is required to
// catch these cases (as opposed to standard dag combines) because
@@ -15949,7 +15959,7 @@
case AArch64ISD::TBZ:
return performTBZCombine(N, DCI, DAG);
case AArch64ISD::CSEL:
- return performCONDCombine(N, DCI, DAG, 2, 3);
+ return performCSELCombine(N, DCI, DAG);
case AArch64ISD::DUP:
return performPostLD1Combine(N, DCI, false);
case AArch64ISD::NVCAST:
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