[PATCH] D101591: [AMDGPU] Improve global SADDR selection

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec created this revision.
rampitec added reviewers: arsenm, foad, Joe_Nash.
Herald added subscribers: kerbowa, jfb, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl.
rampitec requested review of this revision.
Herald added a subscriber: wdng.
Herald added a project: LLVM.

An address can be a uniform sum of two i64 bit values.
That regularly happens in a loop where index is an induction
variable promoted to 64 bit by the LSR. We can materialize
zero in a VGPR and still use SADDR form of the load.


https://reviews.llvm.org/D101591

Files:
  llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
  llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
  llvm/test/CodeGen/AMDGPU/global_atomics.ll
  llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
  llvm/test/CodeGen/AMDGPU/offset-split-global.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D101591.341719.patch
Type: text/x-patch
Size: 99675 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210430/b58b254a/attachment-0001.bin>