[PATCH] D100932: [RISCV] CleanupVSETVLI: Add phase to remove redundant VSETVLI instructions across basic blocks

[ShihPo Hung via Phabricator via llvm-commits]

arcbbb updated this revision to Diff 342319.
arcbbb added a comment.

address Roger's comment

  i. add MIR tests.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100932/new/

https://reviews.llvm.org/D100932

Files:
  llvm/lib/Target/RISCV/RISCVCleanupVSETVLI.cpp
  llvm/lib/Target/RISCV/RISCVCleanupVSETVLI.h
  llvm/test/CodeGen/RISCV/rvv/cleanup-vsetvli-global.mir
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

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