[llvm] 2b93c9c - [X86] AMD Zen 3 Scheduler Model
Roman Lebedev via llvm-commits
llvm-commits at lists.llvm.org
Sat May 1 12:11:10 PDT 2021
Author: Roman Lebedev
Date: 2021-05-01T22:08:13+03:00
New Revision: 2b93c9c16c586c26d20a5166c6ffbd71bc85b2e6
URL: https://github.com/llvm/llvm-project/commit/2b93c9c16c586c26d20a5166c6ffbd71bc85b2e6
DIFF: https://github.com/llvm/llvm-project/commit/2b93c9c16c586c26d20a5166c6ffbd71bc85b2e6.diff
LOG: [X86] AMD Zen 3 Scheduler Model
Introduce basic schedule model for AMD Zen 3 CPU's, a.k.a `znver3`.
This is fully built from scratch, from llvm-mca measurements
and documented reference materials.
Nothing was copied from `znver2`/`znver1`.
I believe this is in a reasonable state of completion for inclusion,
probably better than D52779 `bdver2` was :)
Namely:
* uops are pretty spot-on (at least what llvm-mca can measure)
{F16422596}
* latency is also pretty spot-on (at least what llvm-mca can measure)
{F16422601}
* throughput is within reason
{F16422607}
I haven't run much benchmarks with this,
however RawSpeed benchmarks says this is beneficial:
{F16603978}
{F16604029}
I'll call out the obvious problems there:
* i didn't really bother with X87 instructions
* i didn't really bother with obviously-microcoded/system instructions
* There are large discrepancy in throughput for `mr` and `rm` instructions.
I'm not really sure if it's a modelling defect that needs to be fixed,
or it's a defect of measurments.
* Pipe distributions are probably bad :)
I can't do much here until AMD allows that to be fixed
by documenting the appropriate counters and updating libpfm
That being said, as @RKSimon notes:
>>! In D94395#2647381, @RKSimon wrote:
> I'll mention again that all the znver* models appear to be very inaccurate wrt SIMD/FPU instructions <...>
so how much worse this could possibly be?!
Things that aren't there:
* Various tunings: zero idioms, etc. That is follow-ups.
Differential Revision: https://reviews.llvm.org/D94395
Added:
llvm/lib/Target/X86/X86ScheduleZnver3.td
llvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update-2.s
llvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update-3.s
llvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update-4.s
llvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update-5.s
llvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update-6.s
llvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update-7.s
llvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-adx.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-aes.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-avx1.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-avx2.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-bmi1.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-bmi2.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-clflushopt.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-clzero.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-cmov.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-cmpxchg.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-f16c.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-fma.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-fsgsbase.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-lea.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-lzcnt.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-mmx.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-movbe.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-mwaitx.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-pclmul.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-popcnt.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-prefetchw.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-rdrand.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-rdseed.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-sha.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-sse1.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-sse2.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-sse3.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-sse41.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-sse42.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-sse4a.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-ssse3.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-x86_32.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-x86_64.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-x87.s
Modified:
llvm/lib/Target/X86/X86.td
llvm/lib/Target/X86/X86PfmCounters.td
llvm/test/CodeGen/X86/slow-unaligned-mem.ll
llvm/test/CodeGen/X86/x86-64-double-shifts-var.ll
llvm/test/tools/llvm-mca/X86/cpus.s
llvm/test/tools/llvm-mca/X86/in-order-cpu.s
llvm/test/tools/llvm-mca/X86/read-after-ld-1.s
llvm/test/tools/llvm-mca/X86/register-file-statistics.s
llvm/test/tools/llvm-mca/X86/scheduler-queue-usage.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index b47190a3faef1..1af007f093830 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -555,6 +555,7 @@ include "X86SchedBroadwell.td"
include "X86ScheduleSLM.td"
include "X86ScheduleZnver1.td"
include "X86ScheduleZnver2.td"
+include "X86ScheduleZnver3.td"
include "X86ScheduleBdVer2.td"
include "X86ScheduleBtVer2.td"
include "X86SchedSkylakeClient.td"
@@ -1382,7 +1383,7 @@ def : ProcModel<"znver1", Znver1Model, ProcessorFeatures.ZNFeatures,
ProcessorFeatures.ZNTuning>;
def : ProcModel<"znver2", Znver2Model, ProcessorFeatures.ZN2Features,
ProcessorFeatures.ZN2Tuning>;
-def : ProcModel<"znver3", Znver2Model, ProcessorFeatures.ZN3Features,
+def : ProcModel<"znver3", Znver3Model, ProcessorFeatures.ZN3Features,
ProcessorFeatures.ZN3Tuning>;
def : Proc<"geode", [FeatureX87, FeatureCMPXCHG8B, Feature3DNowA],
diff --git a/llvm/lib/Target/X86/X86PfmCounters.td b/llvm/lib/Target/X86/X86PfmCounters.td
index 833013fb69f3f..3844667ccc748 100644
--- a/llvm/lib/Target/X86/X86PfmCounters.td
+++ b/llvm/lib/Target/X86/X86PfmCounters.td
@@ -233,3 +233,16 @@ def ZnVer2PfmCounters : ProcPfmCounters {
];
}
def : PfmCountersBinding<"znver2", ZnVer2PfmCounters>;
+
+def ZnVer3PfmCounters : ProcPfmCounters {
+ let CycleCounter = PfmCounter<"cycles_not_in_halt">;
+ let UopsCounter = PfmCounter<"retired_ops">;
+ let IssueCounters = [
+ PfmIssueCounter<"Zn3Int", "ops_type_dispatched_from_decoder:int_disp_retire_mode">,
+ PfmIssueCounter<"Zn3FPU", "ops_type_dispatched_from_decoder:fp_disp_retire_mode">,
+ PfmIssueCounter<"Zn3Load", "ls_dispatch:ld_dispatch">,
+ PfmIssueCounter<"Zn3Store", "ls_dispatch:store_dispatch">,
+ PfmIssueCounter<"Zn3Divider", "div_op_count">
+ ];
+}
+def : PfmCountersBinding<"znver3", ZnVer3PfmCounters>;
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver3.td b/llvm/lib/Target/X86/X86ScheduleZnver3.td
new file mode 100644
index 0000000000000..1576b527b2d3d
--- /dev/null
+++ b/llvm/lib/Target/X86/X86ScheduleZnver3.td
@@ -0,0 +1,1455 @@
+//=- X86ScheduleZnver3.td - X86 Znver3 Scheduling ------------*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the machine model for Znver3 to support instruction
+// scheduling and other instruction cost heuristics.
+// Based on:
+// * AMD Software Optimization Guide for AMD Family 19h Processors.
+// https://www.amd.com/system/files/TechDocs/56665.zip
+// * The microarchitecture of Intel, AMD and VIA CPUs, By Agner Fog
+// http://www.agner.org/optimize/microarchitecture.pdf
+// * AMD Zen 3 Ryzen Deep Dive Review
+// https://www.anandtech.com/show/16214/
+//===----------------------------------------------------------------------===//
+
+def Znver3Model : SchedMachineModel {
+ // AMD SOG 19h, 2.9.6 Dispatch
+ // The processor may dispatch up to 6 macro ops per cycle
+ // into the execution engine.
+ let IssueWidth = 6;
+ // AMD SOG 19h, 2.10.3
+ // The retire control unit (RCU) tracks the completion status of all
+ // outstanding operations (integer, load/store, and floating-point) and is
+ // the final arbiter for exception processing and recovery.
+ // The unit can receive up to 6 macro ops dispatched per cycle and track up
+ // to 256 macro ops in-flight in non-SMT mode or 128 per thread in SMT mode.
+ let MicroOpBufferSize = 256;
+ // AMD SOG 19h, 2.9.1 Op Cache
+ // The op cache is organized as an associative cache with 64 sets and 8 ways.
+ // At each set-way intersection is an entry containing up to 8 macro ops.
+ // The maximum capacity of the op cache is 4K ops.
+ // Agner, 22.5 µop cache
+ // The size of the µop cache is big enough for holding most critical loops.
+ let LoopMicroOpBufferSize = 4096;
+ // AMD SOG 19h, 2.6.2 L1 Data Cache
+ // The L1 data cache has a 4- or 5- cycle integer load-to-use latency.
+ // AMD SOG 19h, 2.12 L1 Data Cache
+ // The AGU and LS pipelines are optimized for simple address generation modes.
+ // <...> and can achieve 4-cycle load-to-use integer load latency.
+ let LoadLatency = 4;
+ // AMD SOG 19h, 2.12 L1 Data Cache
+ // The AGU and LS pipelines are optimized for simple address generation modes.
+ // <...> and can achieve <...> 7-cycle load-to-use FP load latency.
+ int VecLoadLatency = 7;
+ // Latency of a simple store operation.
+ int StoreLatency = 1;
+ // FIXME
+ let HighLatency = 25; // FIXME: any better choice?
+ // AMD SOG 19h, 2.8 Optimizing Branching
+ // The branch misprediction penalty is in the range from 11 to 18 cycles,
+ // <...>. The common case penalty is 13 cycles.
+ let MispredictPenalty = 13;
+
+ let PostRAScheduler = 1; // Enable Post RegAlloc Scheduler pass.
+
+ // FIXME: This variable is required for incomplete model.
+ // We haven't catered all instructions.
+ // So, we reset the value of this variable so as to
+ // say that the model is incomplete.
+ let CompleteModel = 0;
+}
+
+let SchedModel = Znver3Model in {
+
+
+//===----------------------------------------------------------------------===//
+// RCU
+//===----------------------------------------------------------------------===//
+
+// AMD SOG 19h, 2.10.3 Retire Control Unit
+// The unit can receive up to 6 macro ops dispatched per cycle and track up to
+// 256 macro ops in-flight in non-SMT mode or 128 per thread in SMT mode. <...>
+// The retire unit handles in-order commit of up to eight macro ops per cycle.
+def Zn3RCU : RetireControlUnit<Znver3Model.MicroOpBufferSize, 8>;
+
+//===----------------------------------------------------------------------===//
+// Units
+//===----------------------------------------------------------------------===//
+
+// There are total of three Units, each one with it's own schedulers.
+
+//===----------------------------------------------------------------------===//
+// Integer Execution Unit
+//
+
+// AMD SOG 19h, 2.4 Superscalar Organization
+// The processor uses four decoupled independent integer scheduler queues,
+// each one servicing one ALU pipeline and one or two other pipelines
+
+//
+// Execution pipes
+//===----------------------------------------------------------------------===//
+
+// AMD SOG 19h, 2.10.2 Execution Units
+// The processor contains 4 general purpose integer execution pipes.
+// Each pipe has an ALU capable of general purpose integer operations.
+def Zn3ALU0 : ProcResource<1>;
+def Zn3ALU1 : ProcResource<1>;
+def Zn3ALU2 : ProcResource<1>;
+def Zn3ALU3 : ProcResource<1>;
+
+// AMD SOG 19h, 2.10.2 Execution Units
+// There is also a separate branch execution unit.
+def Zn3BRU1 : ProcResource<1>;
+
+// AMD SOG 19h, 2.10.2 Execution Units
+// There are three Address Generation Units (AGUs) for all load and store
+// address generation. There are also 3 store data movement units
+// associated with the same schedulers as the AGUs.
+def Zn3AGU0 : ProcResource<1>;
+def Zn3AGU1 : ProcResource<1>;
+def Zn3AGU2 : ProcResource<1>;
+
+//
+// Execution Units
+//===----------------------------------------------------------------------===//
+
+// AMD SOG 19h, 2.10.2 Execution Units
+// ALU0 additionally has divide <...> execution capability.
+defvar Zn3Divider = Zn3ALU0;
+
+// AMD SOG 19h, 2.10.2 Execution Units
+// ALU0 additionally has <...> branch execution capability.
+defvar Zn3BRU0 = Zn3ALU0;
+
+// Integer Multiplication issued on ALU1.
+defvar Zn3Multiplier = Zn3ALU1;
+
+// Execution pipeline grouping
+//===----------------------------------------------------------------------===//
+
+// General ALU operations
+def Zn3ALU0123 : ProcResGroup<[Zn3ALU0, Zn3ALU1, Zn3ALU2, Zn3ALU3]>;
+
+// General AGU operations
+def Zn3AGU012 : ProcResGroup<[Zn3AGU0, Zn3AGU1, Zn3AGU2]>;
+
+// Control flow: jumps, calls
+def Zn3BRU01 : ProcResGroup<[Zn3BRU0, Zn3BRU1]>;
+
+// Everything that isn't control flow, but still needs to access CC register,
+// namely: conditional moves, SETcc.
+def Zn3ALU03 : ProcResGroup<[Zn3ALU0, Zn3ALU3]>;
+
+// Zn3ALU1 handles complex bit twiddling: CRC/PDEP/PEXT
+
+// Simple bit twiddling: bit test, shift/rotate, bit extraction
+def Zn3ALU12 : ProcResGroup<[Zn3ALU1, Zn3ALU2]>;
+
+
+//
+// Scheduling
+//===----------------------------------------------------------------------===//
+
+// AMD SOG 19h, 2.10.3 Retire Control Unit
+// The integer physical register file (PRF) consists of 192 registers.
+def Zn3IntegerPRF : RegisterFile<192, [GR64, CCR]>;
+
+// anandtech, The integer scheduler has a 4*24 entry macro op capacity.
+// AMD SOG 19h, 2.10.1 Schedulers
+// The schedulers can receive up to six macro ops per cycle, with a limit of
+// two per scheduler. Each scheduler can issue one micro op per cycle into
+// each of its associated pipelines
+// FIXME: these are 4 separate schedulers, not a single big one.
+def Zn3Int : ProcResGroup<[Zn3ALU0, Zn3AGU0, Zn3BRU0, // scheduler 0
+ Zn3ALU1, Zn3AGU1, // scheduler 1
+ Zn3ALU2, Zn3AGU2, // scheduler 2
+ Zn3ALU3, Zn3BRU1 // scheduler 3
+ ]> {
+ let BufferSize = !mul(4, 24);
+}
+
+
+//===----------------------------------------------------------------------===//
+// Floating-Point Unit
+//
+
+// AMD SOG 19h, 2.4 Superscalar Organization
+// The processor uses <...> two decoupled independent floating point schedulers
+// each servicing two FP pipelines and one store or FP-to-integer pipeline.
+
+//
+// Execution pipes
+//===----------------------------------------------------------------------===//
+
+// AMD SOG 19h, 2.10.1 Schedulers
+// <...>, and six FPU pipes.
+// Agner, 22.10 Floating point execution pipes
+// There are six floating point/vector execution pipes,
+def Zn3FPP0 : ProcResource<1>;
+def Zn3FPP1 : ProcResource<1>;
+def Zn3FPP2 : ProcResource<1>;
+def Zn3FPP3 : ProcResource<1>;
+def Zn3FPP45 : ProcResource<2>;
+
+//
+// Execution Units
+//===----------------------------------------------------------------------===//
+// AMD SOG 19h, 2.11.1 Floating Point Execution Resources
+
+// (v)FMUL*, (v)FMA*, Floating Point Compares, Blendv(DQ)
+defvar Zn3FPFMul0 = Zn3FPP0;
+defvar Zn3FPFMul1 = Zn3FPP1;
+
+// (v)FADD*
+defvar Zn3FPFAdd0 = Zn3FPP2;
+defvar Zn3FPFAdd1 = Zn3FPP3;
+
+// All convert operations except pack/unpack
+defvar Zn3FPFCvt0 = Zn3FPP2;
+defvar Zn3FPFCvt1 = Zn3FPP3;
+
+// All Divide and Square Root except Reciprocal Approximation
+// AMD SOG 19h, 2.11.1 Floating Point Execution Resources
+// FDIV unit can support 2 simultaneous operations in flight
+// even though it occupies a single pipe.
+// FIXME: BufferSize=2 ?
+defvar Zn3FPFDiv = Zn3FPP1;
+
+// Moves and Logical operations on Floating Point Data Types
+defvar Zn3FPFMisc0 = Zn3FPP0;
+defvar Zn3FPFMisc1 = Zn3FPP1;
+defvar Zn3FPFMisc2 = Zn3FPP2;
+defvar Zn3FPFMisc3 = Zn3FPP3;
+
+// Integer Adds, Subtracts, and Compares
+// Some complex VADD operations are not available in all pipes.
+defvar Zn3FPVAdd0 = Zn3FPP0;
+defvar Zn3FPVAdd1 = Zn3FPP1;
+defvar Zn3FPVAdd2 = Zn3FPP2;
+defvar Zn3FPVAdd3 = Zn3FPP3;
+
+// Integer Multiplies, SAD, Blendvb
+defvar Zn3FPVMul0 = Zn3FPP0;
+defvar Zn3FPVMul1 = Zn3FPP3;
+
+// Data Shuffles, Packs, Unpacks, Permute
+// Some complex shuffle operations are only available in pipe1.
+defvar Zn3FPVShuf = Zn3FPP1;
+defvar Zn3FPVShufAux = Zn3FPP2;
+
+// Bit Shift Left/Right operations
+defvar Zn3FPVShift0 = Zn3FPP1;
+defvar Zn3FPVShift1 = Zn3FPP2;
+
+// Moves and Logical operations on Packed Integer Data Types
+defvar Zn3FPVMisc0 = Zn3FPP0;
+defvar Zn3FPVMisc1 = Zn3FPP1;
+defvar Zn3FPVMisc2 = Zn3FPP2;
+defvar Zn3FPVMisc3 = Zn3FPP3;
+
+// *AES*
+defvar Zn3FPAES0 = Zn3FPP0;
+defvar Zn3FPAES1 = Zn3FPP1;
+
+// *CLM*
+defvar Zn3FPCLM0 = Zn3FPP0;
+defvar Zn3FPCLM1 = Zn3FPP1;
+
+// Execution pipeline grouping
+//===----------------------------------------------------------------------===//
+
+// AMD SOG 19h, 2.11 Floating-Point Unit
+// Stores and floating point to general purpose register transfer
+// have 2 dedicated pipelines (pipe 5 and 6).
+def Zn3FPU0123 : ProcResGroup<[Zn3FPP0, Zn3FPP1, Zn3FPP2, Zn3FPP3]>;
+
+// (v)FMUL*, (v)FMA*, Floating Point Compares, Blendv(DQ)
+def Zn3FPFMul01 : ProcResGroup<[Zn3FPFMul0, Zn3FPFMul1]>;
+
+// (v)FADD*
+// Some complex VADD operations are not available in all pipes.
+def Zn3FPFAdd01 : ProcResGroup<[Zn3FPFAdd0, Zn3FPFAdd1]>;
+
+// All convert operations except pack/unpack
+def Zn3FPFCvt01 : ProcResGroup<[Zn3FPFCvt0, Zn3FPFCvt1]>;
+
+// All Divide and Square Root except Reciprocal Approximation
+// def Zn3FPFDiv : ProcResGroup<[Zn3FPFDiv]>;
+
+// Moves and Logical operations on Floating Point Data Types
+def Zn3FPFMisc0123 : ProcResGroup<[Zn3FPFMisc0, Zn3FPFMisc1, Zn3FPFMisc2, Zn3FPFMisc3]>;
+
+def Zn3FPFMisc12 : ProcResGroup<[Zn3FPFMisc1, Zn3FPFMisc2]>;
+
+// Loads, Stores and Move to General Register (EX) Operations
+// AMD SOG 19h, 2.11 Floating-Point Unit
+// Stores and floating point to general purpose register transfer
+// have 2 dedicated pipelines (pipe 5 and 6).
+defvar Zn3FPLd01 = Zn3FPP45;
+
+// AMD SOG 19h, 2.11 Floating-Point Unit
+// Note that FP stores are supported on two pipelines,
+// but throughput is limited to one per cycle.
+let Super = Zn3FPP45 in
+def Zn3FPSt : ProcResource<1>;
+
+// Integer Adds, Subtracts, and Compares
+// Some complex VADD operations are not available in all pipes.
+def Zn3FPVAdd0123 : ProcResGroup<[Zn3FPVAdd0, Zn3FPVAdd1, Zn3FPVAdd2, Zn3FPVAdd3]>;
+
+def Zn3FPVAdd01: ProcResGroup<[Zn3FPVAdd0, Zn3FPVAdd1]>;
+def Zn3FPVAdd12: ProcResGroup<[Zn3FPVAdd1, Zn3FPVAdd2]>;
+
+// Integer Multiplies, SAD, Blendvb
+def Zn3FPVMul01 : ProcResGroup<[Zn3FPVMul0, Zn3FPVMul1]>;
+
+// Data Shuffles, Packs, Unpacks, Permute
+// Some complex shuffle operations are only available in pipe1.
+def Zn3FPVShuf01 : ProcResGroup<[Zn3FPVShuf, Zn3FPVShufAux]>;
+
+// Bit Shift Left/Right operations
+def Zn3FPVShift01 : ProcResGroup<[Zn3FPVShift0, Zn3FPVShift1]>;
+
+// Moves and Logical operations on Packed Integer Data Types
+def Zn3FPVMisc0123 : ProcResGroup<[Zn3FPVMisc0, Zn3FPVMisc1, Zn3FPVMisc2, Zn3FPVMisc3]>;
+
+// *AES*
+def Zn3FPAES01 : ProcResGroup<[Zn3FPAES0, Zn3FPAES1]>;
+
+// *CLM*
+def Zn3FPCLM01 : ProcResGroup<[Zn3FPCLM0, Zn3FPCLM1]>;
+
+
+//
+// Scheduling
+//===----------------------------------------------------------------------===//
+
+// Agner, 21.8 Register renaming and out-of-order schedulers
+// The floating point register file has 160 vector registers
+// of 128 bits each in Zen 1 and 256 bits each in Zen 2.
+// anandtech also confirms this.
+def Zn3FpPRF : RegisterFile<160, [VR64, VR128, VR256], [1, 1, 1]>;
+
+// AMD SOG 19h, 2.11 Floating-Point Unit
+// The floating-point scheduler has a 2*32 entry macro op capacity.
+// AMD SOG 19h, 2.11 Floating-Point Unit
+// <...> the scheduler can issue 1 micro op per cycle for each pipe.
+// FIXME: those are two separate schedulers, not a single big one.
+def Zn3FP : ProcResGroup<[Zn3FPP0, Zn3FPP2, /*Zn3FPP4,*/ // scheduler 0
+ Zn3FPP1, Zn3FPP3, Zn3FPP45 /*Zn3FPP5*/ // scheduler 1
+ ]> {
+ let BufferSize = !mul(2, 32);
+}
+
+// AMD SOG 19h, 2.11 Floating-Point Unit
+// Macro ops can be dispatched to the 64 entry Non Scheduling Queue (NSQ)
+// even if floating-point scheduler is full.
+// FIXME: how to model this properly?
+
+
+//===----------------------------------------------------------------------===//
+// Load-Store Unit
+//
+
+// AMD SOG 19h, 2.12 Load-Store Unit
+// The LS unit contains three largely independent pipe-lines
+// enabling the execution of three 256-bit memory operations per cycle.
+def Zn3LSU : ProcResource<3>;
+
+// AMD SOG 19h, 2.12 Load-Store Unit
+// All three memory operations can be loads.
+let Super = Zn3LSU in
+def Zn3Load : ProcResource<3> {
+ // AMD SOG 19h, 2.12 Load-Store Unit
+ // The LS unit can process up to 72 out-of-order loads.
+ let BufferSize = 72;
+}
+
+def Zn3LoadQueue : LoadQueue<Zn3Load>;
+
+// AMD SOG 19h, 2.12 Load-Store Unit
+// A maximum of two of the memory operations can be stores.
+let Super = Zn3LSU in
+def Zn3Store : ProcResource<2> {
+ // AMD SOG 19h, 2.12 Load-Store Unit
+ // The LS unit utilizes a 64-entry store queue (STQ).
+ let BufferSize = 64;
+}
+
+def Zn3StoreQueue : StoreQueue<Zn3Store>;
+
+//===----------------------------------------------------------------------===//
+// Basic helper classes.
+//===----------------------------------------------------------------------===//
+
+// Many SchedWrites are defined in pairs with and without a folded load.
+// Instructions with folded loads are usually micro-fused, so they only appear
+// as two micro-ops when dispatched by the schedulers.
+// This multiclass defines the resource usage for variants with and without
+// folded loads.
+
+multiclass __zn3WriteRes<SchedWrite SchedRW, list<ProcResourceKind> ExePorts,
+ int Lat = 1, list<int> Res = [], int UOps = 1> {
+ def : WriteRes<SchedRW, ExePorts> {
+ let Latency = Lat;
+ let ResourceCycles = Res;
+ let NumMicroOps = UOps;
+ }
+}
+
+multiclass __zn3WriteResPair<X86FoldableSchedWrite SchedRW,
+ list<ProcResourceKind> ExePorts, int Lat,
+ list<int> Res, int UOps, int LoadLat, int LoadUOps,
+ ProcResourceKind AGU, int LoadRes> {
+ defm : __zn3WriteRes<SchedRW, ExePorts, Lat, Res, UOps>;
+
+ defm : __zn3WriteRes<SchedRW.Folded,
+ !listconcat([AGU, Zn3Load], ExePorts),
+ !add(Lat, LoadLat),
+ !if(!and(!empty(Res), !eq(LoadRes, 1)),
+ [],
+ !listconcat([1, LoadRes],
+ !if(!empty(Res),
+ !listsplat(1, !size(ExePorts)),
+ Res))),
+ !add(UOps, LoadUOps)>;
+}
+
+// For classes without folded loads.
+multiclass Zn3WriteResInt<SchedWrite SchedRW,
+ list<ProcResourceKind> ExePorts, int Lat = 1,
+ list<int> Res = [], int UOps = 1> {
+ defm : __zn3WriteRes<SchedRW, ExePorts, Lat, Res, UOps>;
+}
+
+multiclass Zn3WriteResXMM<SchedWrite SchedRW,
+ list<ProcResourceKind> ExePorts, int Lat = 1,
+ list<int> Res = [], int UOps = 1> {
+ defm : __zn3WriteRes<SchedRW, ExePorts, Lat, Res, UOps>;
+}
+
+multiclass Zn3WriteResYMM<SchedWrite SchedRW,
+ list<ProcResourceKind> ExePorts, int Lat = 1,
+ list<int> Res = [], int UOps = 1> {
+ defm : __zn3WriteRes<SchedRW, ExePorts, Lat, Res, UOps>;
+}
+
+// For classes with folded loads.
+multiclass Zn3WriteResIntPair<X86FoldableSchedWrite SchedRW,
+ list<ProcResourceKind> ExePorts, int Lat = 1,
+ list<int> Res = [], int UOps = 1,
+ int LoadUOps = 0, int LoadRes = 1> {
+ defm : __zn3WriteResPair<SchedRW, ExePorts, Lat, Res, UOps,
+ Znver3Model.LoadLatency,
+ LoadUOps, Zn3AGU012, LoadRes>;
+}
+
+multiclass Zn3WriteResXMMPair<X86FoldableSchedWrite SchedRW,
+ list<ProcResourceKind> ExePorts, int Lat = 1,
+ list<int> Res = [], int UOps = 1,
+ int LoadUOps = 0, int LoadRes = 1> {
+ defm : __zn3WriteResPair<SchedRW, ExePorts, Lat, Res, UOps,
+ Znver3Model.VecLoadLatency,
+ LoadUOps, Zn3FPLd01, LoadRes>;
+}
+
+multiclass Zn3WriteResYMMPair<X86FoldableSchedWrite SchedRW,
+ list<ProcResourceKind> ExePorts, int Lat = 1,
+ list<int> Res = [], int UOps = 1,
+ int LoadUOps = 0, int LoadRes = 1> {
+ defm : __zn3WriteResPair<SchedRW, ExePorts, Lat, Res, UOps,
+ Znver3Model.VecLoadLatency,
+ LoadUOps, Zn3FPLd01, LoadRes>;
+}
+
+
+//===----------------------------------------------------------------------===//
+// Here be dragons.
+//===----------------------------------------------------------------------===//
+
+def : ReadAdvance<ReadAfterLd, Znver3Model.LoadLatency>;
+
+def : ReadAdvance<ReadAfterVecLd, Znver3Model.VecLoadLatency>;
+def : ReadAdvance<ReadAfterVecXLd, Znver3Model.VecLoadLatency>;
+def : ReadAdvance<ReadAfterVecYLd, Znver3Model.VecLoadLatency>;
+
+// AMD SOG 19h, 2.11 Floating-Point Unit
+// There is 1 cycle of added latency for a result to cross
+// from F to I or I to F domain.
+def : ReadAdvance<ReadInt2Fpu, -1>;
+
+// Instructions with both a load and a store folded are modeled as a folded
+// load + WriteRMW.
+defm : Zn3WriteResInt<WriteRMW, [Zn3AGU012, Zn3Store], Znver3Model.StoreLatency, [1, 1], 0>;
+
+// Loads, stores, and moves, not folded with other operations.
+defm : Zn3WriteResInt<WriteLoad, [Zn3AGU012, Zn3Load], !add(Znver3Model.LoadLatency, 1), [1, 1], 1>;
+
+def Zn3WriteMOVSlow : SchedWriteRes<[Zn3AGU012, Zn3Load]> {
+ let Latency = !add(Znver3Model.LoadLatency, 1);
+ let ResourceCycles = [3, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[Zn3WriteMOVSlow], (instrs MOV8rm, MOV8rm_NOREX, MOV16rm, MOVSX16rm16, MOVSX16rm32, MOVZX16rm16, MOVSX16rm8, MOVZX16rm8)>;
+
+defm : Zn3WriteResInt<WriteStore, [Zn3AGU012, Zn3Store], Znver3Model.StoreLatency, [1, 2], 1>;
+defm : Zn3WriteResInt<WriteStoreNT, [Zn3AGU012, Zn3Store], Znver3Model.StoreLatency, [1, 2], 1>;
+defm : Zn3WriteResInt<WriteMove, [Zn3ALU0123], 1, [4], 1>;
+
+def Zn3WriteMoveRenameable : SchedWriteRes<[Zn3ALU0123]> {
+ let Latency = 0;
+ let ResourceCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[Zn3WriteMoveRenameable], (instrs MOV32rr, MOV32rr_REV,
+ MOV64rr, MOV64rr_REV,
+ MOVSX32rr32)>;
+
+def Zn3WriteMOVBE16rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU0123]> {
+ let Latency = Znver3Model.LoadLatency;
+ let ResourceCycles = [1, 1, 4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[Zn3WriteMOVBE16rm], (instrs MOVBE16rm)>;
+
+def Zn3WriteMOVBEmr : SchedWriteRes<[Zn3ALU0123, Zn3AGU012, Zn3Store]> {
+ let Latency = Znver3Model.StoreLatency;
+ let ResourceCycles = [4, 1, 1];
+ let NumMicroOps = 2;
+}
+def : InstRW<[Zn3WriteMOVBEmr], (instrs MOVBE16mr, MOVBE32mr, MOVBE64mr)>;
+
+// Arithmetic.
+defm : Zn3WriteResIntPair<WriteALU, [Zn3ALU0123], 1, [1], 1>; // Simple integer ALU op.
+
+def Zn3WriteALUSlow : SchedWriteRes<[Zn3ALU0123]> {
+ let Latency = 1;
+ let ResourceCycles = [4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[Zn3WriteALUSlow], (instrs ADD8i8, ADD16i16, ADD32i32, ADD64i32,
+ AND8i8, AND16i16, AND32i32, AND64i32,
+ OR8i8, OR16i16, OR32i32, OR64i32,
+ SUB8i8, SUB16i16, SUB32i32, SUB64i32,
+ XOR8i8, XOR16i16, XOR32i32, XOR64i32)>;
+
+def Zn3WriteMoveExtend : SchedWriteRes<[Zn3ALU0123]> {
+ let Latency = 1;
+ let ResourceCycles = [4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[Zn3WriteMoveExtend], (instrs MOVSX16rr16, MOVSX16rr32, MOVZX16rr16, MOVSX16rr8, MOVZX16rr8)>;
+
+def Zn3WriteMaterialize32bitImm: SchedWriteRes<[Zn3ALU0123]> {
+ let Latency = 1;
+ let ResourceCycles = [2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[Zn3WriteMaterialize32bitImm], (instrs MOV32ri, MOV32ri_alt, MOV64ri32)>;
+
+def Zn3WritePDEP_PEXT : SchedWriteRes<[Zn3ALU1]> {
+ let Latency = 3;
+ let ResourceCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[Zn3WritePDEP_PEXT], (instrs PDEP32rr, PDEP64rr,
+ PEXT32rr, PEXT64rr)>;
+
+defm : Zn3WriteResIntPair<WriteADC, [Zn3ALU0123], 1, [4], 1>; // Integer ALU + flags op.
+
+def Zn3WriteADC8mr_SBB8mr : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU0123, Zn3Store]> {
+ let Latency = 1;
+ let ResourceCycles = [1, 1, 7, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[Zn3WriteADC8mr_SBB8mr], (instrs ADC8mr, SBB8mr)>;
+
+// This is for simple LEAs with one or two input operands.
+defm : Zn3WriteResInt<WriteLEA, [Zn3AGU012], 1, [1], 1>; // LEA instructions can't fold loads.
+
+// This write is used for slow LEA instructions.
+def Zn3Write3OpsLEA : SchedWriteRes<[Zn3ALU0123]> {
+ let Latency = 2;
+ let ResourceCycles = [1];
+ let NumMicroOps = 2;
+}
+
+// On Piledriver, a slow LEA is either a 3Ops LEA (base, index, offset),
+// or an LEA with a `Scale` value
diff erent than 1.
+def Zn3SlowLEAPredicate : MCSchedPredicate<
+ CheckAny<[
+ // A 3-operand LEA (base, index, offset).
+ IsThreeOperandsLEAFn,
+ // An LEA with a "Scale"
diff erent than 1.
+ CheckAll<[
+ CheckIsImmOperand<2>,
+ CheckNot<CheckImmOperand<2, 1>>
+ ]>
+ ]>
+>;
+
+def Zn3WriteLEA : SchedWriteVariant<[
+ SchedVar<Zn3SlowLEAPredicate, [Zn3Write3OpsLEA]>,
+ SchedVar<NoSchedPred, [WriteLEA]>
+]>;
+
+def : InstRW<[Zn3WriteLEA], (instrs LEA32r, LEA64r, LEA64_32r)>;
+
+def Zn3SlowLEA16r : SchedWriteRes<[Zn3ALU0123]> {
+ let Latency = 2; // FIXME: not from llvm-exegesis
+ let ResourceCycles = [4];
+ let NumMicroOps = 2;
+}
+
+def : InstRW<[Zn3SlowLEA16r], (instrs LEA16r)>;
+
+// Integer multiplication
+defm : Zn3WriteResIntPair<WriteIMul8, [Zn3Multiplier], 3, [3], 1>; // Integer 8-bit multiplication.
+defm : Zn3WriteResIntPair<WriteIMul16, [Zn3Multiplier], 3, [3], 3, /*LoadUOps=*/1>; // Integer 16-bit multiplication.
+defm : Zn3WriteResIntPair<WriteIMul16Imm, [Zn3Multiplier], 4, [4], 2>; // Integer 16-bit multiplication by immediate.
+defm : Zn3WriteResIntPair<WriteIMul16Reg, [Zn3Multiplier], 3, [1], 1>; // Integer 16-bit multiplication by register.
+defm : Zn3WriteResIntPair<WriteIMul32, [Zn3Multiplier], 3, [3], 2>; // Integer 32-bit multiplication.
+
+def Zn3MULX32rr : SchedWriteRes<[Zn3Multiplier]> {
+ let Latency = 3;
+ let ResourceCycles = [1];
+ let NumMicroOps = 2;
+}
+def : InstRW<[Zn3MULX32rr], (instrs MULX32rr)>;
+
+def Zn3MULX32rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3Multiplier]> {
+ let Latency = !add(Znver3Model.LoadLatency, Zn3MULX32rr.Latency);
+ let ResourceCycles = [1, 1, 2];
+ let NumMicroOps = Zn3MULX32rr.NumMicroOps;
+}
+def : InstRW<[Zn3MULX32rm], (instrs MULX32rm)>;
+
+defm : Zn3WriteResIntPair<WriteIMul32Imm, [Zn3Multiplier], 3, [1], 1>; // Integer 32-bit multiplication by immediate.
+defm : Zn3WriteResIntPair<WriteIMul32Reg, [Zn3Multiplier], 3, [1], 1>; // Integer 32-bit multiplication by register.
+defm : Zn3WriteResIntPair<WriteIMul64, [Zn3Multiplier], 3, [3], 2>; // Integer 64-bit multiplication.
+
+def Zn3MULX64rr : SchedWriteRes<[Zn3Multiplier]> {
+ let Latency = 4;
+ let ResourceCycles = [1];
+ let NumMicroOps = 2;
+}
+def : InstRW<[Zn3MULX64rr], (instrs MULX64rr)>;
+
+def Zn3MULX64rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3Multiplier]> {
+ let Latency = !add(Znver3Model.LoadLatency, Zn3MULX64rr.Latency);
+ let ResourceCycles = [1, 1, 2];
+ let NumMicroOps = Zn3MULX64rr.NumMicroOps;
+}
+def : InstRW<[Zn3MULX64rm], (instrs MULX64rm)>;
+
+defm : Zn3WriteResIntPair<WriteIMul64Imm, [Zn3Multiplier], 3, [1], 1>; // Integer 64-bit multiplication by immediate.
+defm : Zn3WriteResIntPair<WriteIMul64Reg, [Zn3Multiplier], 3, [1], 1>; // Integer 64-bit multiplication by register.
+defm : Zn3WriteResInt<WriteIMulH, [Zn3Multiplier], 2, [2], 2>; // Integer multiplication, high part.
+
+defm : Zn3WriteResInt<WriteBSWAP32, [Zn3ALU0123], 1, [1], 1>; // Byte Order (Endianness) 32-bit Swap.
+defm : Zn3WriteResInt<WriteBSWAP64, [Zn3ALU0123], 1, [1], 1>; // Byte Order (Endianness) 64-bit Swap.
+
+defm : Zn3WriteResIntPair<WriteCMPXCHG, [Zn3ALU0123], 3, [12], 5>; // Compare and set, compare and swap.
+
+def Zn3WriteCMPXCHG8rr : SchedWriteRes<[Zn3ALU0123]> {
+ let Latency = 3;
+ let ResourceCycles = [12];
+ let NumMicroOps = 3;
+}
+def : InstRW<[Zn3WriteCMPXCHG8rr], (instrs CMPXCHG8rr)>;
+
+defm : Zn3WriteResInt<WriteCMPXCHGRMW, [Zn3ALU0123], 3, [12], 6>; // Compare and set, compare and swap.
+
+def Zn3WriteCMPXCHG8rm_LCMPXCHG8 : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU0123]> {
+ let Latency = !add(Znver3Model.LoadLatency, Zn3WriteCMPXCHG8rr.Latency);
+ let ResourceCycles = [1, 1, 12];
+ let NumMicroOps = !add(Zn3WriteCMPXCHG8rr.NumMicroOps, 2);
+}
+def : InstRW<[Zn3WriteCMPXCHG8rm_LCMPXCHG8], (instrs CMPXCHG8rm, LCMPXCHG8)>;
+
+def Zn3WriteCMPXCHG8B : SchedWriteRes<[Zn3ALU0123]> {
+ let Latency = 3; // FIXME: not from llvm-exegesis
+ let ResourceCycles = [24];
+ let NumMicroOps = 19;
+}
+def : InstRW<[Zn3WriteCMPXCHG8B], (instrs CMPXCHG8B)>;
+
+def Zn3WriteCMPXCHG16B_LCMPXCHG16B : SchedWriteRes<[Zn3ALU0123]> {
+ let Latency = 4; // FIXME: not from llvm-exegesis
+ let ResourceCycles = [59];
+ let NumMicroOps = 28;
+}
+def : InstRW<[Zn3WriteCMPXCHG16B_LCMPXCHG16B], (instrs CMPXCHG16B, LCMPXCHG16B)>;
+
+defm : Zn3WriteResInt<WriteXCHG, [Zn3ALU0123], 0, [8], 2>; // Compare+Exchange - TODO RMW support.
+
+def Zn3WriteWriteXCHGUnrenameable : SchedWriteRes<[Zn3ALU0123]> {
+ let Latency = 1;
+ let ResourceCycles = [2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[Zn3WriteWriteXCHGUnrenameable], (instrs XCHG8rr, XCHG16rr, XCHG16ar)>;
+
+def Zn3WriteXCHG8rm_XCHG16rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU0123]> {
+ let Latency = !add(Znver3Model.LoadLatency, 3); // FIXME: not from llvm-exegesis
+ let ResourceCycles = [1, 1, 2];
+ let NumMicroOps = 5;
+}
+def : InstRW<[Zn3WriteXCHG8rm_XCHG16rm], (instrs XCHG8rm, XCHG16rm)>;
+
+def Zn3WriteXCHG32rm_XCHG64rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU0123]> {
+ let Latency = !add(Znver3Model.LoadLatency, 2); // FIXME: not from llvm-exegesis
+ let ResourceCycles = [1, 1, 2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[Zn3WriteXCHG32rm_XCHG64rm], (instrs XCHG32rm, XCHG64rm)>;
+
+// Integer division.
+// FIXME: uops for 8-bit division measures as 2. for others it's a guess.
+// FIXME: latency for 8-bit division measures as 10. for others it's a guess.
+defm : Zn3WriteResIntPair<WriteDiv8, [Zn3Divider], 10, [10], 2>;
+defm : Zn3WriteResIntPair<WriteDiv16, [Zn3Divider], 11, [11], 2>;
+defm : Zn3WriteResIntPair<WriteDiv32, [Zn3Divider], 13, [13], 2>;
+defm : Zn3WriteResIntPair<WriteDiv64, [Zn3Divider], 17, [17], 2>;
+defm : Zn3WriteResIntPair<WriteIDiv8, [Zn3Divider], 10, [10], 2>;
+defm : Zn3WriteResIntPair<WriteIDiv16, [Zn3Divider], 11, [11], 2>;
+defm : Zn3WriteResIntPair<WriteIDiv32, [Zn3Divider], 13, [13], 2>;
+defm : Zn3WriteResIntPair<WriteIDiv64, [Zn3Divider], 17, [17], 2>;
+
+defm : Zn3WriteResIntPair<WriteBSF, [Zn3ALU1], 3, [3], 6, /*LoadUOps=*/2>; // Bit scan forward.
+defm : Zn3WriteResIntPair<WriteBSR, [Zn3ALU1], 4, [4], 6, /*LoadUOps=*/2>; // Bit scan reverse.
+
+defm : Zn3WriteResIntPair<WritePOPCNT, [Zn3ALU0123], 1, [1], 1>; // Bit population count.
+
+def Zn3WritePOPCNT16rr : SchedWriteRes<[Zn3ALU0123]> {
+ let Latency = 1;
+ let ResourceCycles = [4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[Zn3WritePOPCNT16rr], (instrs POPCNT16rr)>;
+
+defm : Zn3WriteResIntPair<WriteLZCNT, [Zn3ALU0123], 1, [1], 1>; // Leading zero count.
+
+def Zn3WriteLZCNT16rr : SchedWriteRes<[Zn3ALU0123]> {
+ let Latency = 1;
+ let ResourceCycles = [4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[Zn3WriteLZCNT16rr], (instrs LZCNT16rr)>;
+
+defm : Zn3WriteResIntPair<WriteTZCNT, [Zn3ALU12], 2, [1], 2>; // Trailing zero count.
+
+def Zn3WriteTZCNT16rr : SchedWriteRes<[Zn3ALU0123]> {
+ let Latency = 2;
+ let ResourceCycles = [4];
+ let NumMicroOps = 2;
+}
+def : InstRW<[Zn3WriteTZCNT16rr], (instrs TZCNT16rr)>;
+
+defm : Zn3WriteResIntPair<WriteCMOV, [Zn3ALU03], 1, [1], 1>; // Conditional move.
+defm : Zn3WriteResInt<WriteFCMOV, [Zn3ALU0123], 7, [28], 7>; // FIXME: not from llvm-exegesis // X87 conditional move.
+defm : Zn3WriteResInt<WriteSETCC, [Zn3ALU03], 1, [2], 1>; // Set register based on condition code.
+defm : Zn3WriteResInt<WriteSETCCStore, [Zn3ALU03, Zn3AGU012, Zn3Store], 2, [2, 1, 1], 2>; // FIXME: latency not from llvm-exegesis
+defm : Zn3WriteResInt<WriteLAHFSAHF, [Zn3ALU3], 1, [1], 1>; // Load/Store flags in AH.
+
+defm : Zn3WriteResInt<WriteBitTest, [Zn3ALU12], 1, [1], 1>; // Bit Test
+defm : Zn3WriteResInt<WriteBitTestImmLd, [Zn3AGU012, Zn3Load, Zn3ALU12], !add(Znver3Model.LoadLatency, 1), [1, 1, 1], 2>;
+defm : Zn3WriteResInt<WriteBitTestRegLd, [Zn3AGU012, Zn3Load, Zn3ALU12], !add(Znver3Model.LoadLatency, 1), [1, 1, 1], 7>;
+
+defm : Zn3WriteResInt<WriteBitTestSet, [Zn3ALU12], 2, [2], 2>; // Bit Test + Set
+defm : Zn3WriteResInt<WriteBitTestSetImmLd, [Zn3AGU012, Zn3Load, Zn3ALU12], !add(Znver3Model.LoadLatency, 2), [1, 1, 1], 4>;
+defm : Zn3WriteResInt<WriteBitTestSetRegLd, [Zn3AGU012, Zn3Load, Zn3ALU12], !add(Znver3Model.LoadLatency, 2), [1, 1, 1], 9>;
+
+// Integer shifts and rotates.
+defm : Zn3WriteResIntPair<WriteShift, [Zn3ALU12], 1, [1], 1, /*LoadUOps=*/1>;
+defm : Zn3WriteResIntPair<WriteShiftCL, [Zn3ALU12], 1, [1], 1, /*LoadUOps=*/1>;
+defm : Zn3WriteResIntPair<WriteRotate, [Zn3ALU12], 1, [1], 1, /*LoadUOps=*/1>;
+
+def Zn3WriteRotateR1 : SchedWriteRes<[Zn3ALU12]> {
+ let Latency = 1;
+ let ResourceCycles = [2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[Zn3WriteRotateR1], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
+ RCR8r1, RCR16r1, RCR32r1, RCR64r1)>;
+
+def Zn3WriteRotateM1 : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU12]> {
+ let Latency = !add(Znver3Model.LoadLatency, Zn3WriteRotateR1.Latency);
+ let ResourceCycles = [1, 1, 2];
+ let NumMicroOps = !add(Zn3WriteRotateR1.NumMicroOps, 1);
+}
+def : InstRW<[Zn3WriteRotateM1], (instrs RCL8m1, RCL16m1, RCL32m1, RCL64m1,
+ RCR8m1, RCR16m1, RCR32m1, RCR64m1)>;
+
+def Zn3WriteRotateRightRI : SchedWriteRes<[Zn3ALU12]> {
+ let Latency = 3;
+ let ResourceCycles = [6];
+ let NumMicroOps = 7;
+}
+def : InstRW<[Zn3WriteRotateRightRI], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>;
+
+def Zn3WriteRotateRightMI : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU12]> {
+ let Latency = !add(Znver3Model.LoadLatency, Zn3WriteRotateRightRI.Latency);
+ let ResourceCycles = [1, 1, 8];
+ let NumMicroOps = !add(Zn3WriteRotateRightRI.NumMicroOps, 3);
+}
+def : InstRW<[Zn3WriteRotateRightMI], (instrs RCR8mi, RCR16mi, RCR32mi, RCR64mi)>;
+
+def Zn3WriteRotateLeftRI : SchedWriteRes<[Zn3ALU12]> {
+ let Latency = 4;
+ let ResourceCycles = [8];
+ let NumMicroOps = 9;
+}
+def : InstRW<[Zn3WriteRotateLeftRI], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>;
+
+def Zn3WriteRotateLeftMI : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU12]> {
+ let Latency = !add(Znver3Model.LoadLatency, Zn3WriteRotateLeftRI.Latency);
+ let ResourceCycles = [1, 1, 8];
+ let NumMicroOps = !add(Zn3WriteRotateLeftRI.NumMicroOps, 2);
+}
+def : InstRW<[Zn3WriteRotateLeftMI], (instrs RCL8mi, RCL16mi, RCL32mi, RCL64mi)>;
+
+defm : Zn3WriteResIntPair<WriteRotateCL, [Zn3ALU12], 1, [1], 1, /*LoadUOps=*/1>;
+
+def Zn3WriteRotateRightRCL : SchedWriteRes<[Zn3ALU12]> {
+ let Latency = 3;
+ let ResourceCycles = [6];
+ let NumMicroOps = 7;
+}
+def : InstRW<[Zn3WriteRotateRightRCL], (instrs RCR8rCL, RCR16rCL, RCR32rCL, RCR64rCL)>;
+
+def Zn3WriteRotateRightMCL : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU12]> {
+ let Latency = !add(Znver3Model.LoadLatency, Zn3WriteRotateRightRCL.Latency);
+ let ResourceCycles = [1, 1, 8];
+ let NumMicroOps = !add(Zn3WriteRotateRightRCL.NumMicroOps, 2);
+}
+def : InstRW<[Zn3WriteRotateRightMCL], (instrs RCR8mCL, RCR16mCL, RCR32mCL, RCR64mCL)>;
+
+def Zn3WriteRotateLeftRCL : SchedWriteRes<[Zn3ALU12]> {
+ let Latency = 4;
+ let ResourceCycles = [8];
+ let NumMicroOps = 9;
+}
+def : InstRW<[Zn3WriteRotateLeftRCL], (instrs RCL8rCL, RCL16rCL, RCL32rCL, RCL64rCL)>;
+
+def Zn3WriteRotateLeftMCL : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU12]> {
+ let Latency = !add(Znver3Model.LoadLatency, Zn3WriteRotateLeftRCL.Latency);
+ let ResourceCycles = [1, 1, 8];
+ let NumMicroOps = !add(Zn3WriteRotateLeftRCL.NumMicroOps, 2);
+}
+def : InstRW<[Zn3WriteRotateLeftMCL], (instrs RCL8mCL, RCL16mCL, RCL32mCL, RCL64mCL)>;
+
+// Double shift instructions.
+defm : Zn3WriteResInt<WriteSHDrri, [Zn3ALU12], 2, [3], 4>;
+defm : Zn3WriteResInt<WriteSHDrrcl, [Zn3ALU12], 2, [3], 5>;
+defm : Zn3WriteResInt<WriteSHDmri, [Zn3AGU012, Zn3Load, Zn3ALU12], !add(Znver3Model.LoadLatency, 2), [1, 1, 4], 6>;
+defm : Zn3WriteResInt<WriteSHDmrcl, [Zn3AGU012, Zn3Load, Zn3ALU12], !add(Znver3Model.LoadLatency, 2), [1, 1, 4], 6>;
+
+// BMI1 BEXTR/BLS, BMI2 BZHI
+defm : Zn3WriteResIntPair<WriteBEXTR, [Zn3ALU12], 1, [1], 1, /*LoadUOps=*/1>;
+defm : Zn3WriteResIntPair<WriteBLS, [Zn3ALU0123], 2, [2], 2, /*LoadUOps=*/1>;
+defm : Zn3WriteResIntPair<WriteBZHI, [Zn3ALU12], 1, [1], 1, /*LoadUOps=*/1>;
+
+// Idioms that clear a register, like xorps %xmm0, %xmm0.
+// These can often bypass execution ports completely.
+defm : Zn3WriteResInt<WriteZero, [Zn3ALU0123], 0, [0], 1>;
+
+// Branches don't produce values, so they have no latency, but they still
+// consume resources. Indirect branches can fold loads.
+defm : Zn3WriteResIntPair<WriteJump, [Zn3BRU01], 1, [1], 1>; // FIXME: not from llvm-exegesis
+
+// Floating point. This covers both scalar and vector operations.
+defm : Zn3WriteResInt<WriteFLD0, [Zn3FPLd01, Zn3Load, Zn3FPP1], !add(Znver3Model.LoadLatency, 4), [1, 1, 1], 1>;
+defm : Zn3WriteResInt<WriteFLD1, [Zn3FPLd01, Zn3Load, Zn3FPP1], !add(Znver3Model.LoadLatency, 7), [1, 1, 1], 1>;
+defm : Zn3WriteResInt<WriteFLDC, [Zn3FPLd01, Zn3Load, Zn3FPP1], !add(Znver3Model.LoadLatency, 7), [1, 1, 1], 1>;
+defm : Zn3WriteResXMM<WriteFLoad, [Zn3FPLd01, Zn3Load], !add(Znver3Model.VecLoadLatency, 1), [1, 1], 1>;
+defm : Zn3WriteResXMM<WriteFLoadX, [Zn3FPLd01, Zn3Load], !add(Znver3Model.VecLoadLatency, 1), [1, 1], 1>;
+defm : Zn3WriteResYMM<WriteFLoadY, [Zn3FPLd01, Zn3Load], !add(Znver3Model.VecLoadLatency, 1), [1, 1], 1>;
+defm : Zn3WriteResXMM<WriteFMaskedLoad, [Zn3FPLd01, Zn3Load], !add(Znver3Model.VecLoadLatency, 1), [1, 1], 1>;
+defm : Zn3WriteResYMM<WriteFMaskedLoadY, [Zn3FPLd01, Zn3Load], !add(Znver3Model.VecLoadLatency, 1), [1, 1], 1>;
+defm : Zn3WriteResXMM<WriteFStore, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [1, 1], 1>;
+
+def Zn3WriteWriteFStoreMMX : SchedWriteRes<[Zn3FPSt, Zn3Store]> {
+ let Latency = 2; // FIXME: not from llvm-exegesis
+ let ResourceCycles = [1, 1];
+ let NumMicroOps = 2;
+}
+def : InstRW<[Zn3WriteWriteFStoreMMX], (instrs MOVHPDmr, MOVHPSmr,
+ VMOVHPDmr, VMOVHPSmr)>;
+
+defm : Zn3WriteResXMM<WriteFStoreX, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [1, 1], 1>;
+defm : Zn3WriteResYMM<WriteFStoreY, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [1, 1], 1>;
+defm : Zn3WriteResXMM<WriteFStoreNT, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [1, 1], 1>;
+defm : Zn3WriteResXMM<WriteFStoreNTX, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [1, 1], 1>;
+defm : Zn3WriteResYMM<WriteFStoreNTY, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [1, 1], 1>;
+
+defm : Zn3WriteResXMM<WriteFMaskedStore32, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [6, 1], 18>;
+defm : Zn3WriteResXMM<WriteFMaskedStore64, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [4, 1], 10>;
+defm : Zn3WriteResYMM<WriteFMaskedStore32Y, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [12, 1], 42>;
+defm : Zn3WriteResYMM<WriteFMaskedStore64Y, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [6, 1], 18>;
+
+defm : Zn3WriteResXMM<WriteFMove, [Zn3FPVMisc0123], 0, [1], 1>;
+defm : Zn3WriteResXMM<WriteFMoveX, [Zn3FPVMisc0123], 0, [1], 1>;
+defm : Zn3WriteResYMM<WriteFMoveY, [Zn3FPVMisc0123], 0, [1], 1>;
+
+defm : Zn3WriteResXMMPair<WriteFAdd, [Zn3FPFAdd01], 3, [1], 1>; // Floating point add/sub.
+
+def Zn3WriteX87Arith : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPU0123]> {
+ let Latency = !add(Znver3Model.LoadLatency, 1); // FIXME: not from llvm-exegesis
+ let ResourceCycles = [1, 1, 24];
+ let NumMicroOps = 2;
+}
+def : InstRW<[Zn3WriteX87Arith], (instrs ADD_FI16m, ADD_FI32m,
+ SUB_FI16m, SUB_FI32m,
+ SUBR_FI16m, SUBR_FI32m,
+ MUL_FI16m, MUL_FI32m)>;
+
+def Zn3WriteX87Div : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPU0123]> {
+ let Latency = !add(Znver3Model.LoadLatency, 1); // FIXME: not from llvm-exegesis
+ let ResourceCycles = [1, 1, 62];
+ let NumMicroOps = 2;
+}
+def : InstRW<[Zn3WriteX87Div], (instrs DIV_FI16m, DIV_FI32m,
+ DIVR_FI16m, DIVR_FI32m)>;
+
+defm : Zn3WriteResXMMPair<WriteFAddX, [Zn3FPFAdd01], 3, [1], 1>; // Floating point add/sub (XMM).
+defm : Zn3WriteResYMMPair<WriteFAddY, [Zn3FPFAdd01], 3, [1], 1>; // Floating point add/sub (YMM).
+defm : X86WriteResPairUnsupported<WriteFAddZ>; // Floating point add/sub (ZMM).
+defm : Zn3WriteResXMMPair<WriteFAdd64, [Zn3FPFAdd01], 3, [1], 1>; // Floating point double add/sub.
+defm : Zn3WriteResXMMPair<WriteFAdd64X, [Zn3FPFAdd01], 3, [1], 1>; // Floating point double add/sub (XMM).
+defm : Zn3WriteResYMMPair<WriteFAdd64Y, [Zn3FPFAdd01], 3, [1], 1>; // Floating point double add/sub (YMM).
+defm : X86WriteResPairUnsupported<WriteFAdd64Z>; // Floating point double add/sub (ZMM).
+defm : Zn3WriteResXMMPair<WriteFCmp, [Zn3FPFMul01], 1, [1], 1>; // Floating point compare.
+defm : Zn3WriteResXMMPair<WriteFCmpX, [Zn3FPFMul01], 1, [1], 1>; // Floating point compare (XMM).
+defm : Zn3WriteResYMMPair<WriteFCmpY, [Zn3FPFMul01], 1, [1], 1>; // Floating point compare (YMM).
+defm : X86WriteResPairUnsupported<WriteFCmpZ>; // Floating point compare (ZMM).
+defm : Zn3WriteResXMMPair<WriteFCmp64, [Zn3FPFMul01], 1, [1], 1>; // Floating point double compare.
+defm : Zn3WriteResXMMPair<WriteFCmp64X, [Zn3FPFMul01], 1, [1], 1>; // Floating point double compare (XMM).
+defm : Zn3WriteResYMMPair<WriteFCmp64Y, [Zn3FPFMul01], 1, [1], 1>; // Floating point double compare (YMM).
+defm : X86WriteResPairUnsupported<WriteFCmp64Z>; // Floating point double compare (ZMM).
+defm : Zn3WriteResXMMPair<WriteFCom, [Zn3FPFMul01], 3, [2], 1>; // FIXME: latency not from llvm-exegesis // Floating point compare to flags (X87).
+defm : Zn3WriteResXMMPair<WriteFComX, [Zn3FPFMul01], 4, [2], 2>; // FIXME: latency not from llvm-exegesis // Floating point compare to flags (SSE).
+defm : Zn3WriteResXMMPair<WriteFMul, [Zn3FPFMul01], 3, [1], 1>; // Floating point multiplication.
+defm : Zn3WriteResXMMPair<WriteFMulX, [Zn3FPFMul01], 3, [1], 1>; // Floating point multiplication (XMM).
+defm : Zn3WriteResYMMPair<WriteFMulY, [Zn3FPFMul01], 3, [1], 1>; // Floating point multiplication (YMM).
+defm : X86WriteResPairUnsupported<WriteFMulZ>; // Floating point multiplication (YMM).
+defm : Zn3WriteResXMMPair<WriteFMul64, [Zn3FPFMul01], 3, [1], 1>; // Floating point double multiplication.
+defm : Zn3WriteResXMMPair<WriteFMul64X, [Zn3FPFMul01], 3, [1], 1>; // Floating point double multiplication (XMM).
+defm : Zn3WriteResYMMPair<WriteFMul64Y, [Zn3FPFMul01], 3, [1], 1>; // Floating point double multiplication (YMM).
+defm : X86WriteResPairUnsupported<WriteFMul64Z>; // Floating point double multiplication (ZMM).
+defm : Zn3WriteResXMMPair<WriteFDiv, [Zn3FPFDiv], 11, [3], 1>; // Floating point division.
+defm : Zn3WriteResXMMPair<WriteFDivX, [Zn3FPFDiv], 11, [3], 1>; // Floating point division (XMM).
+defm : Zn3WriteResYMMPair<WriteFDivY, [Zn3FPFDiv], 11, [3], 1>; // Floating point division (YMM).
+defm : X86WriteResPairUnsupported<WriteFDivZ>; // Floating point division (ZMM).
+defm : Zn3WriteResXMMPair<WriteFDiv64, [Zn3FPFDiv], 13, [5], 1>; // Floating point double division.
+defm : Zn3WriteResXMMPair<WriteFDiv64X, [Zn3FPFDiv], 13, [5], 1>; // Floating point double division (XMM).
+defm : Zn3WriteResYMMPair<WriteFDiv64Y, [Zn3FPFDiv], 13, [5], 1>; // Floating point double division (YMM).
+defm : X86WriteResPairUnsupported<WriteFDiv64Z>; // Floating point double division (ZMM).
+defm : Zn3WriteResXMMPair<WriteFSqrt, [Zn3FPFDiv], 15, [5], 1>; // Floating point square root.
+defm : Zn3WriteResXMMPair<WriteFSqrtX, [Zn3FPFDiv], 15, [5], 1>; // Floating point square root (XMM).
+defm : Zn3WriteResYMMPair<WriteFSqrtY, [Zn3FPFDiv], 15, [5], 1>; // Floating point square root (YMM).
+defm : X86WriteResPairUnsupported<WriteFSqrtZ>; // Floating point square root (ZMM).
+defm : Zn3WriteResXMMPair<WriteFSqrt64, [Zn3FPFDiv], 21, [9], 1>; // Floating point double square root.
+defm : Zn3WriteResXMMPair<WriteFSqrt64X, [Zn3FPFDiv], 21, [9], 1>; // Floating point double square root (XMM).
+defm : Zn3WriteResYMMPair<WriteFSqrt64Y, [Zn3FPFDiv], 21, [9], 1>; // Floating point double square root (YMM).
+defm : X86WriteResPairUnsupported<WriteFSqrt64Z>; // Floating point double square root (ZMM).
+defm : Zn3WriteResXMMPair<WriteFSqrt80, [Zn3FPFDiv], 22, [23], 1>; // FIXME: latency not from llvm-exegesis // Floating point long double square root.
+defm : Zn3WriteResXMMPair<WriteFRcp, [Zn3FPFMul01], 3, [1], 1>; // Floating point reciprocal estimate.
+defm : Zn3WriteResXMMPair<WriteFRcpX, [Zn3FPFMul01], 3, [1], 1>; // Floating point reciprocal estimate (XMM).
+defm : Zn3WriteResYMMPair<WriteFRcpY, [Zn3FPFMul01], 3, [1], 1>; // Floating point reciprocal estimate (YMM).
+defm : X86WriteResPairUnsupported<WriteFRcpZ>; // Floating point reciprocal estimate (ZMM).
+defm : Zn3WriteResXMMPair<WriteFRsqrt, [Zn3FPFDiv], 3, [1], 1>; // Floating point reciprocal square root estimate.
+defm : Zn3WriteResXMMPair<WriteFRsqrtX, [Zn3FPFDiv], 3, [1], 1>; // Floating point reciprocal square root estimate (XMM).
+defm : Zn3WriteResYMMPair<WriteFRsqrtY, [Zn3FPFDiv], 3, [1], 1>; // Floating point reciprocal square root estimate (YMM).
+defm : X86WriteResPairUnsupported<WriteFRsqrtZ>; // Floating point reciprocal square root estimate (ZMM).
+defm : Zn3WriteResXMMPair<WriteFMA, [Zn3FPFMul01], 4, [2], 1>; // Fused Multiply Add.
+defm : Zn3WriteResXMMPair<WriteFMAX, [Zn3FPFMul01], 4, [2], 1>; // Fused Multiply Add (XMM).
+defm : Zn3WriteResYMMPair<WriteFMAY, [Zn3FPFMul01], 4, [2], 1>; // Fused Multiply Add (YMM).
+defm : X86WriteResPairUnsupported<WriteFMAZ>; // Fused Multiply Add (ZMM).
+defm : Zn3WriteResXMMPair<WriteDPPD, [Zn3FPFMul01], 9, [6], 3, /*LoadUOps=*/2>; // Floating point double dot product.
+defm : Zn3WriteResXMMPair<WriteDPPS, [Zn3FPFMul01], 15, [8], 8, /*LoadUOps=*/2>; // Floating point single dot product.
+defm : Zn3WriteResYMMPair<WriteDPPSY, [Zn3FPFMul01], 15, [8], 7, /*LoadUOps=*/1>; // Floating point single dot product (YMM).
+defm : X86WriteResPairUnsupported<WriteDPPSZ>; // Floating point single dot product (ZMM).
+defm : Zn3WriteResXMMPair<WriteFSign, [Zn3FPFMul01], 1, [2], 1>; // FIXME: latency not from llvm-exegesis // Floating point fabs/fchs.
+defm : Zn3WriteResXMMPair<WriteFRnd, [Zn3FPFCvt01], 3, [1], 1>; // Floating point rounding.
+defm : Zn3WriteResYMMPair<WriteFRndY, [Zn3FPFCvt01], 3, [1], 1>; // Floating point rounding (YMM).
+defm : X86WriteResPairUnsupported<WriteFRndZ>; // Floating point rounding (ZMM).
+defm : Zn3WriteResXMMPair<WriteFLogic, [Zn3FPVMisc0123], 1, [1], 1>; // Floating point and/or/xor logicals.
+defm : Zn3WriteResYMMPair<WriteFLogicY, [Zn3FPVMisc0123], 1, [1], 1>; // Floating point and/or/xor logicals (YMM).
+defm : X86WriteResPairUnsupported<WriteFLogicZ>; // Floating point and/or/xor logicals (ZMM).
+defm : Zn3WriteResXMMPair<WriteFTest, [Zn3FPFMisc12], 1, [2], 2>; // FIXME: latency not from llvm-exegesis // Floating point TEST instructions.
+defm : Zn3WriteResYMMPair<WriteFTestY, [Zn3FPFMisc12], 1, [2], 2>; // FIXME: latency not from llvm-exegesis // Floating point TEST instructions (YMM).
+defm : X86WriteResPairUnsupported<WriteFTestZ>; // Floating point TEST instructions (ZMM).
+defm : Zn3WriteResXMMPair<WriteFShuffle, [Zn3FPVShuf01], 1, [1], 1>; // Floating point vector shuffles.
+defm : Zn3WriteResYMMPair<WriteFShuffleY, [Zn3FPVShuf01], 1, [1], 1>; // Floating point vector shuffles (YMM).
+defm : X86WriteResPairUnsupported<WriteFShuffleZ>; // Floating point vector shuffles (ZMM).
+defm : Zn3WriteResXMMPair<WriteFVarShuffle, [Zn3FPVShuf01], 3, [1], 1>; // Floating point vector variable shuffles.
+defm : Zn3WriteResYMMPair<WriteFVarShuffleY, [Zn3FPVShuf01], 3, [1], 1>; // Floating point vector variable shuffles (YMM).
+defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>; // Floating point vector variable shuffles (ZMM).
+defm : Zn3WriteResXMMPair<WriteFBlend, [Zn3FPFMul01], 1, [1], 1>; // Floating point vector blends.
+defm : Zn3WriteResYMMPair<WriteFBlendY, [Zn3FPFMul01], 1, [1], 1>; // Floating point vector blends (YMM).
+defm : X86WriteResPairUnsupported<WriteFBlendZ>; // Floating point vector blends (ZMM).
+defm : Zn3WriteResXMMPair<WriteFVarBlend, [Zn3FPFMul01], 1, [1], 1>; // Fp vector variable blends.
+defm : Zn3WriteResYMMPair<WriteFVarBlendY, [Zn3FPFMul01], 1, [1], 1>; // Fp vector variable blends (YMM).
+defm : X86WriteResPairUnsupported<WriteFVarBlendZ>; // Fp vector variable blends (ZMM).
+
+// Horizontal Add/Sub (float and integer)
+defm : Zn3WriteResXMMPair<WriteFHAdd, [Zn3FPFAdd0], 6, [2], 4>;
+defm : Zn3WriteResYMMPair<WriteFHAddY, [Zn3FPFAdd0], 6, [2], 3, /*LoadUOps=*/1>;
+defm : X86WriteResPairUnsupported<WriteFHAddZ>;
+defm : Zn3WriteResXMMPair<WritePHAdd, [Zn3FPVAdd0], 2, [2], 3, /*LoadUOps=*/1>;
+defm : Zn3WriteResXMMPair<WritePHAddX, [Zn3FPVAdd0], 2, [2], 4>;
+defm : Zn3WriteResYMMPair<WritePHAddY, [Zn3FPVAdd0], 2, [2], 3, /*LoadUOps=*/1>;
+defm : X86WriteResPairUnsupported<WritePHAddZ>;
+
+// Vector integer operations.
+defm : Zn3WriteResXMM<WriteVecLoad, [Zn3FPLd01, Zn3Load], !add(Znver3Model.VecLoadLatency, 1), [1, 1], 1>;
+defm : Zn3WriteResXMM<WriteVecLoadX, [Zn3FPLd01, Zn3Load], !add(Znver3Model.VecLoadLatency, 1), [1, 1], 1>;
+defm : Zn3WriteResYMM<WriteVecLoadY, [Zn3FPLd01, Zn3Load], !add(Znver3Model.VecLoadLatency, 1), [1, 1], 1>;
+defm : Zn3WriteResXMM<WriteVecLoadNT, [Zn3FPLd01, Zn3Load], !add(Znver3Model.VecLoadLatency, 1), [1, 1], 1>;
+defm : Zn3WriteResYMM<WriteVecLoadNTY, [Zn3FPLd01, Zn3Load], !add(Znver3Model.VecLoadLatency, 1), [1, 1], 1>;
+defm : Zn3WriteResXMM<WriteVecMaskedLoad, [Zn3FPLd01, Zn3Load], !add(Znver3Model.VecLoadLatency, 1), [1, 1], 1>;
+defm : Zn3WriteResYMM<WriteVecMaskedLoadY, [Zn3FPLd01, Zn3Load], !add(Znver3Model.VecLoadLatency, 1), [1, 1], 1>;
+defm : Zn3WriteResXMM<WriteVecStore, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [1, 1], 1>;
+defm : Zn3WriteResXMM<WriteVecStoreX, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [1, 1], 1>;
+
+def Zn3WriteVEXTRACTF128rr_VEXTRACTI128rr : SchedWriteRes<[Zn3FPFMisc0]> {
+ let Latency = 4;
+ let ResourceCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[Zn3WriteVEXTRACTF128rr_VEXTRACTI128rr], (instrs VEXTRACTF128rr, VEXTRACTI128rr)>;
+
+def Zn3WriteVEXTRACTI128mr : SchedWriteRes<[Zn3FPFMisc0, Zn3FPSt, Zn3Store]> {
+ let Latency = !add(Znver3Model.LoadLatency, Zn3WriteVEXTRACTF128rr_VEXTRACTI128rr.Latency);
+ let ResourceCycles = [1, 1, 1];
+ let NumMicroOps = !add(Zn3WriteVEXTRACTF128rr_VEXTRACTI128rr.NumMicroOps, 1);
+}
+def : InstRW<[Zn3WriteVEXTRACTI128mr], (instrs VEXTRACTI128mr, VEXTRACTF128mr)>;
+
+def Zn3WriteVINSERTF128rmr : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPFMisc0]> {
+ let Latency = !add(Znver3Model.LoadLatency, Zn3WriteVEXTRACTF128rr_VEXTRACTI128rr.Latency);
+ let ResourceCycles = [1, 1, 1];
+ let NumMicroOps = !add(Zn3WriteVEXTRACTF128rr_VEXTRACTI128rr.NumMicroOps, 0);
+}
+def : InstRW<[Zn3WriteVINSERTF128rmr], (instrs VINSERTF128rm)>;
+
+defm : Zn3WriteResYMM<WriteVecStoreY, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [1, 1], 1>;
+defm : Zn3WriteResXMM<WriteVecStoreNT, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [1, 1], 1>;
+defm : Zn3WriteResYMM<WriteVecStoreNTY, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [1, 1], 1>;
+defm : Zn3WriteResXMM<WriteVecMaskedStore32, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [6, 1], 18>;
+defm : Zn3WriteResXMM<WriteVecMaskedStore64, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [4, 1], 10>;
+defm : Zn3WriteResYMM<WriteVecMaskedStore32Y, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [12, 1], 42>;
+defm : Zn3WriteResYMM<WriteVecMaskedStore64Y, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [6, 1], 18>;
+defm : Zn3WriteResXMM<WriteVecMove, [Zn3FPFMisc0123], 1, [1], 1>;
+defm : Zn3WriteResXMM<WriteVecMoveX, [Zn3FPFMisc0123], 0, [1], 1>;
+defm : Zn3WriteResYMM<WriteVecMoveY, [Zn3FPFMisc0123], 0, [1], 1>;
+defm : Zn3WriteResXMM<WriteVecMoveToGpr, [Zn3FPLd01], 1, [2], 1>;
+defm : Zn3WriteResXMM<WriteVecMoveFromGpr, [Zn3FPLd01], 1, [2], 1>;
+
+def Zn3WriteMOVMMX : SchedWriteRes<[Zn3FPLd01, Zn3FPFMisc0123]> {
+ let Latency = 1;
+ let ResourceCycles = [1, 2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[Zn3WriteMOVMMX], (instrs MMX_MOVQ2FR64rr, MMX_MOVQ2DQrr)>;
+
+def Zn3WriteMOVMMXSlow : SchedWriteRes<[Zn3FPLd01, Zn3FPFMisc0123]> {
+ let Latency = 1;
+ let ResourceCycles = [1, 4];
+ let NumMicroOps = 2;
+}
+def : InstRW<[Zn3WriteMOVMMXSlow], (instrs MMX_MOVD64rr, MMX_MOVD64to64rr)>;
+
+defm : Zn3WriteResXMMPair<WriteVecALU, [Zn3FPVAdd0123], 1, [1], 1>; // Vector integer ALU op, no logicals.
+
+def Zn3WriteEXTRQ_INSERTQ : SchedWriteRes<[Zn3FPVShuf01, Zn3FPLd01]> {
+ let Latency = 3;
+ let ResourceCycles = [1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[Zn3WriteEXTRQ_INSERTQ], (instrs EXTRQ, INSERTQ)>;
+
+def Zn3WriteEXTRQI_INSERTQI : SchedWriteRes<[Zn3FPVShuf01, Zn3FPLd01]> {
+ let Latency = 3;
+ let ResourceCycles = [1, 1];
+ let NumMicroOps = 2;
+}
+def : InstRW<[Zn3WriteEXTRQI_INSERTQI], (instrs EXTRQI, INSERTQI)>;
+
+defm : Zn3WriteResXMMPair<WriteVecALUX, [Zn3FPVAdd0123], 1, [1], 1>; // Vector integer ALU op, no logicals (XMM).
+
+def Zn3WriteVecALUXSlow : SchedWriteRes<[Zn3FPVAdd01]> {
+ let Latency = 1;
+ let ResourceCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[Zn3WriteVecALUXSlow], (instrs PABSBrr, PABSDrr, PABSWrr,
+ PADDSBrr, PADDSWrr, PADDUSBrr, PADDUSWrr,
+ PAVGBrr, PAVGWrr,
+ PSIGNBrr, PSIGNDrr, PSIGNWrr,
+ VPABSBrr, VPABSDrr, VPABSWrr,
+ VPADDSBrr, VPADDSWrr, VPADDUSBrr, VPADDUSWrr,
+ VPAVGBrr, VPAVGWrr,
+ VPCMPEQQrr,
+ VPSIGNBrr, VPSIGNDrr, VPSIGNWrr,
+ PSUBSBrr, PSUBSWrr, PSUBUSBrr, PSUBUSWrr, VPSUBSBrr, VPSUBSWrr, VPSUBUSBrr, VPSUBUSWrr)>;
+
+def Zn3WriteVecALUXMMX : SchedWriteRes<[Zn3FPVAdd01]> {
+ let Latency = 1;
+ let ResourceCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[Zn3WriteVecALUXMMX], (instrs MMX_PABSBrr, MMX_PABSDrr, MMX_PABSWrr,
+ MMX_PSIGNBrr, MMX_PSIGNDrr, MMX_PSIGNWrr,
+ MMX_PADDSBirr, MMX_PADDSWirr, MMX_PADDUSBirr, MMX_PADDUSWirr,
+ MMX_PAVGBirr, MMX_PAVGWirr,
+ MMX_PSUBSBirr, MMX_PSUBSWirr, MMX_PSUBUSBirr, MMX_PSUBUSWirr)>;
+
+defm : Zn3WriteResYMMPair<WriteVecALUY, [Zn3FPVAdd0123], 1, [1], 1>; // Vector integer ALU op, no logicals (YMM).
+
+def Zn3WriteVecALUYSlow : SchedWriteRes<[Zn3FPVAdd01]> {
+ let Latency = 1;
+ let ResourceCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[Zn3WriteVecALUYSlow], (instrs VPABSBYrr, VPABSDYrr, VPABSWYrr,
+ VPADDSBYrr, VPADDSWYrr, VPADDUSBYrr, VPADDUSWYrr,
+ VPSUBSBYrr, VPSUBSWYrr, VPSUBUSBYrr, VPSUBUSWYrr,
+ VPAVGBYrr, VPAVGWYrr,
+ VPCMPEQQYrr,
+ VPSIGNBYrr, VPSIGNDYrr, VPSIGNWYrr)>;
+
+defm : X86WriteResPairUnsupported<WriteVecALUZ>; // Vector integer ALU op, no logicals (ZMM).
+defm : Zn3WriteResXMMPair<WriteVecLogic, [Zn3FPVMisc0123], 1, [1], 1>; // Vector integer and/or/xor logicals.
+defm : Zn3WriteResXMMPair<WriteVecLogicX, [Zn3FPVMisc0123], 1, [1], 1>; // Vector integer and/or/xor logicals (XMM).
+defm : Zn3WriteResYMMPair<WriteVecLogicY, [Zn3FPVMisc0123], 1, [1], 1>; // Vector integer and/or/xor logicals (YMM).
+defm : X86WriteResPairUnsupported<WriteVecLogicZ>; // Vector integer and/or/xor logicals (ZMM).
+defm : Zn3WriteResXMMPair<WriteVecTest, [Zn3FPVAdd12, Zn3FPSt], 1, [1, 1], 2>; // FIXME: latency not from llvm-exegesis // Vector integer TEST instructions.
+defm : Zn3WriteResYMMPair<WriteVecTestY, [Zn3FPVAdd12, Zn3FPSt], 1, [1, 1], 2>; // FIXME: latency not from llvm-exegesis // Vector integer TEST instructions (YMM).
+defm : X86WriteResPairUnsupported<WriteVecTestZ>; // Vector integer TEST instructions (ZMM).
+defm : Zn3WriteResXMMPair<WriteVecShift, [Zn3FPVShift01], 1, [1], 1>; // Vector integer shifts (default).
+defm : Zn3WriteResXMMPair<WriteVecShiftX, [Zn3FPVShift01], 1, [1], 1>; // Vector integer shifts (XMM).
+defm : Zn3WriteResYMMPair<WriteVecShiftY, [Zn3FPVShift01], 1, [1], 1>; // Vector integer shifts (YMM).
+defm : X86WriteResPairUnsupported<WriteVecShiftZ>; // Vector integer shifts (ZMM).
+defm : Zn3WriteResXMMPair<WriteVecShiftImm, [Zn3FPVShift01], 1, [1], 1>; // Vector integer immediate shifts (default).
+defm : Zn3WriteResXMMPair<WriteVecShiftImmX, [Zn3FPVShift01], 1, [1], 1>; // Vector integer immediate shifts (XMM).
+defm : Zn3WriteResYMMPair<WriteVecShiftImmY, [Zn3FPVShift01], 1, [1], 1>; // Vector integer immediate shifts (YMM).
+defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>; // Vector integer immediate shifts (ZMM).
+defm : Zn3WriteResXMMPair<WriteVecIMul, [Zn3FPVMul01], 3, [1], 1>; // Vector integer multiply (default).
+defm : Zn3WriteResXMMPair<WriteVecIMulX, [Zn3FPVMul01], 3, [1], 1>; // Vector integer multiply (XMM).
+defm : Zn3WriteResYMMPair<WriteVecIMulY, [Zn3FPVMul01], 3, [1], 1>; // Vector integer multiply (YMM).
+defm : X86WriteResPairUnsupported<WriteVecIMulZ>; // Vector integer multiply (ZMM).
+defm : Zn3WriteResXMMPair<WritePMULLD, [Zn3FPVMul01], 3, [1], 1>; // Vector PMULLD.
+defm : Zn3WriteResYMMPair<WritePMULLDY, [Zn3FPVMul01], 3, [1], 1>; // Vector PMULLD (YMM).
+defm : X86WriteResPairUnsupported<WritePMULLDZ>; // Vector PMULLD (ZMM).
+defm : Zn3WriteResXMMPair<WriteShuffle, [Zn3FPVShuf01], 1, [1], 1>; // Vector shuffles.
+defm : Zn3WriteResXMMPair<WriteShuffleX, [Zn3FPVShuf01], 1, [1], 1>; // Vector shuffles (XMM).
+defm : Zn3WriteResYMMPair<WriteShuffleY, [Zn3FPVShuf01], 1, [1], 1>; // Vector shuffles (YMM).
+defm : X86WriteResPairUnsupported<WriteShuffleZ>; // Vector shuffles (ZMM).
+defm : Zn3WriteResXMMPair<WriteVarShuffle, [Zn3FPVShift01], 1, [1], 1>; // Vector variable shuffles.
+defm : Zn3WriteResXMMPair<WriteVarShuffleX, [Zn3FPVShift01], 1, [1], 1>; // Vector variable shuffles (XMM).
+defm : Zn3WriteResYMMPair<WriteVarShuffleY, [Zn3FPVShift01], 1, [1], 1>; // Vector variable shuffles (YMM).
+defm : X86WriteResPairUnsupported<WriteVarShuffleZ>; // Vector variable shuffles (ZMM).
+defm : Zn3WriteResXMMPair<WriteBlend, [Zn3FPVMisc0123], 1, [1], 1>; // Vector blends.
+defm : Zn3WriteResYMMPair<WriteBlendY, [Zn3FPVMisc0123], 1, [1], 1>; // Vector blends (YMM).
+defm : X86WriteResPairUnsupported<WriteBlendZ>; // Vector blends (ZMM).
+defm : Zn3WriteResXMMPair<WriteVarBlend, [Zn3FPVMul01], 1, [1], 1>; // Vector variable blends.
+defm : Zn3WriteResYMMPair<WriteVarBlendY, [Zn3FPVMul01], 1, [1], 1>; // Vector variable blends (YMM).
+defm : X86WriteResPairUnsupported<WriteVarBlendZ>; // Vector variable blends (ZMM).
+defm : Zn3WriteResXMMPair<WritePSADBW, [Zn3FPVAdd0123], 3, [2], 1>; // Vector PSADBW.
+defm : Zn3WriteResXMMPair<WritePSADBWX, [Zn3FPVAdd0123], 3, [2], 1>; // Vector PSADBW (XMM).
+defm : Zn3WriteResYMMPair<WritePSADBWY, [Zn3FPVAdd0123], 3, [2], 1>; // Vector PSADBW (YMM).
+defm : X86WriteResPairUnsupported<WritePSADBWZ>; // Vector PSADBW (ZMM).
+defm : Zn3WriteResXMMPair<WriteMPSAD, [Zn3FPVAdd0123], 4, [8], 4, /*LoadUOps=*/2>; // Vector MPSAD.
+defm : Zn3WriteResYMMPair<WriteMPSADY, [Zn3FPVAdd0123], 4, [8], 3, /*LoadUOps=*/1>; // Vector MPSAD (YMM).
+defm : X86WriteResPairUnsupported<WriteMPSADZ>; // Vector MPSAD (ZMM).
+defm : Zn3WriteResXMMPair<WritePHMINPOS, [Zn3FPVAdd01], 3, [1], 1>; // Vector PHMINPOS.
+
+// Vector insert/extract operations.
+defm : Zn3WriteResXMMPair<WriteVecInsert, [Zn3FPLd01], 1, [2], 2, /*LoadUOps=*/-1>; // Insert gpr to vector element.
+defm : Zn3WriteResXMM<WriteVecExtract, [Zn3FPLd01], 1, [2], 2>; // Extract vector element to gpr.
+defm : Zn3WriteResXMM<WriteVecExtractSt, [Zn3FPSt, Zn3Store], !add(1, Znver3Model.StoreLatency), [1, 1], 2>; // Extract vector element and store.
+
+// MOVMSK operations.
+defm : Zn3WriteResXMM<WriteFMOVMSK, [Zn3FPVMisc2], 1, [1], 1>;
+defm : Zn3WriteResXMM<WriteVecMOVMSK, [Zn3FPVMisc2], 1, [1], 1>;
+defm : Zn3WriteResYMM<WriteVecMOVMSKY, [Zn3FPVMisc2], 1, [1], 1>;
+defm : Zn3WriteResXMM<WriteMMXMOVMSK, [Zn3FPVMisc2], 1, [1], 1>;
+
+// Conversion between integer and float.
+defm : Zn3WriteResXMMPair<WriteCvtSD2I, [Zn3FPFCvt01], 2, [2], 2>; // Double -> Integer.
+defm : Zn3WriteResXMMPair<WriteCvtPD2I, [Zn3FPFCvt01], 3, [1], 1>; // Double -> Integer (XMM).
+defm : Zn3WriteResYMMPair<WriteCvtPD2IY, [Zn3FPFCvt01], 6, [2], 2>; // Double -> Integer (YMM).
+defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>; // Double -> Integer (ZMM).
+
+def Zn3WriteCvtPD2IMMX : SchedWriteRes<[Zn3FPFCvt01]> {
+ let Latency = 1;
+ let ResourceCycles = [2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[Zn3WriteCvtPD2IMMX], (instrs MMX_CVTPD2PIirm, MMX_CVTTPD2PIirm, MMX_CVTPD2PIirr, MMX_CVTTPD2PIirr)>;
+
+defm : Zn3WriteResXMMPair<WriteCvtSS2I, [Zn3FPFCvt01], 2, [2], 2>; // Float -> Integer.
+
+defm : Zn3WriteResXMMPair<WriteCvtPS2I, [Zn3FPFCvt01], 3, [1], 1>; // Float -> Integer (XMM).
+defm : Zn3WriteResYMMPair<WriteCvtPS2IY, [Zn3FPFCvt01], 3, [1], 1>; // Float -> Integer (YMM).
+defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>; // Float -> Integer (ZMM).
+
+defm : Zn3WriteResXMMPair<WriteCvtI2SD, [Zn3FPFCvt01], 3, [2], 2, /*LoadUOps=*/-1>; // Integer -> Double.
+defm : Zn3WriteResXMMPair<WriteCvtI2PD, [Zn3FPFCvt01], 3, [1], 1>; // Integer -> Double (XMM).
+defm : Zn3WriteResYMMPair<WriteCvtI2PDY, [Zn3FPFCvt01], 4, [2], 2, /*LoadUOps=*/-1>; // Integer -> Double (YMM).
+defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>; // Integer -> Double (ZMM).
+
+def Zn3WriteCvtI2PDMMX : SchedWriteRes<[Zn3FPFCvt01]> {
+ let Latency = 2;
+ let ResourceCycles = [6];
+ let NumMicroOps = 2;
+}
+def : InstRW<[Zn3WriteCvtI2PDMMX], (instrs MMX_CVTPI2PDirm, MMX_CVTPI2PDirr)>;
+
+defm : Zn3WriteResXMMPair<WriteCvtI2SS, [Zn3FPFCvt01], 3, [2], 2, /*LoadUOps=*/-1>; // Integer -> Float.
+defm : Zn3WriteResXMMPair<WriteCvtI2PS, [Zn3FPFCvt01], 3, [1], 1>; // Integer -> Float (XMM).
+defm : Zn3WriteResYMMPair<WriteCvtI2PSY, [Zn3FPFCvt01], 3, [1], 1>; // Integer -> Float (YMM).
+defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>; // Integer -> Float (ZMM).
+
+def Zn3WriteCvtI2PSMMX : SchedWriteRes<[Zn3FPFCvt01]> {
+ let Latency = 3;
+ let ResourceCycles = [1];
+ let NumMicroOps = 2;
+}
+def : InstRW<[Zn3WriteCvtI2PSMMX], (instrs MMX_CVTPI2PSirr)>;
+
+defm : Zn3WriteResXMMPair<WriteCvtSS2SD, [Zn3FPFCvt01], 3, [1], 1>; // Float -> Double size conversion.
+defm : Zn3WriteResXMMPair<WriteCvtPS2PD, [Zn3FPFCvt01], 3, [1], 1>; // Float -> Double size conversion (XMM).
+defm : Zn3WriteResYMMPair<WriteCvtPS2PDY, [Zn3FPFCvt01], 4, [2], 2, /*LoadUOps=*/-1>; // Float -> Double size conversion (YMM).
+defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>; // Float -> Double size conversion (ZMM).
+
+defm : Zn3WriteResXMMPair<WriteCvtSD2SS, [Zn3FPFCvt01], 3, [1], 1>; // Double -> Float size conversion.
+defm : Zn3WriteResXMMPair<WriteCvtPD2PS, [Zn3FPFCvt01], 3, [1], 1>; // Double -> Float size conversion (XMM).
+defm : Zn3WriteResYMMPair<WriteCvtPD2PSY, [Zn3FPFCvt01], 6, [2], 2>; // Double -> Float size conversion (YMM).
+defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>; // Double -> Float size conversion (ZMM).
+
+defm : Zn3WriteResXMMPair<WriteCvtPH2PS, [Zn3FPFCvt01], 3, [1], 1>; // Half -> Float size conversion.
+defm : Zn3WriteResYMMPair<WriteCvtPH2PSY, [Zn3FPFCvt01], 4, [2], 2, /*LoadUOps=*/-1>; // Half -> Float size conversion (YMM).
+defm : X86WriteResPairUnsupported<WriteCvtPH2PSZ>; // Half -> Float size conversion (ZMM).
+
+defm : Zn3WriteResXMM<WriteCvtPS2PH, [Zn3FPFCvt01], 3, [2], 1>; // Float -> Half size conversion.
+defm : Zn3WriteResYMM<WriteCvtPS2PHY, [Zn3FPFCvt01], 6, [2], 2>; // Float -> Half size conversion (YMM).
+defm : X86WriteResUnsupported<WriteCvtPS2PHZ>; // Float -> Half size conversion (ZMM).
+defm : Zn3WriteResXMM<WriteCvtPS2PHSt, [Zn3FPFCvt01, Zn3FPSt, Zn3Store], !add(3, Znver3Model.StoreLatency), [1, 1, 1], 2>; // Float -> Half + store size conversion.
+defm : Zn3WriteResYMM<WriteCvtPS2PHYSt, [Zn3FPFCvt01, Zn3FPSt, Zn3Store], !add(6, Znver3Model.StoreLatency), [2, 1, 1], 3>; // Float -> Half + store size conversion (YMM).
+defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>; // Float -> Half + store size conversion (ZMM).
+
+// CRC32 instruction.
+defm : Zn3WriteResIntPair<WriteCRC32, [Zn3ALU1], 3, [1], 1>;
+
+def Zn3WriteSHA1MSG1rr : SchedWriteRes<[Zn3FPU0123]> {
+ let Latency = 2;
+ let ResourceCycles = [2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[Zn3WriteSHA1MSG1rr], (instrs SHA1MSG1rr)>;
+
+def Zn3WriteSHA1MSG1rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPU0123]> {
+ let Latency = !add(Znver3Model.LoadLatency, Zn3WriteSHA1MSG1rr.Latency);
+ let ResourceCycles = [1, 1, 2];
+ let NumMicroOps = !add(Zn3WriteSHA1MSG1rr.NumMicroOps, 0);
+}
+def : InstRW<[Zn3WriteSHA1MSG1rm], (instrs SHA1MSG1rm)>;
+
+def Zn3WriteSHA1MSG2rr_SHA1NEXTErr : SchedWriteRes<[Zn3FPU0123]> {
+ let Latency = 1;
+ let ResourceCycles = [2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[Zn3WriteSHA1MSG2rr_SHA1NEXTErr], (instrs SHA1MSG2rr, SHA1NEXTErr)>;
+
+def Zn3Writerm_SHA1MSG2rm_SHA1NEXTErm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPU0123]> {
+ let Latency = !add(Znver3Model.LoadLatency, Zn3WriteSHA1MSG2rr_SHA1NEXTErr.Latency);
+ let ResourceCycles = [1, 1, 2];
+ let NumMicroOps = !add(Zn3WriteSHA1MSG2rr_SHA1NEXTErr.NumMicroOps, 0);
+}
+def : InstRW<[Zn3Writerm_SHA1MSG2rm_SHA1NEXTErm], (instrs SHA1MSG2rm, SHA1NEXTErm)>;
+
+def Zn3WriteSHA256MSG1rr : SchedWriteRes<[Zn3FPU0123]> {
+ let Latency = 2;
+ let ResourceCycles = [3];
+ let NumMicroOps = 2;
+}
+def : InstRW<[Zn3WriteSHA256MSG1rr], (instrs SHA256MSG1rr)>;
+
+def Zn3Writerm_SHA256MSG1rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPU0123]> {
+ let Latency = !add(Znver3Model.LoadLatency, Zn3WriteSHA256MSG1rr.Latency);
+ let ResourceCycles = [1, 1, 3];
+ let NumMicroOps = !add(Zn3WriteSHA256MSG1rr.NumMicroOps, 0);
+}
+def : InstRW<[Zn3Writerm_SHA256MSG1rm], (instrs SHA256MSG1rm)>;
+
+def Zn3WriteSHA256MSG2rr : SchedWriteRes<[Zn3FPU0123]> {
+ let Latency = 3;
+ let ResourceCycles = [8];
+ let NumMicroOps = 4;
+}
+def : InstRW<[Zn3WriteSHA256MSG2rr], (instrs SHA256MSG2rr)>;
+
+def Zn3WriteSHA256MSG2rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPU0123]> {
+ let Latency = !add(Znver3Model.LoadLatency, Zn3WriteSHA256MSG2rr.Latency);
+ let ResourceCycles = [1, 1, 8];
+ let NumMicroOps = !add(Zn3WriteSHA256MSG2rr.NumMicroOps, 1);
+}
+def : InstRW<[Zn3WriteSHA256MSG2rm], (instrs SHA256MSG2rm)>;
+
+def Zn3WriteSHA1RNDS4rri : SchedWriteRes<[Zn3FPU0123]> {
+ let Latency = 6;
+ let ResourceCycles = [8];
+ let NumMicroOps = 1;
+}
+def : InstRW<[Zn3WriteSHA1RNDS4rri], (instrs SHA1RNDS4rri)>;
+
+def Zn3WriteSHA256RNDS2rr : SchedWriteRes<[Zn3FPU0123]> {
+ let Latency = 4;
+ let ResourceCycles = [8];
+ let NumMicroOps = 1;
+}
+def : InstRW<[Zn3WriteSHA256RNDS2rr], (instrs SHA256RNDS2rr)>;
+
+// Strings instructions.
+// Packed Compare Implicit Length Strings, Return Mask
+defm : Zn3WriteResXMMPair<WritePCmpIStrM, [Zn3FPVAdd0123], 6, [8], 3, /*LoadUOps=*/1>;
+// Packed Compare Explicit Length Strings, Return Mask
+defm : Zn3WriteResXMMPair<WritePCmpEStrM, [Zn3FPVAdd0123], 6, [12], 7, /*LoadUOps=*/5>;
+// Packed Compare Implicit Length Strings, Return Index
+defm : Zn3WriteResXMMPair<WritePCmpIStrI, [Zn3FPVAdd0123], 2, [8], 4>;
+// Packed Compare Explicit Length Strings, Return Index
+defm : Zn3WriteResXMMPair<WritePCmpEStrI, [Zn3FPVAdd0123], 6, [12], 8, /*LoadUOps=*/4>;
+
+// AES instructions.
+defm : Zn3WriteResXMMPair<WriteAESDecEnc, [Zn3FPAES01], 4, [1], 1>; // Decryption, encryption.
+defm : Zn3WriteResXMMPair<WriteAESIMC, [Zn3FPAES01], 4, [1], 1>; // InvMixColumn.
+defm : Zn3WriteResXMMPair<WriteAESKeyGen, [Zn3FPAES01], 4, [1], 1>; // Key Generation.
+
+// Carry-less multiplication instructions.
+defm : Zn3WriteResXMMPair<WriteCLMul, [Zn3FPCLM01], 4, [4], 4>;
+
+// EMMS/FEMMS
+defm : Zn3WriteResInt<WriteEMMS, [Zn3ALU0123], 2, [1], 1>; // FIXME: latency not from llvm-exegesis
+
+// Load/store MXCSR
+defm : Zn3WriteResInt<WriteLDMXCSR, [Zn3AGU012, Zn3Load, Zn3ALU0123], !add(Znver3Model.LoadLatency, 1), [1, 1, 6], 1>; // FIXME: latency not from llvm-exegesis
+defm : Zn3WriteResInt<WriteSTMXCSR, [Zn3ALU0123, Zn3AGU012, Zn3Store], !add(1, Znver3Model.StoreLatency), [60, 1, 1], 2>; // FIXME: latency not from llvm-exegesis
+
+// Catch-all for expensive system instructions.
+defm : Zn3WriteResInt<WriteSystem, [Zn3ALU0123], 100, [100], 100>;
+
+def Zn3WriteVZEROUPPER : SchedWriteRes<[Zn3FPU0123]> {
+ let Latency = 0; // FIXME: not from llvm-exegesis
+ let ResourceCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[Zn3WriteVZEROUPPER], (instrs VZEROUPPER)>;
+
+def Zn3WriteVZEROALL : SchedWriteRes<[Zn3FPU0123]> {
+ let Latency = 10; // FIXME: not from llvm-exegesis
+ let ResourceCycles = [24];
+ let NumMicroOps = 18;
+}
+def : InstRW<[Zn3WriteVZEROALL], (instrs VZEROALL)>;
+
+// AVX2.
+defm : Zn3WriteResYMMPair<WriteFShuffle256, [Zn3FPVShuf], 2, [1], 1, /*LoadUOps=*/2>; // Fp 256-bit width vector shuffles.
+defm : Zn3WriteResYMMPair<WriteFVarShuffle256, [Zn3FPVShuf], 7, [1], 2, /*LoadUOps=*/1>; // Fp 256-bit width variable shuffles.
+defm : Zn3WriteResYMMPair<WriteShuffle256, [Zn3FPVShuf], 2, [1], 1>; // 256-bit width vector shuffles.
+
+def Zn3WriteVPERM2I128rr_VPERM2F128rr : SchedWriteRes<[Zn3FPVShuf]> {
+ let Latency = 3;
+ let ResourceCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[Zn3WriteVPERM2I128rr_VPERM2F128rr], (instrs VPERM2I128rr, VPERM2F128rr)>;
+
+def Zn3WriteVPERM2F128rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPVShuf]> {
+ let Latency = !add(Znver3Model.LoadLatency, Zn3WriteVPERM2I128rr_VPERM2F128rr.Latency);
+ let ResourceCycles = [1, 1, 1];
+ let NumMicroOps = !add(Zn3WriteVPERM2I128rr_VPERM2F128rr.NumMicroOps, 0);
+}
+def : InstRW<[Zn3WriteVPERM2F128rm], (instrs VPERM2F128rm)>;
+
+def Zn3WriteVPERMPSYrr : SchedWriteRes<[Zn3FPVShuf]> {
+ let Latency = 7;
+ let ResourceCycles = [1];
+ let NumMicroOps = 2;
+}
+def : InstRW<[Zn3WriteVPERMPSYrr], (instrs VPERMPSYrr)>;
+
+def Zn3WriteVPERMPSYrm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPVShuf]> {
+ let Latency = !add(Znver3Model.LoadLatency, Zn3WriteVPERMPSYrr.Latency);
+ let ResourceCycles = [1, 1, 2];
+ let NumMicroOps = !add(Zn3WriteVPERMPSYrr.NumMicroOps, 1);
+}
+def : InstRW<[Zn3WriteVPERMPSYrm], (instrs VPERMPSYrm)>;
+
+def Zn3WriteVPERMYri : SchedWriteRes<[Zn3FPVShuf]> {
+ let Latency = 6;
+ let ResourceCycles = [1];
+ let NumMicroOps = 2;
+}
+def : InstRW<[Zn3WriteVPERMYri], (instrs VPERMPDYri, VPERMQYri)>;
+
+def Zn3WriteVPERMPDYmi : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPVShuf]> {
+ let Latency = !add(Znver3Model.LoadLatency, Zn3WriteVPERMYri.Latency);
+ let ResourceCycles = [1, 1, 2];
+ let NumMicroOps = !add(Zn3WriteVPERMYri.NumMicroOps, 1);
+}
+def : InstRW<[Zn3WriteVPERMPDYmi], (instrs VPERMPDYmi)>;
+
+def Zn3WriteVPERMDYrr : SchedWriteRes<[Zn3FPVShuf]> {
+ let Latency = 5;
+ let ResourceCycles = [1];
+ let NumMicroOps = 2;
+}
+def : InstRW<[Zn3WriteVPERMDYrr], (instrs VPERMDYrr)>;
+
+def Zn3WriteVPERMYm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPVShuf]> {
+ let Latency = !add(Znver3Model.LoadLatency, Zn3WriteVPERMDYrr.Latency);
+ let ResourceCycles = [1, 1, 2];
+ let NumMicroOps = !add(Zn3WriteVPERMDYrr.NumMicroOps, 0);
+}
+def : InstRW<[Zn3WriteVPERMYm], (instrs VPERMQYmi, VPERMDYrm)>;
+
+defm : Zn3WriteResYMMPair<WriteVPMOV256, [Zn3FPVShuf01], 4, [3], 2, /*LoadUOps=*/-1>; // 256-bit width packed vector width-changing move.
+defm : Zn3WriteResYMMPair<WriteVarShuffle256, [Zn3FPVShift01], 1, [1], 2>; // 256-bit width vector variable shuffles.
+defm : Zn3WriteResXMMPair<WriteVarVecShift, [Zn3FPVShift01], 1, [1], 1>; // Variable vector shifts.
+defm : Zn3WriteResYMMPair<WriteVarVecShiftY, [Zn3FPVShift01], 1, [1], 1>; // Variable vector shifts (YMM).
+defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>; // Variable vector shifts (ZMM).
+
+// Old microcoded instructions that nobody use.
+defm : Zn3WriteResInt<WriteMicrocoded, [Zn3ALU0123], 100, [100], 100>;
+
+// Fence instructions.
+defm : Zn3WriteResInt<WriteFence, [Zn3ALU0123], 1, [100], 1>;
+
+def Zn3WriteLFENCE : SchedWriteRes<[Zn3LSU]> {
+ let Latency = 1;
+ let ResourceCycles = [30];
+ let NumMicroOps = 1;
+}
+def : InstRW<[Zn3WriteLFENCE], (instrs LFENCE)>;
+
+def Zn3WriteSFENCE : SchedWriteRes<[Zn3LSU]> {
+ let Latency = 1;
+ let ResourceCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[Zn3WriteSFENCE], (instrs SFENCE)>;
+
+// Nop, not very useful expect it provides a model for nops!
+defm : Zn3WriteResInt<WriteNop, [Zn3ALU0123], 0, [1], 1>; // FIXME: latency not from llvm-exegesis
+
+} // SchedModel
diff --git a/llvm/test/CodeGen/X86/slow-unaligned-mem.ll b/llvm/test/CodeGen/X86/slow-unaligned-mem.ll
index f2c7c2fa4a564..60099ab6566a0 100644
--- a/llvm/test/CodeGen/X86/slow-unaligned-mem.ll
+++ b/llvm/test/CodeGen/X86/slow-unaligned-mem.ll
@@ -48,6 +48,7 @@
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver4 2>&1 | FileCheck %s --check-prefix=FAST
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver1 2>&1 | FileCheck %s --check-prefix=FAST
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver2 2>&1 | FileCheck %s --check-prefix=FAST
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver3 2>&1 | FileCheck %s --check-prefix=FAST
; Other chips with slow unaligned memory accesses
diff --git a/llvm/test/CodeGen/X86/x86-64-double-shifts-var.ll b/llvm/test/CodeGen/X86/x86-64-double-shifts-var.ll
index 513e7774f6a79..f8a50937fb4ef 100644
--- a/llvm/test/CodeGen/X86/x86-64-double-shifts-var.ll
+++ b/llvm/test/CodeGen/X86/x86-64-double-shifts-var.ll
@@ -14,6 +14,7 @@
; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver4 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver1 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver2 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3 | FileCheck %s
; Verify that for the X86_64 processors that are known to have poor latency
; double precision shift instructions we do not generate 'shld' or 'shrd'
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update-2.s b/llvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update-2.s
new file mode 100644
index 0000000000000..150fa7cbd875e
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update-2.s
@@ -0,0 +1,48 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -iterations=1 -resource-pressure=false -timeline < %s | FileCheck %s
+
+imul %rax, %rbx
+lzcnt %ax, %bx
+add %ecx, %ebx
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 3
+# CHECK-NEXT: Total Cycles: 8
+# CHECK-NEXT: Total uOps: 3
+
+# CHECK: Dispatch Width: 6
+# CHECK-NEXT: uOps Per Cycle: 0.38
+# CHECK-NEXT: IPC: 0.38
+# CHECK-NEXT: Block RThroughput: 1.3
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 1.00 imulq %rax, %rbx
+# CHECK-NEXT: 1 1 1.00 lzcntw %ax, %bx
+# CHECK-NEXT: 1 1 0.25 addl %ecx, %ebx
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 01234567
+
+# CHECK: [0,0] DeeeER . imulq %rax, %rbx
+# CHECK-NEXT: [0,1] D===eER. lzcntw %ax, %bx
+# CHECK-NEXT: [0,2] D====eER addl %ecx, %ebx
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 imulq %rax, %rbx
+# CHECK-NEXT: 1. 1 4.0 0.0 0.0 lzcntw %ax, %bx
+# CHECK-NEXT: 2. 1 5.0 0.0 0.0 addl %ecx, %ebx
+# CHECK-NEXT: 1 3.3 0.3 0.0 <total>
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update-3.s b/llvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update-3.s
new file mode 100644
index 0000000000000..7ac674c5a6b59
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update-3.s
@@ -0,0 +1,102 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -iterations=1500 -timeline -timeline-max-iterations=6 < %s | FileCheck %s
+
+# The ILP is limited by the false dependency on %dx. So, the mov cannot execute
+# in parallel with the add.
+
+add %cx, %dx
+mov %ax, %dx
+xor %bx, %dx
+
+# CHECK: Iterations: 1500
+# CHECK-NEXT: Instructions: 4500
+# CHECK-NEXT: Total Cycles: 4503
+# CHECK-NEXT: Total uOps: 4500
+
+# CHECK: Dispatch Width: 6
+# CHECK-NEXT: uOps Per Cycle: 1.00
+# CHECK-NEXT: IPC: 1.00
+# CHECK-NEXT: Block RThroughput: 1.5
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.25 addw %cx, %dx
+# CHECK-NEXT: 1 1 1.00 movw %ax, %dx
+# CHECK-NEXT: 1 1 0.25 xorw %bx, %dx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: - - - 1.50 1.50 1.50 1.50 - - - - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - addw %cx, %dx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - movw %ax, %dx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - xorw %bx, %dx
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 0
+
+# CHECK: [0,0] DeER . . . . addw %cx, %dx
+# CHECK-NEXT: [0,1] D=eER. . . . movw %ax, %dx
+# CHECK-NEXT: [0,2] D==eER . . . xorw %bx, %dx
+# CHECK-NEXT: [1,0] D===eER . . . addw %cx, %dx
+# CHECK-NEXT: [1,1] D====eER . . . movw %ax, %dx
+# CHECK-NEXT: [1,2] D=====eER . . . xorw %bx, %dx
+# CHECK-NEXT: [2,0] .D=====eER. . . addw %cx, %dx
+# CHECK-NEXT: [2,1] .D======eER . . movw %ax, %dx
+# CHECK-NEXT: [2,2] .D=======eER . . xorw %bx, %dx
+# CHECK-NEXT: [3,0] .D========eER . . addw %cx, %dx
+# CHECK-NEXT: [3,1] .D=========eER . . movw %ax, %dx
+# CHECK-NEXT: [3,2] .D==========eER. . xorw %bx, %dx
+# CHECK-NEXT: [4,0] . D==========eER . addw %cx, %dx
+# CHECK-NEXT: [4,1] . D===========eER . movw %ax, %dx
+# CHECK-NEXT: [4,2] . D============eER . xorw %bx, %dx
+# CHECK-NEXT: [5,0] . D=============eER . addw %cx, %dx
+# CHECK-NEXT: [5,1] . D==============eER. movw %ax, %dx
+# CHECK-NEXT: [5,2] . D===============eER xorw %bx, %dx
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 6 7.5 0.2 0.0 addw %cx, %dx
+# CHECK-NEXT: 1. 6 8.5 0.0 0.0 movw %ax, %dx
+# CHECK-NEXT: 2. 6 9.5 0.0 0.0 xorw %bx, %dx
+# CHECK-NEXT: 6 8.5 0.1 0.0 <total>
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update-4.s b/llvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update-4.s
new file mode 100644
index 0000000000000..582da14211d0d
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update-4.s
@@ -0,0 +1,105 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -iterations=1500 -timeline -timeline-max-iterations=7 < %s | FileCheck %s
+
+# The lzcnt cannot execute in parallel with the imul because there is a false
+# dependency on %bx.
+
+imul %ax, %bx
+lzcnt %ax, %bx
+add %cx, %bx
+
+# CHECK: Iterations: 1500
+# CHECK-NEXT: Instructions: 4500
+# CHECK-NEXT: Total Cycles: 7503
+# CHECK-NEXT: Total uOps: 4500
+
+# CHECK: Dispatch Width: 6
+# CHECK-NEXT: uOps Per Cycle: 0.60
+# CHECK-NEXT: IPC: 0.60
+# CHECK-NEXT: Block RThroughput: 1.3
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 1.00 imulw %ax, %bx
+# CHECK-NEXT: 1 1 1.00 lzcntw %ax, %bx
+# CHECK-NEXT: 1 1 0.25 addw %cx, %bx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: - - - 1.67 1.00 1.67 1.67 - - - - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - - - - imulw %ax, %bx
+# CHECK-NEXT: - - - 1.33 - 1.33 1.33 - - - - - - - - - - - - - - - - lzcntw %ax, %bx
+# CHECK-NEXT: - - - 0.33 - 0.33 0.33 - - - - - - - - - - - - - - - - addw %cx, %bx
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789 01234567
+# CHECK-NEXT: Index 0123456789 0123456789
+
+# CHECK: [0,0] DeeeER . . . . . . . imulw %ax, %bx
+# CHECK-NEXT: [0,1] D===eER . . . . . . . lzcntw %ax, %bx
+# CHECK-NEXT: [0,2] D====eER . . . . . . . addw %cx, %bx
+# CHECK-NEXT: [1,0] D=====eeeER . . . . . . imulw %ax, %bx
+# CHECK-NEXT: [1,1] D========eER . . . . . . lzcntw %ax, %bx
+# CHECK-NEXT: [1,2] D=========eER . . . . . . addw %cx, %bx
+# CHECK-NEXT: [2,0] .D=========eeeER . . . . . imulw %ax, %bx
+# CHECK-NEXT: [2,1] .D============eER . . . . . lzcntw %ax, %bx
+# CHECK-NEXT: [2,2] .D=============eER . . . . . addw %cx, %bx
+# CHECK-NEXT: [3,0] .D==============eeeER . . . . imulw %ax, %bx
+# CHECK-NEXT: [3,1] .D=================eER . . . . lzcntw %ax, %bx
+# CHECK-NEXT: [3,2] .D==================eER . . . . addw %cx, %bx
+# CHECK-NEXT: [4,0] . D==================eeeER . . . imulw %ax, %bx
+# CHECK-NEXT: [4,1] . D=====================eER . . . lzcntw %ax, %bx
+# CHECK-NEXT: [4,2] . D======================eER . . . addw %cx, %bx
+# CHECK-NEXT: [5,0] . D=======================eeeER . . imulw %ax, %bx
+# CHECK-NEXT: [5,1] . D==========================eER . . lzcntw %ax, %bx
+# CHECK-NEXT: [5,2] . D===========================eER . . addw %cx, %bx
+# CHECK-NEXT: [6,0] . D===========================eeeER . imulw %ax, %bx
+# CHECK-NEXT: [6,1] . D==============================eER. lzcntw %ax, %bx
+# CHECK-NEXT: [6,2] . D===============================eER addw %cx, %bx
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 7 14.7 0.1 0.0 imulw %ax, %bx
+# CHECK-NEXT: 1. 7 17.7 0.0 0.0 lzcntw %ax, %bx
+# CHECK-NEXT: 2. 7 18.7 0.0 0.0 addw %cx, %bx
+# CHECK-NEXT: 7 17.0 0.0 0.0 <total>
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update-5.s b/llvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update-5.s
new file mode 100644
index 0000000000000..dda87e9ebc922
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update-5.s
@@ -0,0 +1,80 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -iterations=1500 -timeline -timeline-max-iterations=8 < %s | FileCheck %s
+
+lzcnt %ax, %bx ## partial register stall.
+
+# CHECK: Iterations: 1500
+# CHECK-NEXT: Instructions: 1500
+# CHECK-NEXT: Total Cycles: 1503
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 6
+# CHECK-NEXT: uOps Per Cycle: 1.00
+# CHECK-NEXT: IPC: 1.00
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 lzcntw %ax, %bx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - lzcntw %ax, %bx
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeER . . lzcntw %ax, %bx
+# CHECK-NEXT: [1,0] D=eER. . lzcntw %ax, %bx
+# CHECK-NEXT: [2,0] D==eER . lzcntw %ax, %bx
+# CHECK-NEXT: [3,0] D===eER . lzcntw %ax, %bx
+# CHECK-NEXT: [4,0] D====eER . lzcntw %ax, %bx
+# CHECK-NEXT: [5,0] D=====eER . lzcntw %ax, %bx
+# CHECK-NEXT: [6,0] .D=====eER. lzcntw %ax, %bx
+# CHECK-NEXT: [7,0] .D======eER lzcntw %ax, %bx
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 8 4.3 0.1 0.0 lzcntw %ax, %bx
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update-6.s b/llvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update-6.s
new file mode 100644
index 0000000000000..71520ea1ce4b5
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update-6.s
@@ -0,0 +1,98 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -iterations=1500 -timeline -timeline-max-iterations=4 < %s | FileCheck %s
+
+# Each lzcnt has a false dependency on %ecx; the first lzcnt has to wait on the
+# imul. However, the folded load can start immediately.
+# The last lzcnt has a false dependency on %cx. However, even in this case, the
+# folded load can start immediately.
+
+imul %edx, %ecx
+lzcnt (%rsp), %cx
+lzcnt 2(%rsp), %cx
+
+# CHECK: Iterations: 1500
+# CHECK-NEXT: Instructions: 4500
+# CHECK-NEXT: Total Cycles: 9003
+# CHECK-NEXT: Total uOps: 4500
+
+# CHECK: Dispatch Width: 6
+# CHECK-NEXT: uOps Per Cycle: 0.50
+# CHECK-NEXT: IPC: 0.50
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 1.00 imull %edx, %ecx
+# CHECK-NEXT: 1 5 0.33 * lzcntw (%rsp), %cx
+# CHECK-NEXT: 1 5 0.33 * lzcntw 2(%rsp), %cx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: 0.67 0.67 0.67 0.67 1.00 0.67 0.67 - - - - - - - - 0.67 0.67 0.67 0.67 0.67 0.67 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - - - - imull %edx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - lzcntw (%rsp), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - lzcntw 2(%rsp), %cx
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 0123456
+
+# CHECK: [0,0] DeeeER . . . .. imull %edx, %ecx
+# CHECK-NEXT: [0,1] DeeeeeER . . . .. lzcntw (%rsp), %cx
+# CHECK-NEXT: [0,2] D=eeeeeER . . . .. lzcntw 2(%rsp), %cx
+# CHECK-NEXT: [1,0] D======eeeER . . .. imull %edx, %ecx
+# CHECK-NEXT: [1,1] D======eeeeeER . . .. lzcntw (%rsp), %cx
+# CHECK-NEXT: [1,2] D=======eeeeeER. . .. lzcntw 2(%rsp), %cx
+# CHECK-NEXT: [2,0] .D===========eeeER . .. imull %edx, %ecx
+# CHECK-NEXT: [2,1] .D===========eeeeeER. .. lzcntw (%rsp), %cx
+# CHECK-NEXT: [2,2] .D============eeeeeER .. lzcntw 2(%rsp), %cx
+# CHECK-NEXT: [3,0] .D=================eeeER .. imull %edx, %ecx
+# CHECK-NEXT: [3,1] .D=================eeeeeER. lzcntw (%rsp), %cx
+# CHECK-NEXT: [3,2] .D==================eeeeeER lzcntw 2(%rsp), %cx
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 4 9.5 0.3 0.0 imull %edx, %ecx
+# CHECK-NEXT: 1. 4 9.5 0.0 0.0 lzcntw (%rsp), %cx
+# CHECK-NEXT: 2. 4 10.5 0.0 0.0 lzcntw 2(%rsp), %cx
+# CHECK-NEXT: 4 9.8 0.1 0.0 <total>
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update-7.s b/llvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update-7.s
new file mode 100644
index 0000000000000..d782e5dd59783
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update-7.s
@@ -0,0 +1,52 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -iterations=1 -resource-pressure=false -timeline < %s | FileCheck %s
+
+# An instruction that writes to a 32-bit register will not have any false
+# dependence on the corresponding 64-bit register because the upper part of
+# the 64-bit register is set to zero
+
+imulq %rax, %rcx
+addl %edx, %ecx
+addq %rcx, %rdx
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 3
+# CHECK-NEXT: Total Cycles: 8
+# CHECK-NEXT: Total uOps: 3
+
+# CHECK: Dispatch Width: 6
+# CHECK-NEXT: uOps Per Cycle: 0.38
+# CHECK-NEXT: IPC: 0.38
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 1.00 imulq %rax, %rcx
+# CHECK-NEXT: 1 1 0.25 addl %edx, %ecx
+# CHECK-NEXT: 1 1 0.25 addq %rcx, %rdx
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 01234567
+
+# CHECK: [0,0] DeeeER . imulq %rax, %rcx
+# CHECK-NEXT: [0,1] D===eER. addl %edx, %ecx
+# CHECK-NEXT: [0,2] D====eER addq %rcx, %rdx
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 imulq %rax, %rcx
+# CHECK-NEXT: 1. 1 4.0 0.0 0.0 addl %edx, %ecx
+# CHECK-NEXT: 2. 1 5.0 0.0 0.0 addq %rcx, %rdx
+# CHECK-NEXT: 1 3.3 0.3 0.0 <total>
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update.s b/llvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update.s
new file mode 100644
index 0000000000000..2dd1b4b337eee
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update.s
@@ -0,0 +1,48 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -iterations=1 -resource-pressure=false -timeline < %s | FileCheck %s
+
+imul %ax, %cx
+add %al, %cl
+add %ecx, %ebx
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 3
+# CHECK-NEXT: Total Cycles: 8
+# CHECK-NEXT: Total uOps: 3
+
+# CHECK: Dispatch Width: 6
+# CHECK-NEXT: uOps Per Cycle: 0.38
+# CHECK-NEXT: IPC: 0.38
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 1.00 imulw %ax, %cx
+# CHECK-NEXT: 1 1 0.25 addb %al, %cl
+# CHECK-NEXT: 1 1 0.25 addl %ecx, %ebx
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 01234567
+
+# CHECK: [0,0] DeeeER . imulw %ax, %cx
+# CHECK-NEXT: [0,1] D===eER. addb %al, %cl
+# CHECK-NEXT: [0,2] D====eER addl %ecx, %ebx
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 imulw %ax, %cx
+# CHECK-NEXT: 1. 1 4.0 0.0 0.0 addb %al, %cl
+# CHECK-NEXT: 2. 1 5.0 0.0 0.0 addl %ecx, %ebx
+# CHECK-NEXT: 1 3.3 0.3 0.0 <total>
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-adx.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-adx.s
new file mode 100644
index 0000000000000..4e024e5846f18
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-adx.s
@@ -0,0 +1,70 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+adcx %ebx, %ecx
+adcx (%rbx), %ecx
+adcx %rbx, %rcx
+adcx (%rbx), %rcx
+
+adox %ebx, %ecx
+adox (%rbx), %ecx
+adox %rbx, %rcx
+adox (%rbx), %rcx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 adcxl %ebx, %ecx
+# CHECK-NEXT: 1 5 1.00 * adcxl (%rbx), %ecx
+# CHECK-NEXT: 1 1 1.00 adcxq %rbx, %rcx
+# CHECK-NEXT: 1 5 1.00 * adcxq (%rbx), %rcx
+# CHECK-NEXT: 1 1 1.00 adoxl %ebx, %ecx
+# CHECK-NEXT: 1 5 1.00 * adoxl (%rbx), %ecx
+# CHECK-NEXT: 1 1 1.00 adoxq %rbx, %rcx
+# CHECK-NEXT: 1 5 1.00 * adoxq (%rbx), %rcx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: 1.33 1.33 1.33 8.00 8.00 8.00 8.00 - - - - - - - - 1.33 1.33 1.33 1.33 1.33 1.33 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - adcxl %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 1.00 1.00 1.00 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - adcxl (%rbx), %ecx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - adcxq %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 1.00 1.00 1.00 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - adcxq (%rbx), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - adoxl %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 1.00 1.00 1.00 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - adoxl (%rbx), %ecx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - adoxq %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 1.00 1.00 1.00 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - adoxq (%rbx), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-aes.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-aes.s
new file mode 100644
index 0000000000000..5abf3cca9211c
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-aes.s
@@ -0,0 +1,86 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+aesdec %xmm0, %xmm2
+aesdec (%rax), %xmm2
+
+aesdeclast %xmm0, %xmm2
+aesdeclast (%rax), %xmm2
+
+aesenc %xmm0, %xmm2
+aesenc (%rax), %xmm2
+
+aesenclast %xmm0, %xmm2
+aesenclast (%rax), %xmm2
+
+aesimc %xmm0, %xmm2
+aesimc (%rax), %xmm2
+
+aeskeygenassist $22, %xmm0, %xmm2
+aeskeygenassist $22, (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 4 0.50 aesdec %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * aesdec (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 aesdeclast %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * aesdeclast (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 aesenc %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * aesenc (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 aesenclast %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * aesenclast (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 aesimc %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * aesimc (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 aeskeygenassist $22, %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * aeskeygenassist $22, (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: - - - - - - - - 6.00 6.00 - - 3.00 3.00 - 2.00 2.00 2.00 2.00 2.00 2.00 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - aesdec %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - aesdec (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - aesdeclast %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - aesdeclast (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - aesenc %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - aesenc (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - aesenclast %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - aesenclast (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - aesimc %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - aesimc (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - aeskeygenassist $22, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - aeskeygenassist $22, (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-avx1.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-avx1.s
new file mode 100644
index 0000000000000..9893fb0d0fe92
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-avx1.s
@@ -0,0 +1,2446 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+vaddpd %xmm0, %xmm1, %xmm2
+vaddpd (%rax), %xmm1, %xmm2
+
+vaddpd %ymm0, %ymm1, %ymm2
+vaddpd (%rax), %ymm1, %ymm2
+
+vaddps %xmm0, %xmm1, %xmm2
+vaddps (%rax), %xmm1, %xmm2
+
+vaddps %ymm0, %ymm1, %ymm2
+vaddps (%rax), %ymm1, %ymm2
+
+vaddsd %xmm0, %xmm1, %xmm2
+vaddsd (%rax), %xmm1, %xmm2
+
+vaddss %xmm0, %xmm1, %xmm2
+vaddss (%rax), %xmm1, %xmm2
+
+vaddsubpd %xmm0, %xmm1, %xmm2
+vaddsubpd (%rax), %xmm1, %xmm2
+
+vaddsubpd %ymm0, %ymm1, %ymm2
+vaddsubpd (%rax), %ymm1, %ymm2
+
+vaddsubps %xmm0, %xmm1, %xmm2
+vaddsubps (%rax), %xmm1, %xmm2
+
+vaddsubps %ymm0, %ymm1, %ymm2
+vaddsubps (%rax), %ymm1, %ymm2
+
+vaesdec %xmm0, %xmm1, %xmm2
+vaesdec (%rax), %xmm1, %xmm2
+
+vaesdeclast %xmm0, %xmm1, %xmm2
+vaesdeclast (%rax), %xmm1, %xmm2
+
+vaesenc %xmm0, %xmm1, %xmm2
+vaesenc (%rax), %xmm1, %xmm2
+
+vaesenclast %xmm0, %xmm1, %xmm2
+vaesenclast (%rax), %xmm1, %xmm2
+
+vaesimc %xmm0, %xmm2
+vaesimc (%rax), %xmm2
+
+vaeskeygenassist $22, %xmm0, %xmm2
+vaeskeygenassist $22, (%rax), %xmm2
+
+vandnpd %xmm0, %xmm1, %xmm2
+vandnpd (%rax), %xmm1, %xmm2
+
+vandnpd %ymm0, %ymm1, %ymm2
+vandnpd (%rax), %ymm1, %ymm2
+
+vandnps %xmm0, %xmm1, %xmm2
+vandnps (%rax), %xmm1, %xmm2
+
+vandnps %ymm0, %ymm1, %ymm2
+vandnps (%rax), %ymm1, %ymm2
+
+vandpd %xmm0, %xmm1, %xmm2
+vandpd (%rax), %xmm1, %xmm2
+
+vandpd %ymm0, %ymm1, %ymm2
+vandpd (%rax), %ymm1, %ymm2
+
+vandps %xmm0, %xmm1, %xmm2
+vandps (%rax), %xmm1, %xmm2
+
+vandps %ymm0, %ymm1, %ymm2
+vandps (%rax), %ymm1, %ymm2
+
+vblendpd $11, %xmm0, %xmm1, %xmm2
+vblendpd $11, (%rax), %xmm1, %xmm2
+
+vblendpd $11, %ymm0, %ymm1, %ymm2
+vblendpd $11, (%rax), %ymm1, %ymm2
+
+vblendps $11, %xmm0, %xmm1, %xmm2
+vblendps $11, (%rax), %xmm1, %xmm2
+
+vblendps $11, %ymm0, %ymm1, %ymm2
+vblendps $11, (%rax), %ymm1, %ymm2
+
+vblendvpd %xmm3, %xmm0, %xmm1, %xmm2
+vblendvpd %xmm3, (%rax), %xmm1, %xmm2
+
+vblendvpd %ymm3, %ymm0, %ymm1, %ymm2
+vblendvpd %ymm3, (%rax), %ymm1, %ymm2
+
+vblendvps %xmm3, %xmm0, %xmm1, %xmm2
+vblendvps %xmm3, (%rax), %xmm1, %xmm2
+
+vblendvps %ymm3, %ymm0, %ymm1, %ymm2
+vblendvps %ymm3, (%rax), %ymm1, %ymm2
+
+vbroadcastf128 (%rax), %ymm2
+
+vbroadcastsd (%rax), %ymm2
+
+vbroadcastss (%rax), %xmm2
+vbroadcastss (%rax), %ymm2
+
+vcmppd $0, %xmm0, %xmm1, %xmm2
+vcmppd $0, (%rax), %xmm1, %xmm2
+
+vcmppd $0, %ymm0, %ymm1, %ymm2
+vcmppd $0, (%rax), %ymm1, %ymm2
+
+vcmpps $0, %xmm0, %xmm1, %xmm2
+vcmpps $0, (%rax), %xmm1, %xmm2
+
+vcmpps $0, %ymm0, %ymm1, %ymm2
+vcmpps $0, (%rax), %ymm1, %ymm2
+
+vcmpsd $0, %xmm0, %xmm1, %xmm2
+vcmpsd $0, (%rax), %xmm1, %xmm2
+
+vcmpss $0, %xmm0, %xmm1, %xmm2
+vcmpss $0, (%rax), %xmm1, %xmm2
+
+vcomisd %xmm0, %xmm1
+vcomisd (%rax), %xmm1
+
+vcomiss %xmm0, %xmm1
+vcomiss (%rax), %xmm1
+
+vcvtdq2pd %xmm0, %xmm2
+vcvtdq2pd (%rax), %xmm2
+
+vcvtdq2pd %xmm0, %ymm2
+vcvtdq2pd (%rax), %ymm2
+
+vcvtdq2ps %xmm0, %xmm2
+vcvtdq2ps (%rax), %xmm2
+
+vcvtdq2ps %ymm0, %ymm2
+vcvtdq2ps (%rax), %ymm2
+
+vcvtpd2dqx %xmm0, %xmm2
+vcvtpd2dqx (%rax), %xmm2
+
+vcvtpd2dqy %ymm0, %xmm2
+vcvtpd2dqy (%rax), %xmm2
+
+vcvtpd2psx %xmm0, %xmm2
+vcvtpd2psx (%rax), %xmm2
+
+vcvtpd2psy %ymm0, %xmm2
+vcvtpd2psy (%rax), %xmm2
+
+vcvtps2dq %xmm0, %xmm2
+vcvtps2dq (%rax), %xmm2
+
+vcvtps2dq %ymm0, %ymm2
+vcvtps2dq (%rax), %ymm2
+
+vcvtps2pd %xmm0, %xmm2
+vcvtps2pd (%rax), %xmm2
+
+vcvtps2pd %xmm0, %ymm2
+vcvtps2pd (%rax), %ymm2
+
+vcvtsd2si %xmm0, %ecx
+vcvtsd2si %xmm0, %rcx
+vcvtsd2si (%rax), %ecx
+vcvtsd2si (%rax), %rcx
+
+vcvtsd2ss %xmm0, %xmm1, %xmm2
+vcvtsd2ss (%rax), %xmm1, %xmm2
+
+vcvtsi2sdl %ecx, %xmm0, %xmm2
+vcvtsi2sdq %rcx, %xmm0, %xmm2
+vcvtsi2sdl (%rax), %xmm0, %xmm2
+vcvtsi2sdq (%rax), %xmm0, %xmm2
+
+vcvtsi2ssl %ecx, %xmm0, %xmm2
+vcvtsi2ssq %rcx, %xmm0, %xmm2
+vcvtsi2ssl (%rax), %xmm0, %xmm2
+vcvtsi2ssq (%rax), %xmm0, %xmm2
+
+vcvtss2sd %xmm0, %xmm1, %xmm2
+vcvtss2sd (%rax), %xmm1, %xmm2
+
+vcvtss2si %xmm0, %ecx
+vcvtss2si %xmm0, %rcx
+vcvtss2si (%rax), %ecx
+vcvtss2si (%rax), %rcx
+
+vcvttpd2dqx %xmm0, %xmm2
+vcvttpd2dqx (%rax), %xmm2
+
+vcvttpd2dqy %ymm0, %xmm2
+vcvttpd2dqy (%rax), %xmm2
+
+vcvttps2dq %xmm0, %xmm2
+vcvttps2dq (%rax), %xmm2
+
+vcvttps2dq %ymm0, %ymm2
+vcvttps2dq (%rax), %ymm2
+
+vcvttsd2si %xmm0, %ecx
+vcvttsd2si %xmm0, %rcx
+vcvttsd2si (%rax), %ecx
+vcvttsd2si (%rax), %rcx
+
+vcvttss2si %xmm0, %ecx
+vcvttss2si %xmm0, %rcx
+vcvttss2si (%rax), %ecx
+vcvttss2si (%rax), %rcx
+
+vdivpd %xmm0, %xmm1, %xmm2
+vdivpd (%rax), %xmm1, %xmm2
+
+vdivpd %ymm0, %ymm1, %ymm2
+vdivpd (%rax), %ymm1, %ymm2
+
+vdivps %xmm0, %xmm1, %xmm2
+vdivps (%rax), %xmm1, %xmm2
+
+vdivps %ymm0, %ymm1, %ymm2
+vdivps (%rax), %ymm1, %ymm2
+
+vdivsd %xmm0, %xmm1, %xmm2
+vdivsd (%rax), %xmm1, %xmm2
+
+vdivss %xmm0, %xmm1, %xmm2
+vdivss (%rax), %xmm1, %xmm2
+
+vdppd $22, %xmm0, %xmm1, %xmm2
+vdppd $22, (%rax), %xmm1, %xmm2
+
+vdpps $22, %xmm0, %xmm1, %xmm2
+vdpps $22, (%rax), %xmm1, %xmm2
+
+vdpps $22, %ymm0, %ymm1, %ymm2
+vdpps $22, (%rax), %ymm1, %ymm2
+
+vextractf128 $1, %ymm0, %xmm2
+vextractf128 $1, %ymm0, (%rax)
+
+vextractps $1, %xmm0, %rcx
+vextractps $1, %xmm0, (%rax)
+
+vhaddpd %xmm0, %xmm1, %xmm2
+vhaddpd (%rax), %xmm1, %xmm2
+
+vhaddpd %ymm0, %ymm1, %ymm2
+vhaddpd (%rax), %ymm1, %ymm2
+
+vhaddps %xmm0, %xmm1, %xmm2
+vhaddps (%rax), %xmm1, %xmm2
+
+vhaddps %ymm0, %ymm1, %ymm2
+vhaddps (%rax), %ymm1, %ymm2
+
+vhsubpd %xmm0, %xmm1, %xmm2
+vhsubpd (%rax), %xmm1, %xmm2
+
+vhsubpd %ymm0, %ymm1, %ymm2
+vhsubpd (%rax), %ymm1, %ymm2
+
+vhsubps %xmm0, %xmm1, %xmm2
+vhsubps (%rax), %xmm1, %xmm2
+
+vhsubps %ymm0, %ymm1, %ymm2
+vhsubps (%rax), %ymm1, %ymm2
+
+vinsertf128 $1, %xmm0, %ymm1, %ymm2
+vinsertf128 $1, (%rax), %ymm1, %ymm2
+
+vinsertps $1, %xmm0, %xmm1, %xmm2
+vinsertps $1, (%rax), %xmm1, %xmm2
+
+vlddqu (%rax), %xmm2
+vlddqu (%rax), %ymm2
+
+vldmxcsr (%rax)
+
+vmaskmovdqu %xmm0, %xmm1
+
+vmaskmovpd (%rax), %xmm0, %xmm2
+vmaskmovpd (%rax), %ymm0, %ymm2
+
+vmaskmovpd %xmm0, %xmm1, (%rax)
+vmaskmovpd %ymm0, %ymm1, (%rax)
+
+vmaskmovps (%rax), %xmm0, %xmm2
+vmaskmovps (%rax), %ymm0, %ymm2
+
+vmaskmovps %xmm0, %xmm1, (%rax)
+vmaskmovps %ymm0, %ymm1, (%rax)
+
+vmaxpd %xmm0, %xmm1, %xmm2
+vmaxpd (%rax), %xmm1, %xmm2
+
+vmaxpd %ymm0, %ymm1, %ymm2
+vmaxpd (%rax), %ymm1, %ymm2
+
+vmaxps %xmm0, %xmm1, %xmm2
+vmaxps (%rax), %xmm1, %xmm2
+
+vmaxps %ymm0, %ymm1, %ymm2
+vmaxps (%rax), %ymm1, %ymm2
+
+vmaxsd %xmm0, %xmm1, %xmm2
+vmaxsd (%rax), %xmm1, %xmm2
+
+vmaxss %xmm0, %xmm1, %xmm2
+vmaxss (%rax), %xmm1, %xmm2
+
+vminpd %xmm0, %xmm1, %xmm2
+vminpd (%rax), %xmm1, %xmm2
+
+vminpd %ymm0, %ymm1, %ymm2
+vminpd (%rax), %ymm1, %ymm2
+
+vminps %xmm0, %xmm1, %xmm2
+vminps (%rax), %xmm1, %xmm2
+
+vminps %ymm0, %ymm1, %ymm2
+vminps (%rax), %ymm1, %ymm2
+
+vminsd %xmm0, %xmm1, %xmm2
+vminsd (%rax), %xmm1, %xmm2
+
+vminss %xmm0, %xmm1, %xmm2
+vminss (%rax), %xmm1, %xmm2
+
+vmovapd %xmm0, %xmm2
+vmovapd %xmm0, (%rax)
+vmovapd (%rax), %xmm2
+
+vmovapd %ymm0, %ymm2
+vmovapd %ymm0, (%rax)
+vmovapd (%rax), %ymm2
+
+vmovaps %xmm0, %xmm2
+vmovaps %xmm0, (%rax)
+vmovaps (%rax), %xmm2
+
+vmovaps %ymm0, %ymm2
+vmovaps %ymm0, (%rax)
+vmovaps (%rax), %ymm2
+
+vmovd %eax, %xmm2
+vmovd (%rax), %xmm2
+
+vmovd %xmm0, %ecx
+vmovd %xmm0, (%rax)
+
+vmovddup %xmm0, %xmm2
+vmovddup (%rax), %xmm2
+
+vmovddup %ymm0, %ymm2
+vmovddup (%rax), %ymm2
+
+vmovdqa %xmm0, %xmm2
+vmovdqa %xmm0, (%rax)
+vmovdqa (%rax), %xmm2
+
+vmovdqa %ymm0, %ymm2
+vmovdqa %ymm0, (%rax)
+vmovdqa (%rax), %ymm2
+
+vmovdqu %xmm0, %xmm2
+vmovdqu %xmm0, (%rax)
+vmovdqu (%rax), %xmm2
+
+vmovdqu %ymm0, %ymm2
+vmovdqu %ymm0, (%rax)
+vmovdqu (%rax), %ymm2
+
+vmovhlps %xmm0, %xmm1, %xmm2
+vmovlhps %xmm0, %xmm1, %xmm2
+
+vmovhpd %xmm0, (%rax)
+vmovhpd (%rax), %xmm1, %xmm2
+
+vmovhps %xmm0, (%rax)
+vmovhps (%rax), %xmm1, %xmm2
+
+vmovlpd %xmm0, (%rax)
+vmovlpd (%rax), %xmm1, %xmm2
+
+vmovlps %xmm0, (%rax)
+vmovlps (%rax), %xmm1, %xmm2
+
+vmovmskpd %xmm0, %rcx
+vmovmskpd %ymm0, %rcx
+
+vmovmskps %xmm0, %rcx
+vmovmskps %ymm0, %rcx
+
+vmovntdq %xmm0, (%rax)
+vmovntdq %ymm0, (%rax)
+
+vmovntdqa (%rax), %xmm2
+vmovntdqa (%rax), %ymm2
+
+vmovntpd %xmm0, (%rax)
+vmovntpd %ymm0, (%rax)
+
+vmovntps %xmm0, (%rax)
+vmovntps %ymm0, (%rax)
+
+vmovq %xmm0, %xmm2
+
+vmovq %rax, %xmm2
+vmovq (%rax), %xmm2
+
+vmovq %xmm0, %rcx
+vmovq %xmm0, (%rax)
+
+vmovsd %xmm0, %xmm1, %xmm2
+vmovsd %xmm0, (%rax)
+vmovsd (%rax), %xmm2
+
+vmovshdup %xmm0, %xmm2
+vmovshdup (%rax), %xmm2
+
+vmovshdup %ymm0, %ymm2
+vmovshdup (%rax), %ymm2
+
+vmovsldup %xmm0, %xmm2
+vmovsldup (%rax), %xmm2
+
+vmovsldup %ymm0, %ymm2
+vmovsldup (%rax), %ymm2
+
+vmovss %xmm0, %xmm1, %xmm2
+vmovss %xmm0, (%rax)
+vmovss (%rax), %xmm2
+
+vmovupd %xmm0, %xmm2
+vmovupd %xmm0, (%rax)
+vmovupd (%rax), %xmm2
+
+vmovupd %ymm0, %ymm2
+vmovupd %ymm0, (%rax)
+vmovupd (%rax), %ymm2
+
+vmovups %xmm0, %xmm2
+vmovups %xmm0, (%rax)
+vmovups (%rax), %xmm2
+
+vmovups %ymm0, %ymm2
+vmovups %ymm0, (%rax)
+vmovups (%rax), %ymm2
+
+vmpsadbw $1, %xmm0, %xmm1, %xmm2
+vmpsadbw $1, (%rax), %xmm1, %xmm2
+
+vmulpd %xmm0, %xmm1, %xmm2
+vmulpd (%rax), %xmm1, %xmm2
+
+vmulpd %ymm0, %ymm1, %ymm2
+vmulpd (%rax), %ymm1, %ymm2
+
+vmulps %xmm0, %xmm1, %xmm2
+vmulps (%rax), %xmm1, %xmm2
+
+vmulps %ymm0, %ymm1, %ymm2
+vmulps (%rax), %ymm1, %ymm2
+
+vmulsd %xmm0, %xmm1, %xmm2
+vmulsd (%rax), %xmm1, %xmm2
+
+vmulss %xmm0, %xmm1, %xmm2
+vmulss (%rax), %xmm1, %xmm2
+
+vorpd %xmm0, %xmm1, %xmm2
+vorpd (%rax), %xmm1, %xmm2
+
+vorpd %ymm0, %ymm1, %ymm2
+vorpd (%rax), %ymm1, %ymm2
+
+vorps %xmm0, %xmm1, %xmm2
+vorps (%rax), %xmm1, %xmm2
+
+vorps %ymm0, %ymm1, %ymm2
+vorps (%rax), %ymm1, %ymm2
+
+vpabsb %xmm0, %xmm2
+vpabsb (%rax), %xmm2
+
+vpabsd %xmm0, %xmm2
+vpabsd (%rax), %xmm2
+
+vpabsw %xmm0, %xmm2
+vpabsw (%rax), %xmm2
+
+vpackssdw %xmm0, %xmm1, %xmm2
+vpackssdw (%rax), %xmm1, %xmm2
+
+vpacksswb %xmm0, %xmm1, %xmm2
+vpacksswb (%rax), %xmm1, %xmm2
+
+vpackusdw %xmm0, %xmm1, %xmm2
+vpackusdw (%rax), %xmm1, %xmm2
+
+vpackuswb %xmm0, %xmm1, %xmm2
+vpackuswb (%rax), %xmm1, %xmm2
+
+vpaddb %xmm0, %xmm1, %xmm2
+vpaddb (%rax), %xmm1, %xmm2
+
+vpaddd %xmm0, %xmm1, %xmm2
+vpaddd (%rax), %xmm1, %xmm2
+
+vpaddq %xmm0, %xmm1, %xmm2
+vpaddq (%rax), %xmm1, %xmm2
+
+vpaddsb %xmm0, %xmm1, %xmm2
+vpaddsb (%rax), %xmm1, %xmm2
+
+vpaddsw %xmm0, %xmm1, %xmm2
+vpaddsw (%rax), %xmm1, %xmm2
+
+vpaddusb %xmm0, %xmm1, %xmm2
+vpaddusb (%rax), %xmm1, %xmm2
+
+vpaddusw %xmm0, %xmm1, %xmm2
+vpaddusw (%rax), %xmm1, %xmm2
+
+vpaddw %xmm0, %xmm1, %xmm2
+vpaddw (%rax), %xmm1, %xmm2
+
+vpalignr $1, %xmm0, %xmm1, %xmm2
+vpalignr $1, (%rax), %xmm1, %xmm2
+
+vpand %xmm0, %xmm1, %xmm2
+vpand (%rax), %xmm1, %xmm2
+
+vpandn %xmm0, %xmm1, %xmm2
+vpandn (%rax), %xmm1, %xmm2
+
+vpavgb %xmm0, %xmm1, %xmm2
+vpavgb (%rax), %xmm1, %xmm2
+
+vpavgw %xmm0, %xmm1, %xmm2
+vpavgw (%rax), %xmm1, %xmm2
+
+vpblendvb %xmm3, %xmm0, %xmm1, %xmm2
+vpblendvb %xmm3, (%rax), %xmm1, %xmm2
+
+vpblendw $11, %xmm0, %xmm1, %xmm2
+vpblendw $11, (%rax), %xmm1, %xmm2
+
+vpclmulqdq $11, %xmm0, %xmm1, %xmm2
+vpclmulqdq $11, (%rax), %xmm1, %xmm2
+
+vpcmpeqb %xmm0, %xmm1, %xmm2
+vpcmpeqb (%rax), %xmm1, %xmm2
+
+vpcmpeqd %xmm0, %xmm1, %xmm2
+vpcmpeqd (%rax), %xmm1, %xmm2
+
+vpcmpeqq %xmm0, %xmm1, %xmm2
+vpcmpeqq (%rax), %xmm1, %xmm2
+
+vpcmpeqw %xmm0, %xmm1, %xmm2
+vpcmpeqw (%rax), %xmm1, %xmm2
+
+vpcmpestri $1, %xmm0, %xmm2
+vpcmpestri $1, (%rax), %xmm2
+
+vpcmpestrm $1, %xmm0, %xmm2
+vpcmpestrm $1, (%rax), %xmm2
+
+vpcmpgtb %xmm0, %xmm1, %xmm2
+vpcmpgtb (%rax), %xmm1, %xmm2
+
+vpcmpgtd %xmm0, %xmm1, %xmm2
+vpcmpgtd (%rax), %xmm1, %xmm2
+
+vpcmpgtq %xmm0, %xmm1, %xmm2
+vpcmpgtq (%rax), %xmm1, %xmm2
+
+vpcmpgtw %xmm0, %xmm1, %xmm2
+vpcmpgtw (%rax), %xmm1, %xmm2
+
+vpcmpistri $1, %xmm0, %xmm2
+vpcmpistri $1, (%rax), %xmm2
+
+vpcmpistrm $1, %xmm0, %xmm2
+vpcmpistrm $1, (%rax), %xmm2
+
+vperm2f128 $1, %ymm0, %ymm1, %ymm2
+vperm2f128 $1, (%rax), %ymm1, %ymm2
+
+vpermilpd $1, %xmm0, %xmm2
+vpermilpd $1, (%rax), %xmm2
+vpermilpd %xmm0, %xmm1, %xmm2
+vpermilpd (%rax), %xmm1, %xmm2
+
+vpermilpd $1, %ymm0, %ymm2
+vpermilpd $1, (%rax), %ymm2
+vpermilpd %ymm0, %ymm1, %ymm2
+vpermilpd (%rax), %ymm1, %ymm2
+
+vpermilps $1, %xmm0, %xmm2
+vpermilps $1, (%rax), %xmm2
+vpermilps %xmm0, %xmm1, %xmm2
+vpermilps (%rax), %xmm1, %xmm2
+
+vpermilps $1, %ymm0, %ymm2
+vpermilps $1, (%rax), %ymm2
+vpermilps %ymm0, %ymm1, %ymm2
+vpermilps (%rax), %ymm1, %ymm2
+
+vpextrb $1, %xmm0, %ecx
+vpextrb $1, %xmm0, (%rax)
+
+vpextrd $1, %xmm0, %ecx
+vpextrd $1, %xmm0, (%rax)
+
+vpextrq $1, %xmm0, %rcx
+vpextrq $1, %xmm0, (%rax)
+
+vpextrw $1, %xmm0, %ecx
+vpextrw $1, %xmm0, (%rax)
+
+vphaddd %xmm0, %xmm1, %xmm2
+vphaddd (%rax), %xmm1, %xmm2
+
+vphaddsw %xmm0, %xmm1, %xmm2
+vphaddsw (%rax), %xmm1, %xmm2
+
+vphaddw %xmm0, %xmm1, %xmm2
+vphaddw (%rax), %xmm1, %xmm2
+
+vphminposuw %xmm0, %xmm2
+vphminposuw (%rax), %xmm2
+
+vphsubd %xmm0, %xmm1, %xmm2
+vphsubd (%rax), %xmm1, %xmm2
+
+vphsubsw %xmm0, %xmm1, %xmm2
+vphsubsw (%rax), %xmm1, %xmm2
+
+vphsubw %xmm0, %xmm1, %xmm2
+vphsubw (%rax), %xmm1, %xmm2
+
+vpinsrb $1, %eax, %xmm1, %xmm2
+vpinsrb $1, (%rax), %xmm1, %xmm2
+
+vpinsrd $1, %eax, %xmm1, %xmm2
+vpinsrd $1, (%rax), %xmm1, %xmm2
+
+vpinsrq $1, %rax, %xmm1, %xmm2
+vpinsrq $1, (%rax), %xmm1, %xmm2
+
+vpinsrw $1, %eax, %xmm1, %xmm2
+vpinsrw $1, (%rax), %xmm1, %xmm2
+
+vpmaddubsw %xmm0, %xmm1, %xmm2
+vpmaddubsw (%rax), %xmm1, %xmm2
+
+vpmaddwd %xmm0, %xmm1, %xmm2
+vpmaddwd (%rax), %xmm1, %xmm2
+
+vpmaxsb %xmm0, %xmm1, %xmm2
+vpmaxsb (%rax), %xmm1, %xmm2
+
+vpmaxsd %xmm0, %xmm1, %xmm2
+vpmaxsd (%rax), %xmm1, %xmm2
+
+vpmaxsw %xmm0, %xmm1, %xmm2
+vpmaxsw (%rax), %xmm1, %xmm2
+
+vpmaxub %xmm0, %xmm1, %xmm2
+vpmaxub (%rax), %xmm1, %xmm2
+
+vpmaxud %xmm0, %xmm1, %xmm2
+vpmaxud (%rax), %xmm1, %xmm2
+
+vpmaxuw %xmm0, %xmm1, %xmm2
+vpmaxuw (%rax), %xmm1, %xmm2
+
+vpminsb %xmm0, %xmm1, %xmm2
+vpminsb (%rax), %xmm1, %xmm2
+
+vpminsd %xmm0, %xmm1, %xmm2
+vpminsd (%rax), %xmm1, %xmm2
+
+vpminsw %xmm0, %xmm1, %xmm2
+vpminsw (%rax), %xmm1, %xmm2
+
+vpminub %xmm0, %xmm1, %xmm2
+vpminub (%rax), %xmm1, %xmm2
+
+vpminud %xmm0, %xmm1, %xmm2
+vpminud (%rax), %xmm1, %xmm2
+
+vpminuw %xmm0, %xmm1, %xmm2
+vpminuw (%rax), %xmm1, %xmm2
+
+vpmovmskb %xmm0, %rcx
+
+vpmovsxbd %xmm0, %xmm2
+vpmovsxbd (%rax), %xmm2
+
+vpmovsxbq %xmm0, %xmm2
+vpmovsxbq (%rax), %xmm2
+
+vpmovsxbw %xmm0, %xmm2
+vpmovsxbw (%rax), %xmm2
+
+vpmovsxdq %xmm0, %xmm2
+vpmovsxdq (%rax), %xmm2
+
+vpmovsxwd %xmm0, %xmm2
+vpmovsxwd (%rax), %xmm2
+
+vpmovsxwq %xmm0, %xmm2
+vpmovsxwq (%rax), %xmm2
+
+vpmovzxbd %xmm0, %xmm2
+vpmovzxbd (%rax), %xmm2
+
+vpmovzxbq %xmm0, %xmm2
+vpmovzxbq (%rax), %xmm2
+
+vpmovzxbw %xmm0, %xmm2
+vpmovzxbw (%rax), %xmm2
+
+vpmovzxdq %xmm0, %xmm2
+vpmovzxdq (%rax), %xmm2
+
+vpmovzxwd %xmm0, %xmm2
+vpmovzxwd (%rax), %xmm2
+
+vpmovzxwq %xmm0, %xmm2
+vpmovzxwq (%rax), %xmm2
+
+vpmuldq %xmm0, %xmm1, %xmm2
+vpmuldq (%rax), %xmm1, %xmm2
+
+vpmulhrsw %xmm0, %xmm1, %xmm2
+vpmulhrsw (%rax), %xmm1, %xmm2
+
+vpmulhuw %xmm0, %xmm1, %xmm2
+vpmulhuw (%rax), %xmm1, %xmm2
+
+vpmulhw %xmm0, %xmm1, %xmm2
+vpmulhw (%rax), %xmm1, %xmm2
+
+vpmulld %xmm0, %xmm1, %xmm2
+vpmulld (%rax), %xmm1, %xmm2
+
+vpmullw %xmm0, %xmm1, %xmm2
+vpmullw (%rax), %xmm1, %xmm2
+
+vpmuludq %xmm0, %xmm1, %xmm2
+vpmuludq (%rax), %xmm1, %xmm2
+
+vpor %xmm0, %xmm1, %xmm2
+vpor (%rax), %xmm1, %xmm2
+
+vpsadbw %xmm0, %xmm1, %xmm2
+vpsadbw (%rax), %xmm1, %xmm2
+
+vpshufb %xmm0, %xmm1, %xmm2
+vpshufb (%rax), %xmm1, %xmm2
+
+vpshufd $1, %xmm0, %xmm2
+vpshufd $1, (%rax), %xmm2
+
+vpshufhw $1, %xmm0, %xmm2
+vpshufhw $1, (%rax), %xmm2
+
+vpshuflw $1, %xmm0, %xmm2
+vpshuflw $1, (%rax), %xmm2
+
+vpsignb %xmm0, %xmm1, %xmm2
+vpsignb (%rax), %xmm1, %xmm2
+
+vpsignd %xmm0, %xmm1, %xmm2
+vpsignd (%rax), %xmm1, %xmm2
+
+vpsignw %xmm0, %xmm1, %xmm2
+vpsignw (%rax), %xmm1, %xmm2
+
+vpslld $1, %xmm0, %xmm2
+vpslld %xmm0, %xmm1, %xmm2
+vpslld (%rax), %xmm1, %xmm2
+
+vpslldq $1, %xmm1, %xmm2
+
+vpsllq $1, %xmm0, %xmm2
+vpsllq %xmm0, %xmm1, %xmm2
+vpsllq (%rax), %xmm1, %xmm2
+
+vpsllw $1, %xmm0, %xmm2
+vpsllw %xmm0, %xmm1, %xmm2
+vpsllw (%rax), %xmm1, %xmm2
+
+vpsrad $1, %xmm0, %xmm2
+vpsrad %xmm0, %xmm1, %xmm2
+vpsrad (%rax), %xmm1, %xmm2
+
+vpsraw $1, %xmm0, %xmm2
+vpsraw %xmm0, %xmm1, %xmm2
+vpsraw (%rax), %xmm1, %xmm2
+
+vpsrld $1, %xmm0, %xmm2
+vpsrld %xmm0, %xmm1, %xmm2
+vpsrld (%rax), %xmm1, %xmm2
+
+vpsrldq $1, %xmm1, %xmm2
+
+vpsrlq $1, %xmm0, %xmm2
+vpsrlq %xmm0, %xmm1, %xmm2
+vpsrlq (%rax), %xmm1, %xmm2
+
+vpsrlw $1, %xmm0, %xmm2
+vpsrlw %xmm0, %xmm1, %xmm2
+vpsrlw (%rax), %xmm1, %xmm2
+
+vpsubb %xmm0, %xmm1, %xmm2
+vpsubb (%rax), %xmm1, %xmm2
+
+vpsubd %xmm0, %xmm1, %xmm2
+vpsubd (%rax), %xmm1, %xmm2
+
+vpsubq %xmm0, %xmm1, %xmm2
+vpsubq (%rax), %xmm1, %xmm2
+
+vpsubsb %xmm0, %xmm1, %xmm2
+vpsubsb (%rax), %xmm1, %xmm2
+
+vpsubsw %xmm0, %xmm1, %xmm2
+vpsubsw (%rax), %xmm1, %xmm2
+
+vpsubusb %xmm0, %xmm1, %xmm2
+vpsubusb (%rax), %xmm1, %xmm2
+
+vpsubusw %xmm0, %xmm1, %xmm2
+vpsubusw (%rax), %xmm1, %xmm2
+
+vpsubw %xmm0, %xmm1, %xmm2
+vpsubw (%rax), %xmm1, %xmm2
+
+vptest %xmm0, %xmm1
+vptest (%rax), %xmm1
+
+vptest %ymm0, %ymm1
+vptest (%rax), %ymm1
+
+vpunpckhbw %xmm0, %xmm1, %xmm2
+vpunpckhbw (%rax), %xmm1, %xmm2
+
+vpunpckhdq %xmm0, %xmm1, %xmm2
+vpunpckhdq (%rax), %xmm1, %xmm2
+
+vpunpckhqdq %xmm0, %xmm1, %xmm2
+vpunpckhqdq (%rax), %xmm1, %xmm2
+
+vpunpckhwd %xmm0, %xmm1, %xmm2
+vpunpckhwd (%rax), %xmm1, %xmm2
+
+vpunpcklbw %xmm0, %xmm1, %xmm2
+vpunpcklbw (%rax), %xmm1, %xmm2
+
+vpunpckldq %xmm0, %xmm1, %xmm2
+vpunpckldq (%rax), %xmm1, %xmm2
+
+vpunpcklqdq %xmm0, %xmm1, %xmm2
+vpunpcklqdq (%rax), %xmm1, %xmm2
+
+vpunpcklwd %xmm0, %xmm1, %xmm2
+vpunpcklwd (%rax), %xmm1, %xmm2
+
+vpxor %xmm0, %xmm1, %xmm2
+vpxor (%rax), %xmm1, %xmm2
+
+vrcpps %xmm0, %xmm2
+vrcpps (%rax), %xmm2
+
+vrcpps %ymm0, %ymm2
+vrcpps (%rax), %ymm2
+
+vrcpss %xmm0, %xmm1, %xmm2
+vrcpss (%rax), %xmm1, %xmm2
+
+vroundpd $1, %xmm0, %xmm2
+vroundpd $1, (%rax), %xmm2
+
+vroundpd $1, %ymm0, %ymm2
+vroundpd $1, (%rax), %ymm2
+
+vroundps $1, %xmm0, %xmm2
+vroundps $1, (%rax), %xmm2
+
+vroundps $1, %ymm0, %ymm2
+vroundps $1, (%rax), %ymm2
+
+vroundsd $1, %xmm0, %xmm1, %xmm2
+vroundsd $1, (%rax), %xmm1, %xmm2
+
+vroundss $1, %xmm0, %xmm1, %xmm2
+vroundss $1, (%rax), %xmm1, %xmm2
+
+vrsqrtps %xmm0, %xmm2
+vrsqrtps (%rax), %xmm2
+
+vrsqrtps %ymm0, %ymm2
+vrsqrtps (%rax), %ymm2
+
+vrsqrtss %xmm0, %xmm1, %xmm2
+vrsqrtss (%rax), %xmm1, %xmm2
+
+vshufpd $1, %xmm0, %xmm1, %xmm2
+vshufpd $1, (%rax), %xmm1, %xmm2
+
+vshufpd $1, %ymm0, %ymm1, %ymm2
+vshufpd $1, (%rax), %ymm1, %ymm2
+
+vshufps $1, %xmm0, %xmm1, %xmm2
+vshufps $1, (%rax), %xmm1, %xmm2
+
+vshufps $1, %ymm0, %ymm1, %ymm2
+vshufps $1, (%rax), %ymm1, %ymm2
+
+vsqrtpd %xmm0, %xmm2
+vsqrtpd (%rax), %xmm2
+
+vsqrtpd %ymm0, %ymm2
+vsqrtpd (%rax), %ymm2
+
+vsqrtps %xmm0, %xmm2
+vsqrtps (%rax), %xmm2
+
+vsqrtps %ymm0, %ymm2
+vsqrtps (%rax), %ymm2
+
+vsqrtsd %xmm0, %xmm1, %xmm2
+vsqrtsd (%rax), %xmm1, %xmm2
+
+vsqrtss %xmm0, %xmm1, %xmm2
+vsqrtss (%rax), %xmm1, %xmm2
+
+vstmxcsr (%rax)
+
+vsubpd %xmm0, %xmm1, %xmm2
+vsubpd (%rax), %xmm1, %xmm2
+
+vsubpd %ymm0, %ymm1, %ymm2
+vsubpd (%rax), %ymm1, %ymm2
+
+vsubps %xmm0, %xmm1, %xmm2
+vsubps (%rax), %xmm1, %xmm2
+
+vsubps %ymm0, %ymm1, %ymm2
+vsubps (%rax), %ymm1, %ymm2
+
+vsubsd %xmm0, %xmm1, %xmm2
+vsubsd (%rax), %xmm1, %xmm2
+
+vsubss %xmm0, %xmm1, %xmm2
+vsubss (%rax), %xmm1, %xmm2
+
+vtestpd %xmm0, %xmm1
+vtestpd (%rax), %xmm1
+
+vtestpd %ymm0, %ymm1
+vtestpd (%rax), %ymm1
+
+vtestps %xmm0, %xmm1
+vtestps (%rax), %xmm1
+
+vtestps %ymm0, %ymm1
+vtestps (%rax), %ymm1
+
+vucomisd %xmm0, %xmm1
+vucomisd (%rax), %xmm1
+
+vucomiss %xmm0, %xmm1
+vucomiss (%rax), %xmm1
+
+vunpckhpd %xmm0, %xmm1, %xmm2
+vunpckhpd (%rax), %xmm1, %xmm2
+
+vunpckhpd %ymm0, %ymm1, %ymm2
+vunpckhpd (%rax), %ymm1, %ymm2
+
+vunpckhps %xmm0, %xmm1, %xmm2
+vunpckhps (%rax), %xmm1, %xmm2
+
+vunpckhps %ymm0, %ymm1, %ymm2
+vunpckhps (%rax), %ymm1, %ymm2
+
+vunpcklpd %xmm0, %xmm1, %xmm2
+vunpcklpd (%rax), %xmm1, %xmm2
+
+vunpcklpd %ymm0, %ymm1, %ymm2
+vunpcklpd (%rax), %ymm1, %ymm2
+
+vunpcklps %xmm0, %xmm1, %xmm2
+vunpcklps (%rax), %xmm1, %xmm2
+
+vunpcklps %ymm0, %ymm1, %ymm2
+vunpcklps (%rax), %ymm1, %ymm2
+
+vxorpd %xmm0, %xmm1, %xmm2
+vxorpd (%rax), %xmm1, %xmm2
+
+vxorpd %ymm0, %ymm1, %ymm2
+vxorpd (%rax), %ymm1, %ymm2
+
+vxorps %xmm0, %xmm1, %xmm2
+vxorps (%rax), %xmm1, %xmm2
+
+vxorps %ymm0, %ymm1, %ymm2
+vxorps (%rax), %ymm1, %ymm2
+
+vzeroall
+vzeroupper
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 vaddpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vaddpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaddpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vaddpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vaddps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vaddps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaddps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vaddps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vaddsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vaddsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaddss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vaddss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaddsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vaddsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaddsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vaddsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vaddsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vaddsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaddsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vaddsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vaesdec %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vaesdec (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vaesdeclast %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vaesdeclast (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vaesenc %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vaesenc (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vaesenclast %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vaesenclast (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vaesimc %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vaesimc (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 vaeskeygenassist $22, %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vaeskeygenassist $22, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 vandnpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vandnpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vandnpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vandnpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vandnps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vandnps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vandnps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vandnps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vandpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vandpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vandpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vandpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vandps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vandps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vandps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vandps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vblendpd $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vblendpd $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vblendpd $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vblendpd $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vblendps $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vblendps $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vblendps $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vblendps $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vblendvpd %xmm3, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vblendvpd %xmm3, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vblendvpd %ymm3, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vblendvpd %ymm3, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vblendvps %xmm3, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vblendvps %xmm3, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vblendvps %ymm3, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vblendvps %ymm3, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vbroadcastf128 (%rax), %ymm2
+# CHECK-NEXT: 1 8 0.50 * vbroadcastsd (%rax), %ymm2
+# CHECK-NEXT: 1 8 0.50 * vbroadcastss (%rax), %xmm2
+# CHECK-NEXT: 1 8 0.50 * vbroadcastss (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vcmpeqpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vcmpeqpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vcmpeqpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vcmpeqpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vcmpeqps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vcmpeqps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vcmpeqps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vcmpeqps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vcmpeqsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vcmpeqsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vcmpeqss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vcmpeqss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 4 1.00 vcomisd %xmm0, %xmm1
+# CHECK-NEXT: 2 11 1.00 * vcomisd (%rax), %xmm1
+# CHECK-NEXT: 2 4 1.00 vcomiss %xmm0, %xmm1
+# CHECK-NEXT: 2 11 1.00 * vcomiss (%rax), %xmm1
+# CHECK-NEXT: 1 3 0.50 vcvtdq2pd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vcvtdq2pd (%rax), %xmm2
+# CHECK-NEXT: 2 4 1.00 vcvtdq2pd %xmm0, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vcvtdq2pd (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vcvtdq2ps %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vcvtdq2ps (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 vcvtdq2ps %ymm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vcvtdq2ps (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vcvtpd2dq %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vcvtpd2dqx (%rax), %xmm2
+# CHECK-NEXT: 2 6 1.00 vcvtpd2dq %ymm0, %xmm2
+# CHECK-NEXT: 2 13 1.00 * vcvtpd2dqy (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 vcvtpd2ps %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vcvtpd2psx (%rax), %xmm2
+# CHECK-NEXT: 2 6 1.00 vcvtpd2ps %ymm0, %xmm2
+# CHECK-NEXT: 2 13 1.00 * vcvtpd2psy (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 vcvtps2dq %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vcvtps2dq (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 vcvtps2dq %ymm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vcvtps2dq (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vcvtps2pd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vcvtps2pd (%rax), %xmm2
+# CHECK-NEXT: 2 4 1.00 vcvtps2pd %xmm0, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vcvtps2pd (%rax), %ymm2
+# CHECK-NEXT: 2 2 1.00 vcvtsd2si %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 vcvtsd2si %xmm0, %rcx
+# CHECK-NEXT: 2 9 1.00 * vcvtsd2si (%rax), %ecx
+# CHECK-NEXT: 2 9 1.00 * vcvtsd2si (%rax), %rcx
+# CHECK-NEXT: 1 3 0.50 vcvtsd2ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vcvtsd2ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 4 1.00 vcvtsi2sd %ecx, %xmm0, %xmm2
+# CHECK-NEXT: 2 4 1.00 vcvtsi2sd %rcx, %xmm0, %xmm2
+# CHECK-NEXT: 1 10 1.00 * vcvtsi2sdl (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 1 10 1.00 * vcvtsi2sdq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 2 4 1.00 vcvtsi2ss %ecx, %xmm0, %xmm2
+# CHECK-NEXT: 2 4 1.00 vcvtsi2ss %rcx, %xmm0, %xmm2
+# CHECK-NEXT: 1 10 1.00 * vcvtsi2ssl (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 1 10 1.00 * vcvtsi2ssq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 1 3 0.50 vcvtss2sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vcvtss2sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 2 1.00 vcvtss2si %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 vcvtss2si %xmm0, %rcx
+# CHECK-NEXT: 2 9 1.00 * vcvtss2si (%rax), %ecx
+# CHECK-NEXT: 2 9 1.00 * vcvtss2si (%rax), %rcx
+# CHECK-NEXT: 1 3 0.50 vcvttpd2dq %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vcvttpd2dqx (%rax), %xmm2
+# CHECK-NEXT: 2 6 1.00 vcvttpd2dq %ymm0, %xmm2
+# CHECK-NEXT: 2 13 1.00 * vcvttpd2dqy (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 vcvttps2dq %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vcvttps2dq (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 vcvttps2dq %ymm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vcvttps2dq (%rax), %ymm2
+# CHECK-NEXT: 2 2 1.00 vcvttsd2si %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 vcvttsd2si %xmm0, %rcx
+# CHECK-NEXT: 2 9 1.00 * vcvttsd2si (%rax), %ecx
+# CHECK-NEXT: 2 9 1.00 * vcvttsd2si (%rax), %rcx
+# CHECK-NEXT: 2 2 1.00 vcvttss2si %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 vcvttss2si %xmm0, %rcx
+# CHECK-NEXT: 2 9 1.00 * vcvttss2si (%rax), %ecx
+# CHECK-NEXT: 2 9 1.00 * vcvttss2si (%rax), %rcx
+# CHECK-NEXT: 1 13 5.00 vdivpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 20 5.00 * vdivpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 13 5.00 vdivpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 20 5.00 * vdivpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 11 3.00 vdivps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 18 3.00 * vdivps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 11 3.00 vdivps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 18 3.00 * vdivps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 13 5.00 vdivsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 20 5.00 * vdivsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 11 3.00 vdivss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 18 3.00 * vdivss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 9 3.00 vdppd $22, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 5 16 3.00 * vdppd $22, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 8 15 4.00 vdpps $22, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 10 22 4.00 * vdpps $22, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 7 15 4.00 vdpps $22, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 8 22 4.00 * vdpps $22, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vextractf128 $1, %ymm0, %xmm2
+# CHECK-NEXT: 2 8 1.00 * vextractf128 $1, %ymm0, (%rax)
+# CHECK-NEXT: 2 1 1.00 vextractps $1, %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 * vextractps $1, %xmm0, (%rax)
+# CHECK-NEXT: 4 6 2.00 vhaddpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 13 2.00 * vhaddpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 6 2.00 vhaddpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 13 2.00 * vhaddpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 4 6 2.00 vhaddps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 13 2.00 * vhaddps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 6 2.00 vhaddps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 13 2.00 * vhaddps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 4 6 2.00 vhsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 13 2.00 * vhsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 6 2.00 vhsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 13 2.00 * vhsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 4 6 2.00 vhsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 13 2.00 * vhsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 6 2.00 vhsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 13 2.00 * vhsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 2 1.00 vinsertf128 $1, %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 1.00 * vinsertf128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vinsertps $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vinsertps $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vlddqu (%rax), %xmm2
+# CHECK-NEXT: 1 8 0.50 * vlddqu (%rax), %ymm2
+# CHECK-NEXT: 1 5 1.50 * * U vldmxcsr (%rax)
+# CHECK-NEXT: 1 1 1.00 * * U vmaskmovdqu %xmm0, %xmm1
+# CHECK-NEXT: 1 8 0.50 * vmaskmovpd (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vmaskmovpd (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 10 1 4.00 * * vmaskmovpd %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 18 1 6.00 * * vmaskmovpd %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmaskmovps (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vmaskmovps (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 18 1 6.00 * * vmaskmovps %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 42 1 12.00 * * vmaskmovps %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: 1 1 0.50 vmaxpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vmaxpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vmaxpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vmaxpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vmaxps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vmaxps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vmaxps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vmaxps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vmaxsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vmaxsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vmaxss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vmaxss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vminpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vminpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vminpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vminpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vminps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vminps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vminps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vminps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vminsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vminsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vminss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vminss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 0 0.25 vmovapd %xmm0, %xmm2
+# CHECK-NEXT: 1 1 1.00 * vmovapd %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovapd (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 vmovapd %ymm0, %ymm2
+# CHECK-NEXT: 1 1 1.00 * vmovapd %ymm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovapd (%rax), %ymm2
+# CHECK-NEXT: 1 0 0.25 vmovaps %xmm0, %xmm2
+# CHECK-NEXT: 1 1 1.00 * vmovaps %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovaps (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 vmovaps %ymm0, %ymm2
+# CHECK-NEXT: 1 1 1.00 * vmovaps %ymm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovaps (%rax), %ymm2
+# CHECK-NEXT: 1 1 1.00 vmovd %eax, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vmovd (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 vmovd %xmm0, %ecx
+# CHECK-NEXT: 1 1 1.00 * vmovd %xmm0, (%rax)
+# CHECK-NEXT: 1 1 0.50 vmovddup %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vmovddup (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vmovddup %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vmovddup (%rax), %ymm2
+# CHECK-NEXT: 1 0 0.25 vmovdqa %xmm0, %xmm2
+# CHECK-NEXT: 1 1 1.00 * vmovdqa %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovdqa (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 vmovdqa %ymm0, %ymm2
+# CHECK-NEXT: 1 1 1.00 * vmovdqa %ymm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovdqa (%rax), %ymm2
+# CHECK-NEXT: 1 0 0.25 vmovdqu %xmm0, %xmm2
+# CHECK-NEXT: 1 1 1.00 * vmovdqu %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovdqu (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 vmovdqu %ymm0, %ymm2
+# CHECK-NEXT: 1 1 1.00 * vmovdqu %ymm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovdqu (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vmovhlps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vmovlhps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 2 1.00 * vmovhpd %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovhpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 2 1.00 * vmovhps %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovhps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 1.00 * vmovlpd %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovlpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 1.00 * vmovlps %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovlps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 1.00 vmovmskpd %xmm0, %ecx
+# CHECK-NEXT: 1 1 1.00 vmovmskpd %ymm0, %ecx
+# CHECK-NEXT: 1 1 1.00 vmovmskps %xmm0, %ecx
+# CHECK-NEXT: 1 1 1.00 vmovmskps %ymm0, %ecx
+# CHECK-NEXT: 1 1 1.00 * vmovntdq %xmm0, (%rax)
+# CHECK-NEXT: 1 1 1.00 * vmovntdq %ymm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovntdqa (%rax), %xmm2
+# CHECK-NEXT: 1 8 0.50 * vmovntdqa (%rax), %ymm2
+# CHECK-NEXT: 1 1 1.00 * vmovntpd %xmm0, (%rax)
+# CHECK-NEXT: 1 1 1.00 * vmovntpd %ymm0, (%rax)
+# CHECK-NEXT: 1 1 1.00 * vmovntps %xmm0, (%rax)
+# CHECK-NEXT: 1 1 1.00 * vmovntps %ymm0, (%rax)
+# CHECK-NEXT: 1 1 0.25 vmovq %xmm0, %xmm2
+# CHECK-NEXT: 1 1 1.00 vmovq %rax, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vmovq (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 vmovq %xmm0, %rcx
+# CHECK-NEXT: 1 1 1.00 * vmovq %xmm0, (%rax)
+# CHECK-NEXT: 1 1 0.50 vmovsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 1 1.00 * vmovsd %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vmovshdup %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vmovshdup (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vmovshdup %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vmovshdup (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vmovsldup %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vmovsldup (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vmovsldup %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vmovsldup (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vmovss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 1 1.00 * vmovss %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovss (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 vmovupd %xmm0, %xmm2
+# CHECK-NEXT: 1 1 1.00 * vmovupd %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovupd (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 vmovupd %ymm0, %ymm2
+# CHECK-NEXT: 1 1 1.00 * vmovupd %ymm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovupd (%rax), %ymm2
+# CHECK-NEXT: 1 0 0.25 vmovups %xmm0, %xmm2
+# CHECK-NEXT: 1 1 1.00 * vmovups %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovups (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 vmovups %ymm0, %ymm2
+# CHECK-NEXT: 1 1 1.00 * vmovups %ymm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovups (%rax), %ymm2
+# CHECK-NEXT: 4 4 2.00 vmpsadbw $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 6 11 2.00 * vmpsadbw $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vmulpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vmulpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vmulpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vmulpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vmulps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vmulps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vmulps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vmulps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vmulsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vmulsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vmulss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vmulss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vorpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vorpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vorpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vorpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vorps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vorps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vorps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vorps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpabsb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpabsb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpabsd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpabsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpabsw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpabsw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpackssdw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpackssdw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpacksswb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpacksswb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpackusdw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpackusdw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpackuswb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpackuswb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpaddb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpaddb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpaddd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpaddd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpaddq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpaddq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpaddsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpaddsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpaddsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpaddsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpaddusb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpaddusb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpaddusw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpaddusw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpaddw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpaddw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpalignr $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpalignr $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpand %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpand (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpandn %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpandn (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpavgb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpavgb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpavgw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpavgw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpblendvb %xmm3, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpblendvb %xmm3, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpblendw $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpblendw $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 4 2.00 vpclmulqdq $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 11 2.00 * vpclmulqdq $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpcmpeqb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpcmpeqb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpcmpeqd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpcmpeqd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpcmpeqq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpcmpeqq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpcmpeqw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpcmpeqw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 8 6 3.00 vpcmpestri $1, %xmm0, %xmm2
+# CHECK-NEXT: 12 13 3.00 * vpcmpestri $1, (%rax), %xmm2
+# CHECK-NEXT: 7 6 3.00 vpcmpestrm $1, %xmm0, %xmm2
+# CHECK-NEXT: 12 13 3.00 * vpcmpestrm $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 vpcmpgtb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpcmpgtb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpcmpgtd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpcmpgtd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpcmpgtq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpcmpgtq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpcmpgtw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpcmpgtw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 2 2.00 vpcmpistri $1, %xmm0, %xmm2
+# CHECK-NEXT: 4 9 2.00 * vpcmpistri $1, (%rax), %xmm2
+# CHECK-NEXT: 3 6 2.00 vpcmpistrm $1, %xmm0, %xmm2
+# CHECK-NEXT: 4 13 2.00 * vpcmpistrm $1, (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.00 vperm2f128 $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 7 1.00 * vperm2f128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpermilpd $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpermilpd $1, (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 vpermilpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vpermilpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpermilpd $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpermilpd $1, (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpermilpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpermilpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpermilps $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpermilps $1, (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 vpermilps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vpermilps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpermilps $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpermilps $1, (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpermilps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpermilps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 1 1.00 vpextrb $1, %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 * vpextrb $1, %xmm0, (%rax)
+# CHECK-NEXT: 2 1 1.00 vpextrd $1, %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 * vpextrd $1, %xmm0, (%rax)
+# CHECK-NEXT: 2 1 1.00 vpextrq $1, %xmm0, %rcx
+# CHECK-NEXT: 2 2 1.00 * vpextrq $1, %xmm0, (%rax)
+# CHECK-NEXT: 2 1 1.00 vpextrw $1, %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 * vpextrw $1, %xmm0, (%rax)
+# CHECK-NEXT: 4 2 2.00 vphaddd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 9 2.00 * vphaddd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 2 2.00 vphaddsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 9 2.00 * vphaddsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 2 2.00 vphaddw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 9 2.00 * vphaddw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vphminposuw %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vphminposuw (%rax), %xmm2
+# CHECK-NEXT: 4 2 2.00 vphsubd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 9 2.00 * vphsubd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 2 2.00 vphsubsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 9 2.00 * vphsubsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 2 2.00 vphsubw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 9 2.00 * vphsubw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 2 1.00 vpinsrb $1, %eax, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 1.50 * vpinsrb $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 2 1.00 vpinsrd $1, %eax, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 1.50 * vpinsrd $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 2 1.00 vpinsrq $1, %rax, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 1.50 * vpinsrq $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 2 1.00 vpinsrw $1, %eax, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 1.50 * vpinsrw $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vpmaddubsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vpmaddubsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vpmaddwd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vpmaddwd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpmaxsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmaxsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpmaxsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmaxsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpmaxsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmaxsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpmaxub %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmaxub (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpmaxud %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmaxud (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpmaxuw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmaxuw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpminsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpminsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpminsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpminsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpminsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpminsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpminub %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpminub (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpminud %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpminud (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpminuw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpminuw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 1.00 vpmovmskb %xmm0, %ecx
+# CHECK-NEXT: 1 1 0.50 vpmovsxbd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovsxbd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovsxbq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovsxbq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovsxbw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovsxbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovsxdq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovsxdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovsxwd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovsxwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovsxwq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovsxwq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovzxbd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovzxbd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovzxbq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovzxbq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovzxbw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovzxbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovzxdq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovzxdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovzxwd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovzxwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovzxwq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovzxwq (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 vpmuldq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vpmuldq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vpmulhrsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vpmulhrsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vpmulhuw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vpmulhuw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vpmulhw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vpmulhw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vpmulld %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vpmulld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vpmullw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vpmullw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vpmuludq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vpmuludq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpor %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpor (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vpsadbw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vpsadbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpshufb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpshufb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpshufd $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpshufd $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpshufhw $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpshufhw $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpshuflw $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpshuflw $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsignb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsignb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsignd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsignd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsignw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsignw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpslld $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpslld %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpslld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpslldq $1, %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsllq $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsllq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsllq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsllw $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsllw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsllw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrad $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrad %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsrad (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsraw $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsraw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsraw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrld $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrld %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsrld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrldq $1, %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrlq $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrlq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsrlq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrlw $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrlw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsrlw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpsubb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsubb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpsubd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsubd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpsubq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsubq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsubsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsubsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsubsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsubsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsubusb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsubusb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsubusw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsubusw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpsubw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsubw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 1 1.00 vptest %xmm0, %xmm1
+# CHECK-NEXT: 2 8 1.00 * vptest (%rax), %xmm1
+# CHECK-NEXT: 2 1 1.00 vptest %ymm0, %ymm1
+# CHECK-NEXT: 2 8 1.00 * vptest (%rax), %ymm1
+# CHECK-NEXT: 1 1 0.50 vpunpckhbw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpunpckhbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhdq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpunpckhdq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhqdq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpunpckhqdq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhwd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpunpckhwd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpcklbw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpunpcklbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpckldq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpunpckldq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpcklqdq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpunpcklqdq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpcklwd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpunpcklwd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpxor %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpxor (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vrcpps %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vrcpps (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 vrcpps %ymm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vrcpps (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vrcpss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vrcpss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vroundpd $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vroundpd $1, (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 vroundpd $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vroundpd $1, (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vroundps $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vroundps $1, (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 vroundps $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vroundps $1, (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vroundsd $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vroundsd $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vroundss $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vroundss $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 1.00 vrsqrtps %xmm0, %xmm2
+# CHECK-NEXT: 1 10 1.00 * vrsqrtps (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.00 vrsqrtps %ymm0, %ymm2
+# CHECK-NEXT: 1 10 1.00 * vrsqrtps (%rax), %ymm2
+# CHECK-NEXT: 1 3 1.00 vrsqrtss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 1.00 * vrsqrtss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vshufpd $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vshufpd $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vshufpd $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vshufpd $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vshufps $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vshufps $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vshufps $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vshufps $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 21 9.00 vsqrtpd %xmm0, %xmm2
+# CHECK-NEXT: 1 28 9.00 * vsqrtpd (%rax), %xmm2
+# CHECK-NEXT: 1 21 9.00 vsqrtpd %ymm0, %ymm2
+# CHECK-NEXT: 1 28 9.00 * vsqrtpd (%rax), %ymm2
+# CHECK-NEXT: 1 15 5.00 vsqrtps %xmm0, %xmm2
+# CHECK-NEXT: 1 22 5.00 * vsqrtps (%rax), %xmm2
+# CHECK-NEXT: 1 15 5.00 vsqrtps %ymm0, %ymm2
+# CHECK-NEXT: 1 22 5.00 * vsqrtps (%rax), %ymm2
+# CHECK-NEXT: 1 21 9.00 vsqrtsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 28 9.00 * vsqrtsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 15 5.00 vsqrtss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 22 5.00 * vsqrtss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 2 15.00 * U vstmxcsr (%rax)
+# CHECK-NEXT: 1 3 0.50 vsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vsubsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vsubsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vsubss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vsubss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 1 1.00 vtestpd %xmm0, %xmm1
+# CHECK-NEXT: 2 8 1.00 * vtestpd (%rax), %xmm1
+# CHECK-NEXT: 2 1 1.00 vtestpd %ymm0, %ymm1
+# CHECK-NEXT: 2 8 1.00 * vtestpd (%rax), %ymm1
+# CHECK-NEXT: 2 1 1.00 vtestps %xmm0, %xmm1
+# CHECK-NEXT: 2 8 1.00 * vtestps (%rax), %xmm1
+# CHECK-NEXT: 2 1 1.00 vtestps %ymm0, %ymm1
+# CHECK-NEXT: 2 8 1.00 * vtestps (%rax), %ymm1
+# CHECK-NEXT: 2 4 1.00 vucomisd %xmm0, %xmm1
+# CHECK-NEXT: 2 11 1.00 * vucomisd (%rax), %xmm1
+# CHECK-NEXT: 2 4 1.00 vucomiss %xmm0, %xmm1
+# CHECK-NEXT: 2 11 1.00 * vucomiss (%rax), %xmm1
+# CHECK-NEXT: 1 1 0.50 vunpckhpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vunpckhpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vunpckhpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vunpckhpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vunpckhps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vunpckhps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vunpckhps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vunpckhps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vunpcklpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vunpcklpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vunpcklpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vunpcklpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vunpcklps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vunpcklps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vunpcklps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vunpcklps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vxorpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vxorpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vxorpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vxorpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vxorps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vxorps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vxorps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vxorps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 18 10 6.00 U vzeroall
+# CHECK-NEXT: 1 0 0.25 U vzeroupper
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: 1.33 1.33 1.33 16.50 16.50 16.50 16.50 - 184.25 373.25 253.75 141.75 208.50 208.50 65.00 119.67 119.67 119.67 107.00 107.00 107.00 19.00 19.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vaddpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vaddpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vaddpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vaddpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vaddps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vaddps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vaddps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vaddps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vaddsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vaddsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vaddss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vaddss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vaddsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vaddsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vaddsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vaddsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vaddsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vaddsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vaddsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vaddsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vaesdec %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vaesdec (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vaesdeclast %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vaesdeclast (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vaesenc %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vaesenc (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vaesenclast %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vaesenclast (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vaesimc %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vaesimc (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vaeskeygenassist $22, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vaeskeygenassist $22, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandnpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vandnpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandnpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vandnpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandnps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vandnps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandnps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vandnps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vandpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vandpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vandps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vandps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vblendpd $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vblendpd $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vblendpd $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vblendpd $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vblendps $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vblendps $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vblendps $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vblendps $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vblendvpd %xmm3, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vblendvpd %xmm3, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vblendvpd %ymm3, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vblendvpd %ymm3, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vblendvps %xmm3, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vblendvps %xmm3, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vblendvps %ymm3, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vblendvps %ymm3, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vbroadcastf128 (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vbroadcastsd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vbroadcastss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vbroadcastss (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vcmpeqpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcmpeqpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vcmpeqpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcmpeqpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vcmpeqps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcmpeqps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vcmpeqps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcmpeqps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vcmpeqsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcmpeqsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vcmpeqss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcmpeqss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vcomisd %xmm0, %xmm1
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcomisd (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vcomiss %xmm0, %xmm1
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcomiss (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vcvtdq2pd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcvtdq2pd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - vcvtdq2pd %xmm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcvtdq2pd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vcvtdq2ps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcvtdq2ps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vcvtdq2ps %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcvtdq2ps (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vcvtpd2dq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcvtpd2dqx (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - vcvtpd2dq %ymm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcvtpd2dqy (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vcvtpd2ps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcvtpd2psx (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - vcvtpd2ps %ymm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcvtpd2psy (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vcvtps2dq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcvtps2dq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vcvtps2dq %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcvtps2dq (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vcvtps2pd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcvtps2pd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - vcvtps2pd %xmm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcvtps2pd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - vcvtsd2si %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - vcvtsd2si %xmm0, %rcx
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcvtsd2si (%rax), %ecx
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcvtsd2si (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vcvtsd2ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcvtsd2ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - vcvtsi2sd %ecx, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - vcvtsi2sd %rcx, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcvtsi2sdl (%rax), %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcvtsi2sdq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - vcvtsi2ss %ecx, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - vcvtsi2ss %rcx, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcvtsi2ssl (%rax), %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcvtsi2ssq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vcvtss2sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcvtss2sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - vcvtss2si %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - vcvtss2si %xmm0, %rcx
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcvtss2si (%rax), %ecx
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcvtss2si (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vcvttpd2dq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcvttpd2dqx (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - vcvttpd2dq %ymm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcvttpd2dqy (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vcvttps2dq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcvttps2dq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vcvttps2dq %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcvttps2dq (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - vcvttsd2si %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - vcvttsd2si %xmm0, %rcx
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcvttsd2si (%rax), %ecx
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcvttsd2si (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - vcvttss2si %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - vcvttss2si %xmm0, %rcx
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcvttss2si (%rax), %ecx
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcvttss2si (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - - 5.00 - - - - - - - - - - - - - vdivpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 5.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vdivpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 5.00 - - - - - - - - - - - - - vdivpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 5.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vdivpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - - - - - - - - - - - vdivps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 3.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vdivps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - - - - - - - - - - - vdivps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 3.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vdivps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 5.00 - - - - - - - - - - - - - vdivsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 5.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vdivsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - - - - - - - - - - - vdivss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 3.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vdivss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 3.00 3.00 - - - - - - - - - - - - - vdppd $22, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 3.00 3.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vdppd $22, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 4.00 4.00 - - - - - - - - - - - - - vdpps $22, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 4.00 4.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vdpps $22, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 4.00 4.00 - - - - - - - - - - - - - vdpps $22, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 4.00 4.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vdpps $22, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - - - - vextractf128 $1, %ymm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vextractf128 $1, %ymm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - vextractps $1, %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vextractps $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - 2.00 - - - - - - - - - - - - vhaddpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 2.00 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vhaddpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 2.00 - - - - - - - - - - - - vhaddpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - 2.00 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vhaddpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - 2.00 - - - - - - - - - - - - vhaddps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 2.00 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vhaddps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 2.00 - - - - - - - - - - - - vhaddps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - 2.00 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vhaddps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - 2.00 - - - - - - - - - - - - vhsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 2.00 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vhsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 2.00 - - - - - - - - - - - - vhsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - 2.00 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vhsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - 2.00 - - - - - - - - - - - - vhsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 2.00 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vhsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 2.00 - - - - - - - - - - - - vhsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - 2.00 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vhsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - - - - vinsertf128 $1, %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - vinsertf128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vinsertps $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vinsertps $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vlddqu (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vlddqu (%rax), %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 1.50 1.50 1.50 1.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - vldmxcsr (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vmaskmovdqu %xmm0, %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmaskmovpd (%rax), %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmaskmovpd (%rax), %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 2.00 4.00 0.33 0.33 0.33 - - - 0.50 0.50 vmaskmovpd %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 3.00 3.00 6.00 0.33 0.33 0.33 - - - 0.50 0.50 vmaskmovpd %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmaskmovps (%rax), %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmaskmovps (%rax), %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - 3.00 3.00 6.00 0.33 0.33 0.33 - - - 0.50 0.50 vmaskmovps %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 6.00 6.00 12.00 0.33 0.33 0.33 - - - 0.50 0.50 vmaskmovps %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vmaxpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmaxpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vmaxpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmaxpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vmaxps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmaxps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vmaxps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmaxps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vmaxsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmaxsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vmaxss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmaxss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vminpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vminpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vminpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vminpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vminps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vminps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vminps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vminps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vminsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vminsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vminss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vminss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vmovapd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vmovapd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmovapd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vmovapd %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vmovapd %ymm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmovapd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vmovaps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vmovaps %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmovaps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vmovaps %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vmovaps %ymm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmovaps (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - vmovd %eax, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmovd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - vmovd %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vmovd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vmovddup %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmovddup (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vmovddup %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmovddup (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vmovdqa %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vmovdqa %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmovdqa (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vmovdqa %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vmovdqa %ymm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmovdqa (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vmovdqu %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vmovdqu %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmovdqu (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vmovdqu %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vmovdqu %ymm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmovdqu (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vmovhlps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vmovlhps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vmovhpd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmovhpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vmovhps %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmovhps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vmovlpd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmovlpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vmovlps %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmovlps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - - - - vmovmskpd %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - - - - vmovmskpd %ymm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - - - - vmovmskps %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - - - - vmovmskps %ymm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vmovntdq %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vmovntdq %ymm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmovntdqa (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmovntdqa (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vmovntpd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vmovntpd %ymm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vmovntps %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vmovntps %ymm0, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vmovq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - vmovq %rax, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmovq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - vmovq %xmm0, %rcx
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vmovq %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vmovsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vmovsd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmovsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vmovshdup %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmovshdup (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vmovshdup %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmovshdup (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vmovsldup %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmovsldup (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vmovsldup %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmovsldup (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vmovss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vmovss %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmovss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vmovupd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vmovupd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmovupd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vmovupd %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vmovupd %ymm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmovupd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vmovups %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vmovups %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmovups (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vmovups %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vmovups %ymm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmovups (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 2.00 2.00 2.00 2.00 - - - - - - - - - - - vmpsadbw $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 2.00 2.00 2.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmpsadbw $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vmulpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmulpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vmulpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmulpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vmulps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmulps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vmulps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmulps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vmulsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmulsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vmulss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmulss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vorpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vorpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vorpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vorpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vorps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vorps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vorps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vorps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpabsb %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpabsb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpabsd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpabsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpabsw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpabsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpackssdw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpackssdw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpacksswb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpacksswb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpackusdw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpackusdw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpackuswb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpackuswb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpaddb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpaddd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpaddq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpaddsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpaddsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpaddsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpaddsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpaddusb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpaddusb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpaddusw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpaddusw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpaddw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpalignr $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpalignr $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpand %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpand (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpandn %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpandn (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpavgb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpavgb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpavgw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpavgw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 - - - - - - - - - - - vpblendvb %xmm3, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpblendvb %xmm3, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpblendw $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpblendw $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 2.00 - - - - - - - - - - - - - vpclmulqdq $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 2.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpclmulqdq $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpeqb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpcmpeqb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpeqd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpcmpeqd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpcmpeqq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpcmpeqq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpeqw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpcmpeqw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - vpcmpestri $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 3.00 3.00 3.00 3.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpcmpestri $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - vpcmpestrm $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 3.00 3.00 3.00 3.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpcmpestrm $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpgtb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpcmpgtb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpgtd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpcmpgtd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpgtq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpcmpgtq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpgtw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpcmpgtw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 2.00 2.00 2.00 - - - - - - - - - - - vpcmpistri $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 2.00 2.00 2.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpcmpistri $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 2.00 2.00 2.00 - - - - - - - - - - - vpcmpistrm $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 2.00 2.00 2.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpcmpistrm $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - - - - vperm2f128 $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - vperm2f128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpermilpd $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpermilpd $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpermilpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpermilpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpermilpd $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpermilpd $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpermilpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpermilpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpermilps $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpermilps $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpermilps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpermilps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpermilps $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpermilps $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpermilps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpermilps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - vpextrb $1, %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vpextrb $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - vpextrd $1, %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vpextrd $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - vpextrq $1, %xmm0, %rcx
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vpextrq $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - vpextrw $1, %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vpextrw $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - - - - - vphaddd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vphaddd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - - - - - vphaddsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vphaddsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - - - - - vphaddw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vphaddw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vphminposuw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vphminposuw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - - - - - vphsubd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vphsubd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - - - - - vphsubsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vphsubsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - - - - - vphsubw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vphsubw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - vpinsrb $1, %eax, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpinsrb $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - vpinsrd $1, %eax, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpinsrd $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - vpinsrq $1, %rax, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpinsrq $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - vpinsrw $1, %eax, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpinsrw $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 - - - - - - - - - - - vpmaddubsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmaddubsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 - - - - - - - - - - - vpmaddwd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmaddwd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmaxsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmaxsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmaxsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxub %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmaxub (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxud %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmaxud (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxuw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmaxuw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpminsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpminsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpminsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminub %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpminub (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminud %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpminud (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminuw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpminuw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - - - - vpmovmskb %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpmovsxbd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmovsxbd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpmovsxbq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmovsxbq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpmovsxbw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmovsxbw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpmovsxdq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmovsxdq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpmovsxwd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmovsxwd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpmovsxwq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmovsxwq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpmovzxbd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmovzxbd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpmovzxbq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmovzxbq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpmovzxbw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmovzxbw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpmovzxdq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmovzxdq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpmovzxwd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmovzxwd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpmovzxwq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmovzxwq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 - - - - - - - - - - - vpmuldq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmuldq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 - - - - - - - - - - - vpmulhrsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmulhrsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 - - - - - - - - - - - vpmulhuw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmulhuw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 - - - - - - - - - - - vpmulhw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmulhw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 - - - - - - - - - - - vpmulld %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmulld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 - - - - - - - - - - - vpmullw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmullw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 - - - - - - - - - - - vpmuludq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmuludq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpor %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpor (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsadbw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsadbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpshufb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpshufb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpshufd $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpshufd $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpshufhw $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpshufhw $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpshuflw $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpshuflw $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpsignb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsignb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpsignd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsignd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpsignw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsignw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpslld $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpslld %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpslld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpslldq $1, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsllq $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsllq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsllq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsllw $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsllw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsllw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsrad $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsrad %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsrad (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsraw $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsraw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsraw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsrld $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsrld %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsrld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsrldq $1, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsrlq $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsrlq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsrlq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsrlw $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsrlw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsrlw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsubb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsubd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsubq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpsubsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsubsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpsubsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsubsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpsubusb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsubusb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpsubusw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsubusw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsubw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 1.00 - - - - - - - - vptest %xmm0, %xmm1
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 1.00 1.00 1.00 0.33 0.33 0.33 0.33 0.33 0.33 - - vptest (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 1.00 - - - - - - - - vptest %ymm0, %ymm1
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 1.00 1.00 1.00 0.33 0.33 0.33 0.33 0.33 0.33 - - vptest (%rax), %ymm1
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpunpckhbw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpunpckhbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpunpckhdq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpunpckhdq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpunpckhqdq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpunpckhqdq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpunpckhwd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpunpckhwd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpunpcklbw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpunpcklbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpunpckldq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpunpckldq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpunpcklqdq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpunpcklqdq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpunpcklwd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpunpcklwd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpxor %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpxor (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vrcpps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vrcpps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vrcpps %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vrcpps (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vrcpss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vrcpss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vroundpd $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vroundpd $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vroundpd $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vroundpd $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vroundps $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vroundps $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vroundps $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vroundps $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vroundsd $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vroundsd $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vroundss $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vroundss $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - - - - vrsqrtps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vrsqrtps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - - - - vrsqrtps %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vrsqrtps (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - - - - vrsqrtss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vrsqrtss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vshufpd $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vshufpd $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vshufpd $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vshufpd $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vshufps $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vshufps $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vshufps $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vshufps $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 9.00 - - - - - - - - - - - - - vsqrtpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 9.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vsqrtpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 9.00 - - - - - - - - - - - - - vsqrtpd %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 9.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vsqrtpd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 5.00 - - - - - - - - - - - - - vsqrtps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 5.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vsqrtps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 5.00 - - - - - - - - - - - - - vsqrtps %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 5.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vsqrtps (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 9.00 - - - - - - - - - - - - - vsqrtsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 9.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vsqrtsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 5.00 - - - - - - - - - - - - - vsqrtss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 5.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vsqrtss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 15.00 15.00 15.00 15.00 - - - - - - - - 0.33 0.33 0.33 - - - 0.50 0.50 vstmxcsr (%rax)
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vsubsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vsubsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vsubss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vsubss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - - - - - - - - - - vtestpd %xmm0, %xmm1
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vtestpd (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - - - - - - - - - - vtestpd %ymm0, %ymm1
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vtestpd (%rax), %ymm1
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - - - - - - - - - - vtestps %xmm0, %xmm1
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vtestps (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - - - - - - - - - - - - vtestps %ymm0, %ymm1
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vtestps (%rax), %ymm1
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vucomisd %xmm0, %xmm1
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vucomisd (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vucomiss %xmm0, %xmm1
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vucomiss (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vunpckhpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vunpckhpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vunpckhpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vunpckhpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vunpckhps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vunpckhps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vunpckhps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vunpckhps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vunpcklpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vunpcklpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vunpcklpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vunpcklpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vunpcklps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vunpcklps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vunpcklps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vunpcklps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vxorpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vxorpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vxorpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vxorpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vxorps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vxorps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vxorps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vxorps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 6.00 6.00 6.00 6.00 - - - - - - - - - - - vzeroall
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vzeroupper
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-avx2.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-avx2.s
new file mode 100644
index 0000000000000..3c6b31a1ca011
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-avx2.s
@@ -0,0 +1,1096 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+vbroadcasti128 (%rax), %ymm0
+
+vbroadcastsd %xmm0, %ymm0
+vbroadcastss %xmm0, %ymm0
+
+vextracti128 $1, %ymm0, %xmm2
+vextracti128 $1, %ymm0, (%rax)
+
+vgatherdpd %xmm0, (%rax,%xmm1,2), %xmm2
+vgatherdpd %ymm0, (%rax,%xmm1,2), %ymm2
+
+vgatherdps %xmm0, (%rax,%xmm1,2), %xmm2
+vgatherdps %ymm0, (%rax,%ymm1,2), %ymm2
+
+vgatherqpd %xmm0, (%rax,%xmm1,2), %xmm2
+vgatherqpd %ymm0, (%rax,%ymm1,2), %ymm2
+
+vgatherqps %xmm0, (%rax,%xmm1,2), %xmm2
+vgatherqps %xmm0, (%rax,%ymm1,2), %xmm2
+
+vinserti128 $1, %xmm0, %ymm1, %ymm2
+vinserti128 $1, (%rax), %ymm1, %ymm2
+
+vmovntdqa (%rax), %ymm0
+
+vmpsadbw $1, %ymm0, %ymm1, %ymm2
+vmpsadbw $1, (%rax), %ymm1, %ymm2
+
+vpabsb %ymm0, %ymm2
+vpabsb (%rax), %ymm2
+
+vpabsd %ymm0, %ymm2
+vpabsd (%rax), %ymm2
+
+vpabsw %ymm0, %ymm2
+vpabsw (%rax), %ymm2
+
+vpackssdw %ymm0, %ymm1, %ymm2
+vpackssdw (%rax), %ymm1, %ymm2
+
+vpacksswb %ymm0, %ymm1, %ymm2
+vpacksswb (%rax), %ymm1, %ymm2
+
+vpackusdw %ymm0, %ymm1, %ymm2
+vpackusdw (%rax), %ymm1, %ymm2
+
+vpackuswb %ymm0, %ymm1, %ymm2
+vpackuswb (%rax), %ymm1, %ymm2
+
+vpaddb %ymm0, %ymm1, %ymm2
+vpaddb (%rax), %ymm1, %ymm2
+
+vpaddd %ymm0, %ymm1, %ymm2
+vpaddd (%rax), %ymm1, %ymm2
+
+vpaddq %ymm0, %ymm1, %ymm2
+vpaddq (%rax), %ymm1, %ymm2
+
+vpaddsb %ymm0, %ymm1, %ymm2
+vpaddsb (%rax), %ymm1, %ymm2
+
+vpaddsw %ymm0, %ymm1, %ymm2
+vpaddsw (%rax), %ymm1, %ymm2
+
+vpaddusb %ymm0, %ymm1, %ymm2
+vpaddusb (%rax), %ymm1, %ymm2
+
+vpaddusw %ymm0, %ymm1, %ymm2
+vpaddusw (%rax), %ymm1, %ymm2
+
+vpaddw %ymm0, %ymm1, %ymm2
+vpaddw (%rax), %ymm1, %ymm2
+
+vpalignr $1, %ymm0, %ymm1, %ymm2
+vpalignr $1, (%rax), %ymm1, %ymm2
+
+vpand %ymm0, %ymm1, %ymm2
+vpand (%rax), %ymm1, %ymm2
+
+vpandn %ymm0, %ymm1, %ymm2
+vpandn (%rax), %ymm1, %ymm2
+
+vpavgb %ymm0, %ymm1, %ymm2
+vpavgb (%rax), %ymm1, %ymm2
+
+vpavgw %ymm0, %ymm1, %ymm2
+vpavgw (%rax), %ymm1, %ymm2
+
+vpblendd $11, %xmm0, %xmm1, %xmm2
+vpblendd $11, (%rax), %xmm1, %xmm2
+
+vpblendd $11, %ymm0, %ymm1, %ymm2
+vpblendd $11, (%rax), %ymm1, %ymm2
+
+vpblendvb %ymm3, %ymm0, %ymm1, %ymm2
+vpblendvb %ymm3, (%rax), %ymm1, %ymm2
+
+vpblendw $11, %ymm0, %ymm1, %ymm2
+vpblendw $11, (%rax), %ymm1, %ymm2
+
+vpbroadcastb %xmm0, %xmm0
+vpbroadcastb (%rax), %xmm0
+
+vpbroadcastb %xmm0, %ymm0
+vpbroadcastb (%rax), %ymm0
+
+vpbroadcastd %xmm0, %xmm0
+vpbroadcastd (%rax), %xmm0
+
+vpbroadcastd %xmm0, %ymm0
+vpbroadcastd (%rax), %ymm0
+
+vpbroadcastq %xmm0, %xmm0
+vpbroadcastq (%rax), %xmm0
+
+vpbroadcastq %xmm0, %ymm0
+vpbroadcastq (%rax), %ymm0
+
+vpbroadcastw %xmm0, %xmm0
+vpbroadcastw (%rax), %xmm0
+
+vpbroadcastw %xmm0, %ymm0
+vpbroadcastw (%rax), %ymm0
+
+vpcmpeqb %ymm0, %ymm1, %ymm2
+vpcmpeqb (%rax), %ymm1, %ymm2
+
+vpcmpeqd %ymm0, %ymm1, %ymm2
+vpcmpeqd (%rax), %ymm1, %ymm2
+
+vpcmpeqq %ymm0, %ymm1, %ymm2
+vpcmpeqq (%rax), %ymm1, %ymm2
+
+vpcmpeqw %ymm0, %ymm1, %ymm2
+vpcmpeqw (%rax), %ymm1, %ymm2
+
+vpcmpgtb %ymm0, %ymm1, %ymm2
+vpcmpgtb (%rax), %ymm1, %ymm2
+
+vpcmpgtd %ymm0, %ymm1, %ymm2
+vpcmpgtd (%rax), %ymm1, %ymm2
+
+vpcmpgtq %ymm0, %ymm1, %ymm2
+vpcmpgtq (%rax), %ymm1, %ymm2
+
+vpcmpgtw %ymm0, %ymm1, %ymm2
+vpcmpgtw (%rax), %ymm1, %ymm2
+
+vperm2i128 $1, %ymm0, %ymm1, %ymm2
+vperm2i128 $1, (%rax), %ymm1, %ymm2
+
+vpermd %ymm0, %ymm1, %ymm2
+vpermd (%rax), %ymm1, %ymm2
+
+vpermpd $1, %ymm0, %ymm2
+vpermpd $1, (%rax), %ymm2
+
+vpermps %ymm0, %ymm1, %ymm2
+vpermps (%rax), %ymm1, %ymm2
+
+vpermq $1, %ymm0, %ymm2
+vpermq $1, (%rax), %ymm2
+
+vpgatherdd %xmm0, (%rax,%xmm1,2), %xmm2
+vpgatherdd %ymm0, (%rax,%ymm1,2), %ymm2
+
+vpgatherdq %xmm0, (%rax,%xmm1,2), %xmm2
+vpgatherdq %ymm0, (%rax,%xmm1,2), %ymm2
+
+vpgatherqd %xmm0, (%rax,%xmm1,2), %xmm2
+vpgatherqd %xmm0, (%rax,%ymm1,2), %xmm2
+
+vpgatherqq %xmm0, (%rax,%xmm1,2), %xmm2
+vpgatherqq %ymm0, (%rax,%ymm1,2), %ymm2
+
+vphaddd %ymm0, %ymm1, %ymm2
+vphaddd (%rax), %ymm1, %ymm2
+
+vphaddsw %ymm0, %ymm1, %ymm2
+vphaddsw (%rax), %ymm1, %ymm2
+
+vphaddw %ymm0, %ymm1, %ymm2
+vphaddw (%rax), %ymm1, %ymm2
+
+vphsubd %ymm0, %ymm1, %ymm2
+vphsubd (%rax), %ymm1, %ymm2
+
+vphsubsw %ymm0, %ymm1, %ymm2
+vphsubsw (%rax), %ymm1, %ymm2
+
+vphsubw %ymm0, %ymm1, %ymm2
+vphsubw (%rax), %ymm1, %ymm2
+
+vpmaddubsw %ymm0, %ymm1, %ymm2
+vpmaddubsw (%rax), %ymm1, %ymm2
+
+vpmaddwd %ymm0, %ymm1, %ymm2
+vpmaddwd (%rax), %ymm1, %ymm2
+
+vpmaskmovd (%rax), %xmm0, %xmm2
+vpmaskmovd (%rax), %ymm0, %ymm2
+
+vpmaskmovd %xmm0, %xmm1, (%rax)
+vpmaskmovd %ymm0, %ymm1, (%rax)
+
+vpmaskmovq (%rax), %xmm0, %xmm2
+vpmaskmovq (%rax), %ymm0, %ymm2
+
+vpmaskmovq %xmm0, %xmm1, (%rax)
+vpmaskmovq %ymm0, %ymm1, (%rax)
+
+vpmaxsb %ymm0, %ymm1, %ymm2
+vpmaxsb (%rax), %ymm1, %ymm2
+
+vpmaxsd %ymm0, %ymm1, %ymm2
+vpmaxsd (%rax), %ymm1, %ymm2
+
+vpmaxsw %ymm0, %ymm1, %ymm2
+vpmaxsw (%rax), %ymm1, %ymm2
+
+vpmaxub %ymm0, %ymm1, %ymm2
+vpmaxub (%rax), %ymm1, %ymm2
+
+vpmaxud %ymm0, %ymm1, %ymm2
+vpmaxud (%rax), %ymm1, %ymm2
+
+vpmaxuw %ymm0, %ymm1, %ymm2
+vpmaxuw (%rax), %ymm1, %ymm2
+
+vpminsb %ymm0, %ymm1, %ymm2
+vpminsb (%rax), %ymm1, %ymm2
+
+vpminsd %ymm0, %ymm1, %ymm2
+vpminsd (%rax), %ymm1, %ymm2
+
+vpminsw %ymm0, %ymm1, %ymm2
+vpminsw (%rax), %ymm1, %ymm2
+
+vpminub %ymm0, %ymm1, %ymm2
+vpminub (%rax), %ymm1, %ymm2
+
+vpminud %ymm0, %ymm1, %ymm2
+vpminud (%rax), %ymm1, %ymm2
+
+vpminuw %ymm0, %ymm1, %ymm2
+vpminuw (%rax), %ymm1, %ymm2
+
+vpmovmskb %ymm0, %rcx
+
+vpmovsxbd %xmm0, %ymm2
+vpmovsxbd (%rax), %ymm2
+
+vpmovsxbq %xmm0, %ymm2
+vpmovsxbq (%rax), %ymm2
+
+vpmovsxbw %xmm0, %ymm2
+vpmovsxbw (%rax), %ymm2
+
+vpmovsxdq %xmm0, %ymm2
+vpmovsxdq (%rax), %ymm2
+
+vpmovsxwd %xmm0, %ymm2
+vpmovsxwd (%rax), %ymm2
+
+vpmovsxwq %xmm0, %ymm2
+vpmovsxwq (%rax), %ymm2
+
+vpmovzxbd %xmm0, %ymm2
+vpmovzxbd (%rax), %ymm2
+
+vpmovzxbq %xmm0, %ymm2
+vpmovzxbq (%rax), %ymm2
+
+vpmovzxbw %xmm0, %ymm2
+vpmovzxbw (%rax), %ymm2
+
+vpmovzxdq %xmm0, %ymm2
+vpmovzxdq (%rax), %ymm2
+
+vpmovzxwd %xmm0, %ymm2
+vpmovzxwd (%rax), %ymm2
+
+vpmovzxwq %xmm0, %ymm2
+vpmovzxwq (%rax), %ymm2
+
+vpmuldq %ymm0, %ymm1, %ymm2
+vpmuldq (%rax), %ymm1, %ymm2
+
+vpmulhrsw %ymm0, %ymm1, %ymm2
+vpmulhrsw (%rax), %ymm1, %ymm2
+
+vpmulhuw %ymm0, %ymm1, %ymm2
+vpmulhuw (%rax), %ymm1, %ymm2
+
+vpmulhw %ymm0, %ymm1, %ymm2
+vpmulhw (%rax), %ymm1, %ymm2
+
+vpmulld %ymm0, %ymm1, %ymm2
+vpmulld (%rax), %ymm1, %ymm2
+
+vpmullw %ymm0, %ymm1, %ymm2
+vpmullw (%rax), %ymm1, %ymm2
+
+vpmuludq %ymm0, %ymm1, %ymm2
+vpmuludq (%rax), %ymm1, %ymm2
+
+vpor %ymm0, %ymm1, %ymm2
+vpor (%rax), %ymm1, %ymm2
+
+vpsadbw %ymm0, %ymm1, %ymm2
+vpsadbw (%rax), %ymm1, %ymm2
+
+vpshufb %ymm0, %ymm1, %ymm2
+vpshufb (%rax), %ymm1, %ymm2
+
+vpshufd $1, %ymm0, %ymm2
+vpshufd $1, (%rax), %ymm2
+
+vpshufhw $1, %ymm0, %ymm2
+vpshufhw $1, (%rax), %ymm2
+
+vpshuflw $1, %ymm0, %ymm2
+vpshuflw $1, (%rax), %ymm2
+
+vpsignb %ymm0, %ymm1, %ymm2
+vpsignb (%rax), %ymm1, %ymm2
+
+vpsignd %ymm0, %ymm1, %ymm2
+vpsignd (%rax), %ymm1, %ymm2
+
+vpsignw %ymm0, %ymm1, %ymm2
+vpsignw (%rax), %ymm1, %ymm2
+
+vpslld $1, %ymm0, %ymm2
+vpslld %xmm0, %ymm1, %ymm2
+vpslld (%rax), %ymm1, %ymm2
+
+vpslldq $1, %ymm1, %ymm2
+
+vpsllq $1, %ymm0, %ymm2
+vpsllq %xmm0, %ymm1, %ymm2
+vpsllq (%rax), %ymm1, %ymm2
+
+vpsllvd %xmm0, %xmm1, %xmm2
+vpsllvd (%rax), %xmm1, %xmm2
+
+vpsllvd %ymm0, %ymm1, %ymm2
+vpsllvd (%rax), %ymm1, %ymm2
+
+vpsllvq %xmm0, %xmm1, %xmm2
+vpsllvq (%rax), %xmm1, %xmm2
+
+vpsllvq %ymm0, %ymm1, %ymm2
+vpsllvq (%rax), %ymm1, %ymm2
+
+vpsllw $1, %ymm0, %ymm2
+vpsllw %xmm0, %ymm1, %ymm2
+vpsllw (%rax), %ymm1, %ymm2
+
+vpsrad $1, %ymm0, %ymm2
+vpsrad %xmm0, %ymm1, %ymm2
+vpsrad (%rax), %ymm1, %ymm2
+
+vpsravd %xmm0, %xmm1, %xmm2
+vpsravd (%rax), %xmm1, %xmm2
+
+vpsravd %ymm0, %ymm1, %ymm2
+vpsravd (%rax), %ymm1, %ymm2
+
+vpsraw $1, %ymm0, %ymm2
+vpsraw %xmm0, %ymm1, %ymm2
+vpsraw (%rax), %ymm1, %ymm2
+
+vpsrld $1, %ymm0, %ymm2
+vpsrld %xmm0, %ymm1, %ymm2
+vpsrld (%rax), %ymm1, %ymm2
+
+vpsrldq $1, %ymm1, %ymm2
+
+vpsrlq $1, %ymm0, %ymm2
+vpsrlq %xmm0, %ymm1, %ymm2
+vpsrlq (%rax), %ymm1, %ymm2
+
+vpsrlvd %xmm0, %xmm1, %xmm2
+vpsrlvd (%rax), %xmm1, %xmm2
+
+vpsrlvd %ymm0, %ymm1, %ymm2
+vpsrlvd (%rax), %ymm1, %ymm2
+
+vpsrlvq %xmm0, %xmm1, %xmm2
+vpsrlvq (%rax), %xmm1, %xmm2
+
+vpsrlvq %ymm0, %ymm1, %ymm2
+vpsrlvq (%rax), %ymm1, %ymm2
+
+vpsrlw $1, %ymm0, %ymm2
+vpsrlw %xmm0, %ymm1, %ymm2
+vpsrlw (%rax), %ymm1, %ymm2
+
+vpsubb %ymm0, %ymm1, %ymm2
+vpsubb (%rax), %ymm1, %ymm2
+
+vpsubd %ymm0, %ymm1, %ymm2
+vpsubd (%rax), %ymm1, %ymm2
+
+vpsubq %ymm0, %ymm1, %ymm2
+vpsubq (%rax), %ymm1, %ymm2
+
+vpsubsb %ymm0, %ymm1, %ymm2
+vpsubsb (%rax), %ymm1, %ymm2
+
+vpsubsw %ymm0, %ymm1, %ymm2
+vpsubsw (%rax), %ymm1, %ymm2
+
+vpsubusb %ymm0, %ymm1, %ymm2
+vpsubusb (%rax), %ymm1, %ymm2
+
+vpsubusw %ymm0, %ymm1, %ymm2
+vpsubusw (%rax), %ymm1, %ymm2
+
+vpsubw %ymm0, %ymm1, %ymm2
+vpsubw (%rax), %ymm1, %ymm2
+
+vpunpckhbw %ymm0, %ymm1, %ymm2
+vpunpckhbw (%rax), %ymm1, %ymm2
+
+vpunpckhdq %ymm0, %ymm1, %ymm2
+vpunpckhdq (%rax), %ymm1, %ymm2
+
+vpunpckhqdq %ymm0, %ymm1, %ymm2
+vpunpckhqdq (%rax), %ymm1, %ymm2
+
+vpunpckhwd %ymm0, %ymm1, %ymm2
+vpunpckhwd (%rax), %ymm1, %ymm2
+
+vpunpcklbw %ymm0, %ymm1, %ymm2
+vpunpcklbw (%rax), %ymm1, %ymm2
+
+vpunpckldq %ymm0, %ymm1, %ymm2
+vpunpckldq (%rax), %ymm1, %ymm2
+
+vpunpcklqdq %ymm0, %ymm1, %ymm2
+vpunpcklqdq (%rax), %ymm1, %ymm2
+
+vpunpcklwd %ymm0, %ymm1, %ymm2
+vpunpcklwd (%rax), %ymm1, %ymm2
+
+vpxor %ymm0, %ymm1, %ymm2
+vpxor (%rax), %ymm1, %ymm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 8 0.50 * vbroadcasti128 (%rax), %ymm0
+# CHECK-NEXT: 1 2 1.00 vbroadcastsd %xmm0, %ymm0
+# CHECK-NEXT: 1 2 1.00 vbroadcastss %xmm0, %ymm0
+# CHECK-NEXT: 1 4 1.00 vextracti128 $1, %ymm0, %xmm2
+# CHECK-NEXT: 2 8 1.00 * vextracti128 $1, %ymm0, (%rax)
+# CHECK-NEXT: 1 5 0.33 * vgatherdpd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 1 5 0.33 * vgatherdpd %ymm0, (%rax,%xmm1,2), %ymm2
+# CHECK-NEXT: 1 5 0.33 * vgatherdps %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 1 5 0.33 * vgatherdps %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: 1 5 0.33 * vgatherqpd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 1 5 0.33 * vgatherqpd %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: 1 5 0.33 * vgatherqps %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 1 5 0.33 * vgatherqps %xmm0, (%rax,%ymm1,2), %xmm2
+# CHECK-NEXT: 1 2 1.00 vinserti128 $1, %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 9 1.00 * vinserti128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vmovntdqa (%rax), %ymm0
+# CHECK-NEXT: 3 4 2.00 vmpsadbw $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 11 2.00 * vmpsadbw $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpabsb %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpabsb (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vpabsd %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpabsd (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vpabsw %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpabsw (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vpackssdw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpackssdw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpacksswb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpacksswb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpackusdw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpackusdw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpackuswb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpackuswb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpaddb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpaddb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpaddd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpaddd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpaddq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpaddq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpaddsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpaddsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpaddsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpaddsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpaddusb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpaddusb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpaddusw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpaddusw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpaddw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpaddw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpalignr $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpalignr $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpand %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpand (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpandn %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpandn (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpavgb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpavgb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpavgw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpavgw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpblendd $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpblendd $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpblendd $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpblendd $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpblendvb %ymm3, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpblendvb %ymm3, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpblendw $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpblendw $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpbroadcastb %xmm0, %xmm0
+# CHECK-NEXT: 1 8 0.50 * vpbroadcastb (%rax), %xmm0
+# CHECK-NEXT: 1 2 1.00 vpbroadcastb %xmm0, %ymm0
+# CHECK-NEXT: 1 8 0.50 * vpbroadcastb (%rax), %ymm0
+# CHECK-NEXT: 1 1 0.50 vpbroadcastd %xmm0, %xmm0
+# CHECK-NEXT: 1 8 0.50 * vpbroadcastd (%rax), %xmm0
+# CHECK-NEXT: 1 2 1.00 vpbroadcastd %xmm0, %ymm0
+# CHECK-NEXT: 1 8 0.50 * vpbroadcastd (%rax), %ymm0
+# CHECK-NEXT: 1 1 0.50 vpbroadcastq %xmm0, %xmm0
+# CHECK-NEXT: 1 8 0.50 * vpbroadcastq (%rax), %xmm0
+# CHECK-NEXT: 1 2 1.00 vpbroadcastq %xmm0, %ymm0
+# CHECK-NEXT: 1 8 0.50 * vpbroadcastq (%rax), %ymm0
+# CHECK-NEXT: 1 1 0.50 vpbroadcastw %xmm0, %xmm0
+# CHECK-NEXT: 1 8 0.50 * vpbroadcastw (%rax), %xmm0
+# CHECK-NEXT: 1 2 1.00 vpbroadcastw %xmm0, %ymm0
+# CHECK-NEXT: 1 8 0.50 * vpbroadcastw (%rax), %ymm0
+# CHECK-NEXT: 1 1 0.25 vpcmpeqb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpcmpeqb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpcmpeqd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpcmpeqd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpcmpeqq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpcmpeqq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpcmpeqw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpcmpeqw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpcmpgtb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpcmpgtb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpcmpgtd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpcmpgtd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpcmpgtq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpcmpgtq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpcmpgtw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpcmpgtw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 1.00 vperm2i128 $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 9 1.00 * vperm2i128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 5 1.00 vpermd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 2.00 * vpermd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 6 1.00 vpermpd $1, %ymm0, %ymm2
+# CHECK-NEXT: 3 10 2.00 * vpermpd $1, (%rax), %ymm2
+# CHECK-NEXT: 2 7 1.00 vpermps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 3 11 2.00 * vpermps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 6 1.00 vpermq $1, %ymm0, %ymm2
+# CHECK-NEXT: 2 9 2.00 * vpermq $1, (%rax), %ymm2
+# CHECK-NEXT: 1 5 0.33 * vpgatherdd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 1 5 0.33 * vpgatherdd %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: 1 5 0.33 * vpgatherdq %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 1 5 0.33 * vpgatherdq %ymm0, (%rax,%xmm1,2), %ymm2
+# CHECK-NEXT: 1 5 0.33 * vpgatherqd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 1 5 0.33 * vpgatherqd %xmm0, (%rax,%ymm1,2), %xmm2
+# CHECK-NEXT: 1 5 0.33 * vpgatherqq %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 1 5 0.33 * vpgatherqq %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: 3 2 2.00 vphaddd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 9 2.00 * vphaddd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 3 2 2.00 vphaddsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 9 2.00 * vphaddsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 3 2 2.00 vphaddw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 9 2.00 * vphaddw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 3 2 2.00 vphsubd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 9 2.00 * vphsubd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 3 2 2.00 vphsubsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 9 2.00 * vphsubsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 3 2 2.00 vphsubw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 9 2.00 * vphsubw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmaddubsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmaddubsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmaddwd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmaddwd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpmaskmovd (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmaskmovd (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 18 1 6.00 * * vpmaskmovd %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 42 1 12.00 * * vpmaskmovd %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vpmaskmovq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmaskmovq (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 10 1 4.00 * * vpmaskmovq %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 18 1 6.00 * * vpmaskmovq %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: 1 1 0.25 vpmaxsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpmaxsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpmaxsd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpmaxsd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpmaxsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpmaxsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpmaxub %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpmaxub (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpmaxud %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpmaxud (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpmaxuw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpmaxuw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpminsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpminsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpminsd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpminsd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpminsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpminsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpminub %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpminub (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpminud %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpminud (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpminuw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpminuw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 1.00 vpmovmskb %ymm0, %ecx
+# CHECK-NEXT: 2 4 1.50 vpmovsxbd %xmm0, %ymm2
+# CHECK-NEXT: 1 11 1.50 * vpmovsxbd (%rax), %ymm2
+# CHECK-NEXT: 2 4 1.50 vpmovsxbq %xmm0, %ymm2
+# CHECK-NEXT: 1 11 1.50 * vpmovsxbq (%rax), %ymm2
+# CHECK-NEXT: 2 4 1.50 vpmovsxbw %xmm0, %ymm2
+# CHECK-NEXT: 1 11 1.50 * vpmovsxbw (%rax), %ymm2
+# CHECK-NEXT: 2 4 1.50 vpmovsxdq %xmm0, %ymm2
+# CHECK-NEXT: 1 11 1.50 * vpmovsxdq (%rax), %ymm2
+# CHECK-NEXT: 2 4 1.50 vpmovsxwd %xmm0, %ymm2
+# CHECK-NEXT: 1 11 1.50 * vpmovsxwd (%rax), %ymm2
+# CHECK-NEXT: 2 4 1.50 vpmovsxwq %xmm0, %ymm2
+# CHECK-NEXT: 1 11 1.50 * vpmovsxwq (%rax), %ymm2
+# CHECK-NEXT: 2 4 1.50 vpmovzxbd %xmm0, %ymm2
+# CHECK-NEXT: 1 11 1.50 * vpmovzxbd (%rax), %ymm2
+# CHECK-NEXT: 2 4 1.50 vpmovzxbq %xmm0, %ymm2
+# CHECK-NEXT: 1 11 1.50 * vpmovzxbq (%rax), %ymm2
+# CHECK-NEXT: 2 4 1.50 vpmovzxbw %xmm0, %ymm2
+# CHECK-NEXT: 1 11 1.50 * vpmovzxbw (%rax), %ymm2
+# CHECK-NEXT: 2 4 1.50 vpmovzxdq %xmm0, %ymm2
+# CHECK-NEXT: 1 11 1.50 * vpmovzxdq (%rax), %ymm2
+# CHECK-NEXT: 2 4 1.50 vpmovzxwd %xmm0, %ymm2
+# CHECK-NEXT: 1 11 1.50 * vpmovzxwd (%rax), %ymm2
+# CHECK-NEXT: 2 4 1.50 vpmovzxwq %xmm0, %ymm2
+# CHECK-NEXT: 1 11 1.50 * vpmovzxwq (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmuldq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmuldq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmulhrsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmulhrsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmulhuw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmulhuw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmulhw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmulhw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmulld %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmulld (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmullw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmullw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmuludq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmuludq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpor %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpor (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vpsadbw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpsadbw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpshufb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpshufb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpshufd $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpshufd $1, (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vpshufhw $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpshufhw $1, (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vpshuflw $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpshuflw $1, (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsignb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsignb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsignd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsignd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsignw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsignw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpslld $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpslld %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpslld (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpslldq $1, %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsllq $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsllq %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsllq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsllvd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsllvd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsllvd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsllvd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsllvq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsllvq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsllvq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsllvq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsllw $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsllw %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsllw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsrad $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsrad %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsrad (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsravd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsravd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsravd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsravd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsraw $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsraw %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsraw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsrld $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsrld %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsrld (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsrldq $1, %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsrlq $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsrlq %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsrlq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsrlvd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsrlvd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrlvd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsrlvd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsrlvq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsrlvq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrlvq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsrlvq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsrlw $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsrlw %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsrlw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpsubb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsubb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpsubd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsubd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpsubq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsubq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsubsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsubsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsubsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsubsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsubusb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsubusb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsubusw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsubusw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpsubw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsubw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhbw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpunpckhbw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhdq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpunpckhdq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhqdq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpunpckhqdq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhwd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpunpckhwd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpcklbw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpunpcklbw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpckldq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpunpckldq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpcklqdq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpunpcklqdq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpcklwd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpunpcklwd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpxor %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpxor (%rax), %ymm1, %ymm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: 6.67 6.67 6.67 - - - - - 70.75 139.25 109.75 36.25 80.50 80.50 29.00 52.33 52.33 52.33 50.67 50.67 50.67 2.50 2.50
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vbroadcasti128 (%rax), %ymm0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - - - - vbroadcastsd %xmm0, %ymm0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - - - - vbroadcastss %xmm0, %ymm0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - - - - vextracti128 $1, %ymm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vextracti128 $1, %ymm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - vgatherdpd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - vgatherdpd %ymm0, (%rax,%xmm1,2), %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - vgatherdps %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - vgatherdps %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - vgatherqpd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - vgatherqpd %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - vgatherqps %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - vgatherqps %xmm0, (%rax,%ymm1,2), %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - - - - vinserti128 $1, %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vinserti128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmovntdqa (%rax), %ymm0
+# CHECK-NEXT: - - - - - - - - 2.00 2.00 2.00 2.00 - - - - - - - - - - - vmpsadbw $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 2.00 2.00 2.00 2.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vmpsadbw $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpabsb %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpabsb (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpabsd %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpabsd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpabsw %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpabsw (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpackssdw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpackssdw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpacksswb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpacksswb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpackusdw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpackusdw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpackuswb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpackuswb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpaddb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpaddd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpaddq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpaddsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpaddsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpaddsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpaddsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpaddusb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpaddusb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpaddusw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpaddusw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpaddw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpalignr $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpalignr $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpand %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpand (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpandn %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpandn (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpavgb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpavgb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpavgw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpavgw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpblendd $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpblendd $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpblendd $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpblendd $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 - - - - - - - - - - - vpblendvb %ymm3, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpblendvb %ymm3, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpblendw $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpblendw $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpbroadcastb %xmm0, %xmm0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpbroadcastb (%rax), %xmm0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - - - - vpbroadcastb %xmm0, %ymm0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpbroadcastb (%rax), %ymm0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpbroadcastd %xmm0, %xmm0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpbroadcastd (%rax), %xmm0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - - - - vpbroadcastd %xmm0, %ymm0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpbroadcastd (%rax), %ymm0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpbroadcastq %xmm0, %xmm0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpbroadcastq (%rax), %xmm0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - - - - vpbroadcastq %xmm0, %ymm0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpbroadcastq (%rax), %ymm0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpbroadcastw %xmm0, %xmm0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpbroadcastw (%rax), %xmm0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - - - - vpbroadcastw %xmm0, %ymm0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpbroadcastw (%rax), %ymm0
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpeqb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpcmpeqb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpeqd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpcmpeqd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpcmpeqq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpcmpeqq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpeqw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpcmpeqw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpgtb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpcmpgtb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpgtd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpcmpgtd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpgtq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpcmpgtq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpgtw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpcmpgtw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - - - - vperm2i128 $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vperm2i128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - - - - vpermd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 2.00 - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpermd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - - - - vpermpd $1, %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 2.00 - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpermpd $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - - - - vpermps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 2.00 - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpermps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - - - - vpermq $1, %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 2.00 - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpermq $1, (%rax), %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpgatherdd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpgatherdd %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpgatherdq %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpgatherdq %ymm0, (%rax,%xmm1,2), %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpgatherqd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpgatherqd %xmm0, (%rax,%ymm1,2), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpgatherqq %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpgatherqq %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - - - - - vphaddd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vphaddd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - - - - - vphaddsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vphaddsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - - - - - vphaddw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vphaddw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - - - - - vphsubd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vphsubd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - - - - - vphsubsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vphsubsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - - - - - vphsubw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vphsubw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 - - - - - - - - - - - vpmaddubsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmaddubsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 - - - - - - - - - - - vpmaddwd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmaddwd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmaskmovd (%rax), %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmaskmovd (%rax), %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - 3.00 3.00 6.00 0.33 0.33 0.33 - - - 0.50 0.50 vpmaskmovd %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 6.00 6.00 12.00 0.33 0.33 0.33 - - - 0.50 0.50 vpmaskmovd %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmaskmovq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmaskmovq (%rax), %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 2.00 4.00 0.33 0.33 0.33 - - - 0.50 0.50 vpmaskmovq %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 3.00 3.00 6.00 0.33 0.33 0.33 - - - 0.50 0.50 vpmaskmovq %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmaxsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxsd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmaxsd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmaxsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxub %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmaxub (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxud %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmaxud (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxuw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmaxuw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpminsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminsd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpminsd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpminsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminub %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpminub (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminud %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpminud (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminuw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpminuw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - - - - vpmovmskb %ymm0, %ecx
+# CHECK-NEXT: - - - - - - - - - 1.50 1.50 - - - - - - - - - - - - vpmovsxbd %xmm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.50 1.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmovsxbd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.50 1.50 - - - - - - - - - - - - vpmovsxbq %xmm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.50 1.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmovsxbq (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.50 1.50 - - - - - - - - - - - - vpmovsxbw %xmm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.50 1.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmovsxbw (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.50 1.50 - - - - - - - - - - - - vpmovsxdq %xmm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.50 1.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmovsxdq (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.50 1.50 - - - - - - - - - - - - vpmovsxwd %xmm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.50 1.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmovsxwd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.50 1.50 - - - - - - - - - - - - vpmovsxwq %xmm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.50 1.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmovsxwq (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.50 1.50 - - - - - - - - - - - - vpmovzxbd %xmm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.50 1.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmovzxbd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.50 1.50 - - - - - - - - - - - - vpmovzxbq %xmm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.50 1.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmovzxbq (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.50 1.50 - - - - - - - - - - - - vpmovzxbw %xmm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.50 1.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmovzxbw (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.50 1.50 - - - - - - - - - - - - vpmovzxdq %xmm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.50 1.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmovzxdq (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.50 1.50 - - - - - - - - - - - - vpmovzxwd %xmm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.50 1.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmovzxwd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.50 1.50 - - - - - - - - - - - - vpmovzxwq %xmm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.50 1.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmovzxwq (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 - - - - - - - - - - - vpmuldq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmuldq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 - - - - - - - - - - - vpmulhrsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmulhrsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 - - - - - - - - - - - vpmulhuw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmulhuw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 - - - - - - - - - - - vpmulhw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmulhw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 - - - - - - - - - - - vpmulld %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmulld (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 - - - - - - - - - - - vpmullw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmullw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 - - - - - - - - - - - vpmuludq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpmuludq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpor %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpor (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsadbw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsadbw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpshufb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpshufb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpshufd $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpshufd $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpshufhw $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpshufhw $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpshuflw $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpshuflw $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpsignb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsignb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpsignd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsignd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpsignw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsignw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpslld $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpslld %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpslld (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpslldq $1, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsllq $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsllq %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsllq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsllvd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsllvd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsllvd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsllvd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsllvq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsllvq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsllvq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsllvq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsllw $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsllw %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsllw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsrad $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsrad %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsrad (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsravd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsravd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsravd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsravd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsraw $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsraw %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsraw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsrld $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsrld %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsrld (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsrldq $1, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsrlq $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsrlq %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsrlq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsrlvd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsrlvd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsrlvd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsrlvd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsrlvq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsrlvq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsrlvq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsrlvq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsrlw $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpsrlw %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsrlw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsubb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsubd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsubq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpsubsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsubsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpsubsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsubsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpsubusb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsubusb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpsubusw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsubusw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpsubw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpunpckhbw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpunpckhbw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpunpckhdq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpunpckhdq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpunpckhqdq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpunpckhqdq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpunpckhwd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpunpckhwd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpunpcklbw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpunpcklbw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpunpckldq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpunpckldq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpunpcklqdq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpunpcklqdq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - vpunpcklwd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpunpcklwd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpxor %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpxor (%rax), %ymm1, %ymm2
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-bmi1.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-bmi1.s
new file mode 100644
index 0000000000000..8c0e84135750e
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-bmi1.s
@@ -0,0 +1,135 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+andn %eax, %ebx, %ecx
+andn (%rax), %ebx, %ecx
+
+andn %rax, %rbx, %rcx
+andn (%rax), %rbx, %rcx
+
+bextr %eax, %ebx, %ecx
+bextr %eax, (%rbx), %ecx
+
+bextr %rax, %rbx, %rcx
+bextr %rax, (%rbx), %rcx
+
+blsi %eax, %ecx
+blsi (%rax), %ecx
+
+blsi %rax, %rcx
+blsi (%rax), %rcx
+
+blsmsk %eax, %ecx
+blsmsk (%rax), %ecx
+
+blsmsk %rax, %rcx
+blsmsk (%rax), %rcx
+
+blsr %eax, %ecx
+blsr (%rax), %ecx
+
+blsr %rax, %rcx
+blsr (%rax), %rcx
+
+tzcnt %ax, %cx
+tzcnt (%rax), %cx
+
+tzcnt %eax, %ecx
+tzcnt (%rax), %ecx
+
+tzcnt %rax, %rcx
+tzcnt (%rax), %rcx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.25 andnl %eax, %ebx, %ecx
+# CHECK-NEXT: 1 5 0.33 * andnl (%rax), %ebx, %ecx
+# CHECK-NEXT: 1 1 0.25 andnq %rax, %rbx, %rcx
+# CHECK-NEXT: 1 5 0.33 * andnq (%rax), %rbx, %rcx
+# CHECK-NEXT: 1 1 0.50 bextrl %eax, %ebx, %ecx
+# CHECK-NEXT: 2 5 0.50 * bextrl %eax, (%rbx), %ecx
+# CHECK-NEXT: 1 1 0.50 bextrq %rax, %rbx, %rcx
+# CHECK-NEXT: 2 5 0.50 * bextrq %rax, (%rbx), %rcx
+# CHECK-NEXT: 2 2 0.50 blsil %eax, %ecx
+# CHECK-NEXT: 3 6 0.50 * blsil (%rax), %ecx
+# CHECK-NEXT: 2 2 0.50 blsiq %rax, %rcx
+# CHECK-NEXT: 3 6 0.50 * blsiq (%rax), %rcx
+# CHECK-NEXT: 2 2 0.50 blsmskl %eax, %ecx
+# CHECK-NEXT: 3 6 0.50 * blsmskl (%rax), %ecx
+# CHECK-NEXT: 2 2 0.50 blsmskq %rax, %rcx
+# CHECK-NEXT: 3 6 0.50 * blsmskq (%rax), %rcx
+# CHECK-NEXT: 2 2 0.50 blsrl %eax, %ecx
+# CHECK-NEXT: 3 6 0.50 * blsrl (%rax), %ecx
+# CHECK-NEXT: 2 2 0.50 blsrq %rax, %rcx
+# CHECK-NEXT: 3 6 0.50 * blsrq (%rax), %rcx
+# CHECK-NEXT: 2 2 1.00 tzcntw %ax, %cx
+# CHECK-NEXT: 2 6 0.50 * tzcntw (%rax), %cx
+# CHECK-NEXT: 2 2 0.50 tzcntl %eax, %ecx
+# CHECK-NEXT: 2 6 0.50 * tzcntl (%rax), %ecx
+# CHECK-NEXT: 2 2 0.50 tzcntq %rax, %rcx
+# CHECK-NEXT: 2 6 0.50 * tzcntq (%rax), %rcx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: 4.33 4.33 4.33 8.00 12.50 12.50 8.00 - - - - - - - - 4.33 4.33 4.33 4.33 4.33 4.33 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - andnl %eax, %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - andnl (%rax), %ebx, %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - andnq %rax, %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - andnq (%rax), %rbx, %rcx
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - bextrl %eax, %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - 0.50 0.50 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - bextrl %eax, (%rbx), %ecx
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - bextrq %rax, %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - 0.50 0.50 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - bextrq %rax, (%rbx), %rcx
+# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - - - blsil %eax, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - blsil (%rax), %ecx
+# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - - - blsiq %rax, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - blsiq (%rax), %rcx
+# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - - - blsmskl %eax, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - blsmskl (%rax), %ecx
+# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - - - blsmskq %rax, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - blsmskq (%rax), %rcx
+# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - - - blsrl %eax, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - blsrl (%rax), %ecx
+# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - - - blsrq %rax, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - blsrq (%rax), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - tzcntw %ax, %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - 0.50 0.50 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - tzcntw (%rax), %cx
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - tzcntl %eax, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - 0.50 0.50 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - tzcntl (%rax), %ecx
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - tzcntq %rax, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - 0.50 0.50 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - tzcntq (%rax), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-bmi2.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-bmi2.s
new file mode 100644
index 0000000000000..5a92920952b3b
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-bmi2.s
@@ -0,0 +1,156 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+bzhi %eax, %ebx, %ecx
+bzhi %eax, (%rbx), %ecx
+
+bzhi %rax, %rbx, %rcx
+bzhi %rax, (%rbx), %rcx
+
+mulx %eax, %ebx, %ecx
+mulx (%rax), %ebx, %ecx
+
+mulx %rax, %rbx, %rcx
+mulx (%rax), %rbx, %rcx
+
+pdep %eax, %ebx, %ecx
+pdep (%rax), %ebx, %ecx
+
+pdep %rax, %rbx, %rcx
+pdep (%rax), %rbx, %rcx
+
+pext %eax, %ebx, %ecx
+pext (%rax), %ebx, %ecx
+
+pext %rax, %rbx, %rcx
+pext (%rax), %rbx, %rcx
+
+rorx $1, %eax, %ecx
+rorx $1, (%rax), %ecx
+
+rorx $1, %rax, %rcx
+rorx $1, (%rax), %rcx
+
+sarx %eax, %ebx, %ecx
+sarx %eax, (%rbx), %ecx
+
+sarx %rax, %rbx, %rcx
+sarx %rax, (%rbx), %rcx
+
+shlx %eax, %ebx, %ecx
+shlx %eax, (%rbx), %ecx
+
+shlx %rax, %rbx, %rcx
+shlx %rax, (%rbx), %rcx
+
+shrx %eax, %ebx, %ecx
+shrx %eax, (%rbx), %ecx
+
+shrx %rax, %rbx, %rcx
+shrx %rax, (%rbx), %rcx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.50 bzhil %eax, %ebx, %ecx
+# CHECK-NEXT: 2 5 0.50 * bzhil %eax, (%rbx), %ecx
+# CHECK-NEXT: 1 1 0.50 bzhiq %rax, %rbx, %rcx
+# CHECK-NEXT: 2 5 0.50 * bzhiq %rax, (%rbx), %rcx
+# CHECK-NEXT: 2 3 1.00 mulxl %eax, %ebx, %ecx
+# CHECK-NEXT: 2 7 2.00 * mulxl (%rax), %ebx, %ecx
+# CHECK-NEXT: 2 4 1.00 mulxq %rax, %rbx, %rcx
+# CHECK-NEXT: 2 8 2.00 * mulxq (%rax), %rbx, %rcx
+# CHECK-NEXT: 1 3 1.00 pdepl %eax, %ebx, %ecx
+# CHECK-NEXT: 1 5 0.33 * pdepl (%rax), %ebx, %ecx
+# CHECK-NEXT: 1 3 1.00 pdepq %rax, %rbx, %rcx
+# CHECK-NEXT: 1 5 0.33 * pdepq (%rax), %rbx, %rcx
+# CHECK-NEXT: 1 3 1.00 pextl %eax, %ebx, %ecx
+# CHECK-NEXT: 1 5 0.33 * pextl (%rax), %ebx, %ecx
+# CHECK-NEXT: 1 3 1.00 pextq %rax, %rbx, %rcx
+# CHECK-NEXT: 1 5 0.33 * pextq (%rax), %rbx, %rcx
+# CHECK-NEXT: 1 1 0.50 rorxl $1, %eax, %ecx
+# CHECK-NEXT: 2 5 0.50 * rorxl $1, (%rax), %ecx
+# CHECK-NEXT: 1 1 0.50 rorxq $1, %rax, %rcx
+# CHECK-NEXT: 2 5 0.50 * rorxq $1, (%rax), %rcx
+# CHECK-NEXT: 1 1 0.50 sarxl %eax, %ebx, %ecx
+# CHECK-NEXT: 2 5 0.50 * sarxl %eax, (%rbx), %ecx
+# CHECK-NEXT: 1 1 0.50 sarxq %rax, %rbx, %rcx
+# CHECK-NEXT: 2 5 0.50 * sarxq %rax, (%rbx), %rcx
+# CHECK-NEXT: 1 1 0.50 shlxl %eax, %ebx, %ecx
+# CHECK-NEXT: 2 5 0.50 * shlxl %eax, (%rbx), %ecx
+# CHECK-NEXT: 1 1 0.50 shlxq %rax, %rbx, %rcx
+# CHECK-NEXT: 2 5 0.50 * shlxq %rax, (%rbx), %rcx
+# CHECK-NEXT: 1 1 0.50 shrxl %eax, %ebx, %ecx
+# CHECK-NEXT: 2 5 0.50 * shrxl %eax, (%rbx), %ecx
+# CHECK-NEXT: 1 1 0.50 shrxq %rax, %rbx, %rcx
+# CHECK-NEXT: 2 5 0.50 * shrxq %rax, (%rbx), %rcx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: 5.33 5.33 5.33 1.00 21.00 11.00 1.00 - - - - - - - - 5.33 5.33 5.33 5.33 5.33 5.33 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - bzhil %eax, %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - 0.50 0.50 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - bzhil %eax, (%rbx), %ecx
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - bzhiq %rax, %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - 0.50 0.50 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - bzhiq %rax, (%rbx), %rcx
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - - - - mulxl %eax, %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - 2.00 - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - mulxl (%rax), %ebx, %ecx
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - - - - mulxq %rax, %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - 2.00 - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - mulxq (%rax), %rbx, %rcx
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - - - - pdepl %eax, %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - pdepl (%rax), %ebx, %ecx
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - - - - pdepq %rax, %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - pdepq (%rax), %rbx, %rcx
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - - - - pextl %eax, %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - pextl (%rax), %ebx, %ecx
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - - - - pextq %rax, %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - pextq (%rax), %rbx, %rcx
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - rorxl $1, %eax, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - 0.50 0.50 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - rorxl $1, (%rax), %ecx
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - rorxq $1, %rax, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - 0.50 0.50 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - rorxq $1, (%rax), %rcx
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - sarxl %eax, %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - 0.50 0.50 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - sarxl %eax, (%rbx), %ecx
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - sarxq %rax, %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - 0.50 0.50 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - sarxq %rax, (%rbx), %rcx
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - shlxl %eax, %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - 0.50 0.50 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - shlxl %eax, (%rbx), %ecx
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - shlxq %rax, %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - 0.50 0.50 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - shlxq %rax, (%rbx), %rcx
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - shrxl %eax, %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - 0.50 0.50 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - shrxl %eax, (%rbx), %ecx
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - shrxq %rax, %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - 0.50 0.50 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - shrxq %rax, (%rbx), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-clflushopt.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-clflushopt.s
new file mode 100644
index 0000000000000..3e7219c9c6d0f
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-clflushopt.s
@@ -0,0 +1,48 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+clflushopt (%rax)
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 5 0.33 * * U clflushopt (%rax)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - clflushopt (%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-clzero.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-clzero.s
new file mode 100644
index 0000000000000..0dc89faad77c4
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-clzero.s
@@ -0,0 +1,48 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+clzero
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 5 0.33 U clzero
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - clzero
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-cmov.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-cmov.s
new file mode 100644
index 0000000000000..e0e46afd0c0b4
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-cmov.s
@@ -0,0 +1,338 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+cmovow %si, %di
+cmovnow %si, %di
+cmovbw %si, %di
+cmovaew %si, %di
+cmovew %si, %di
+cmovnew %si, %di
+cmovbew %si, %di
+cmovaw %si, %di
+cmovsw %si, %di
+cmovnsw %si, %di
+cmovpw %si, %di
+cmovnpw %si, %di
+cmovlw %si, %di
+cmovgew %si, %di
+cmovlew %si, %di
+cmovgw %si, %di
+
+cmovow (%rax), %di
+cmovnow (%rax), %di
+cmovbw (%rax), %di
+cmovaew (%rax), %di
+cmovew (%rax), %di
+cmovnew (%rax), %di
+cmovbew (%rax), %di
+cmovaw (%rax), %di
+cmovsw (%rax), %di
+cmovnsw (%rax), %di
+cmovpw (%rax), %di
+cmovnpw (%rax), %di
+cmovlw (%rax), %di
+cmovgew (%rax), %di
+cmovlew (%rax), %di
+cmovgw (%rax), %di
+
+cmovol %esi, %edi
+cmovnol %esi, %edi
+cmovbl %esi, %edi
+cmovael %esi, %edi
+cmovel %esi, %edi
+cmovnel %esi, %edi
+cmovbel %esi, %edi
+cmoval %esi, %edi
+cmovsl %esi, %edi
+cmovnsl %esi, %edi
+cmovpl %esi, %edi
+cmovnpl %esi, %edi
+cmovll %esi, %edi
+cmovgel %esi, %edi
+cmovlel %esi, %edi
+cmovgl %esi, %edi
+
+cmovol (%rax), %edi
+cmovnol (%rax), %edi
+cmovbl (%rax), %edi
+cmovael (%rax), %edi
+cmovel (%rax), %edi
+cmovnel (%rax), %edi
+cmovbel (%rax), %edi
+cmoval (%rax), %edi
+cmovsl (%rax), %edi
+cmovnsl (%rax), %edi
+cmovpl (%rax), %edi
+cmovnpl (%rax), %edi
+cmovll (%rax), %edi
+cmovgel (%rax), %edi
+cmovlel (%rax), %edi
+cmovgl (%rax), %edi
+
+cmovoq %rsi, %rdi
+cmovnoq %rsi, %rdi
+cmovbq %rsi, %rdi
+cmovaeq %rsi, %rdi
+cmoveq %rsi, %rdi
+cmovneq %rsi, %rdi
+cmovbeq %rsi, %rdi
+cmovaq %rsi, %rdi
+cmovsq %rsi, %rdi
+cmovnsq %rsi, %rdi
+cmovpq %rsi, %rdi
+cmovnpq %rsi, %rdi
+cmovlq %rsi, %rdi
+cmovgeq %rsi, %rdi
+cmovleq %rsi, %rdi
+cmovgq %rsi, %rdi
+
+cmovoq (%rax), %rdi
+cmovnoq (%rax), %rdi
+cmovbq (%rax), %rdi
+cmovaeq (%rax), %rdi
+cmoveq (%rax), %rdi
+cmovneq (%rax), %rdi
+cmovbeq (%rax), %rdi
+cmovaq (%rax), %rdi
+cmovsq (%rax), %rdi
+cmovnsq (%rax), %rdi
+cmovpq (%rax), %rdi
+cmovnpq (%rax), %rdi
+cmovlq (%rax), %rdi
+cmovgeq (%rax), %rdi
+cmovleq (%rax), %rdi
+cmovgq (%rax), %rdi
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.50 cmovow %si, %di
+# CHECK-NEXT: 1 1 0.50 cmovnow %si, %di
+# CHECK-NEXT: 1 1 0.50 cmovbw %si, %di
+# CHECK-NEXT: 1 1 0.50 cmovaew %si, %di
+# CHECK-NEXT: 1 1 0.50 cmovew %si, %di
+# CHECK-NEXT: 1 1 0.50 cmovnew %si, %di
+# CHECK-NEXT: 1 1 0.50 cmovbew %si, %di
+# CHECK-NEXT: 1 1 0.50 cmovaw %si, %di
+# CHECK-NEXT: 1 1 0.50 cmovsw %si, %di
+# CHECK-NEXT: 1 1 0.50 cmovnsw %si, %di
+# CHECK-NEXT: 1 1 0.50 cmovpw %si, %di
+# CHECK-NEXT: 1 1 0.50 cmovnpw %si, %di
+# CHECK-NEXT: 1 1 0.50 cmovlw %si, %di
+# CHECK-NEXT: 1 1 0.50 cmovgew %si, %di
+# CHECK-NEXT: 1 1 0.50 cmovlew %si, %di
+# CHECK-NEXT: 1 1 0.50 cmovgw %si, %di
+# CHECK-NEXT: 1 5 0.50 * cmovow (%rax), %di
+# CHECK-NEXT: 1 5 0.50 * cmovnow (%rax), %di
+# CHECK-NEXT: 1 5 0.50 * cmovbw (%rax), %di
+# CHECK-NEXT: 1 5 0.50 * cmovaew (%rax), %di
+# CHECK-NEXT: 1 5 0.50 * cmovew (%rax), %di
+# CHECK-NEXT: 1 5 0.50 * cmovnew (%rax), %di
+# CHECK-NEXT: 1 5 0.50 * cmovbew (%rax), %di
+# CHECK-NEXT: 1 5 0.50 * cmovaw (%rax), %di
+# CHECK-NEXT: 1 5 0.50 * cmovsw (%rax), %di
+# CHECK-NEXT: 1 5 0.50 * cmovnsw (%rax), %di
+# CHECK-NEXT: 1 5 0.50 * cmovpw (%rax), %di
+# CHECK-NEXT: 1 5 0.50 * cmovnpw (%rax), %di
+# CHECK-NEXT: 1 5 0.50 * cmovlw (%rax), %di
+# CHECK-NEXT: 1 5 0.50 * cmovgew (%rax), %di
+# CHECK-NEXT: 1 5 0.50 * cmovlew (%rax), %di
+# CHECK-NEXT: 1 5 0.50 * cmovgw (%rax), %di
+# CHECK-NEXT: 1 1 0.50 cmovol %esi, %edi
+# CHECK-NEXT: 1 1 0.50 cmovnol %esi, %edi
+# CHECK-NEXT: 1 1 0.50 cmovbl %esi, %edi
+# CHECK-NEXT: 1 1 0.50 cmovael %esi, %edi
+# CHECK-NEXT: 1 1 0.50 cmovel %esi, %edi
+# CHECK-NEXT: 1 1 0.50 cmovnel %esi, %edi
+# CHECK-NEXT: 1 1 0.50 cmovbel %esi, %edi
+# CHECK-NEXT: 1 1 0.50 cmoval %esi, %edi
+# CHECK-NEXT: 1 1 0.50 cmovsl %esi, %edi
+# CHECK-NEXT: 1 1 0.50 cmovnsl %esi, %edi
+# CHECK-NEXT: 1 1 0.50 cmovpl %esi, %edi
+# CHECK-NEXT: 1 1 0.50 cmovnpl %esi, %edi
+# CHECK-NEXT: 1 1 0.50 cmovll %esi, %edi
+# CHECK-NEXT: 1 1 0.50 cmovgel %esi, %edi
+# CHECK-NEXT: 1 1 0.50 cmovlel %esi, %edi
+# CHECK-NEXT: 1 1 0.50 cmovgl %esi, %edi
+# CHECK-NEXT: 1 5 0.50 * cmovol (%rax), %edi
+# CHECK-NEXT: 1 5 0.50 * cmovnol (%rax), %edi
+# CHECK-NEXT: 1 5 0.50 * cmovbl (%rax), %edi
+# CHECK-NEXT: 1 5 0.50 * cmovael (%rax), %edi
+# CHECK-NEXT: 1 5 0.50 * cmovel (%rax), %edi
+# CHECK-NEXT: 1 5 0.50 * cmovnel (%rax), %edi
+# CHECK-NEXT: 1 5 0.50 * cmovbel (%rax), %edi
+# CHECK-NEXT: 1 5 0.50 * cmoval (%rax), %edi
+# CHECK-NEXT: 1 5 0.50 * cmovsl (%rax), %edi
+# CHECK-NEXT: 1 5 0.50 * cmovnsl (%rax), %edi
+# CHECK-NEXT: 1 5 0.50 * cmovpl (%rax), %edi
+# CHECK-NEXT: 1 5 0.50 * cmovnpl (%rax), %edi
+# CHECK-NEXT: 1 5 0.50 * cmovll (%rax), %edi
+# CHECK-NEXT: 1 5 0.50 * cmovgel (%rax), %edi
+# CHECK-NEXT: 1 5 0.50 * cmovlel (%rax), %edi
+# CHECK-NEXT: 1 5 0.50 * cmovgl (%rax), %edi
+# CHECK-NEXT: 1 1 0.50 cmovoq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.50 cmovnoq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.50 cmovbq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.50 cmovaeq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.50 cmoveq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.50 cmovneq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.50 cmovbeq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.50 cmovaq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.50 cmovsq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.50 cmovnsq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.50 cmovpq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.50 cmovnpq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.50 cmovlq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.50 cmovgeq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.50 cmovleq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.50 cmovgq %rsi, %rdi
+# CHECK-NEXT: 1 5 0.50 * cmovoq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.50 * cmovnoq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.50 * cmovbq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.50 * cmovaeq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.50 * cmoveq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.50 * cmovneq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.50 * cmovbeq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.50 * cmovaq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.50 * cmovsq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.50 * cmovnsq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.50 * cmovpq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.50 * cmovnpq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.50 * cmovlq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.50 * cmovgeq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.50 * cmovleq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.50 * cmovgq (%rax), %rdi
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: 16.00 16.00 16.00 48.00 - - 48.00 - - - - - - - - 16.00 16.00 16.00 16.00 16.00 16.00 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovow %si, %di
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovnow %si, %di
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovbw %si, %di
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovaew %si, %di
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovew %si, %di
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovnew %si, %di
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovbew %si, %di
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovaw %si, %di
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovsw %si, %di
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovnsw %si, %di
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovpw %si, %di
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovnpw %si, %di
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovlw %si, %di
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovgew %si, %di
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovlew %si, %di
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovgw %si, %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovow (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovnow (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovbw (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovaew (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovew (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovnew (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovbew (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovaw (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovsw (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovnsw (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovpw (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovnpw (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovlw (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovgew (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovlew (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovgw (%rax), %di
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovol %esi, %edi
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovnol %esi, %edi
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovbl %esi, %edi
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovael %esi, %edi
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovel %esi, %edi
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovnel %esi, %edi
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovbel %esi, %edi
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmoval %esi, %edi
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovsl %esi, %edi
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovnsl %esi, %edi
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovpl %esi, %edi
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovnpl %esi, %edi
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovll %esi, %edi
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovgel %esi, %edi
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovlel %esi, %edi
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovgl %esi, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovol (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovnol (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovbl (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovael (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovel (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovnel (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovbel (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmoval (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovsl (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovnsl (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovpl (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovnpl (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovll (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovgel (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovlel (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovgl (%rax), %edi
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovoq %rsi, %rdi
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovnoq %rsi, %rdi
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovbq %rsi, %rdi
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovaeq %rsi, %rdi
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmoveq %rsi, %rdi
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovneq %rsi, %rdi
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovbeq %rsi, %rdi
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovaq %rsi, %rdi
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovsq %rsi, %rdi
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovnsq %rsi, %rdi
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovpq %rsi, %rdi
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovnpq %rsi, %rdi
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovlq %rsi, %rdi
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovgeq %rsi, %rdi
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovleq %rsi, %rdi
+# CHECK-NEXT: - - - 0.50 - - 0.50 - - - - - - - - - - - - - - - - cmovgq %rsi, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovoq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovnoq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovbq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovaeq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmoveq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovneq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovbeq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovaq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovsq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovnsq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovpq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovnpq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovlq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovgeq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovleq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 - - 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmovgq (%rax), %rdi
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-cmpxchg.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-cmpxchg.s
new file mode 100644
index 0000000000000..03763e5a2bfe7
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-cmpxchg.s
@@ -0,0 +1,51 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+cmpxchg8b (%rax)
+cmpxchg16b (%rax)
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 19 3 6.00 * * cmpxchg8b (%rax)
+# CHECK-NEXT: 28 4 14.75 * * cmpxchg16b (%rax)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: - - - 20.75 20.75 20.75 20.75 - - - - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - 6.00 6.00 6.00 6.00 - - - - - - - - - - - - - - - - cmpxchg8b (%rax)
+# CHECK-NEXT: - - - 14.75 14.75 14.75 14.75 - - - - - - - - - - - - - - - - cmpxchg16b (%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-f16c.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-f16c.s
new file mode 100644
index 0000000000000..bb995d588c43c
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-f16c.s
@@ -0,0 +1,72 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+vcvtph2ps %xmm0, %xmm2
+vcvtph2ps (%rax), %xmm2
+
+vcvtph2ps %xmm0, %ymm2
+vcvtph2ps (%rax), %ymm2
+
+vcvtps2ph $0, %xmm0, %xmm2
+vcvtps2ph $0, %xmm0, (%rax)
+
+vcvtps2ph $0, %ymm0, %xmm2
+vcvtps2ph $0, %ymm0, (%rax)
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 vcvtph2ps %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vcvtph2ps (%rax), %xmm2
+# CHECK-NEXT: 2 4 1.00 vcvtph2ps %xmm0, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vcvtph2ps (%rax), %ymm2
+# CHECK-NEXT: 1 3 1.00 vcvtps2ph $0, %xmm0, %xmm2
+# CHECK-NEXT: 2 4 1.00 * vcvtps2ph $0, %xmm0, (%rax)
+# CHECK-NEXT: 2 6 1.00 vcvtps2ph $0, %ymm0, %xmm2
+# CHECK-NEXT: 3 7 1.00 * vcvtps2ph $0, %ymm0, (%rax)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: - - - - - - - - - - 6.50 6.50 2.00 2.00 2.00 1.33 1.33 1.33 0.67 0.67 0.67 1.00 1.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - vcvtph2ps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcvtph2ps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - vcvtph2ps %xmm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vcvtph2ps (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - vcvtps2ph $0, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vcvtps2ph $0, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - vcvtps2ph $0, %ymm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 vcvtps2ph $0, %ymm0, (%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-fma.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-fma.s
new file mode 100644
index 0000000000000..a1cbac28bea46
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-fma.s
@@ -0,0 +1,716 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+vfmadd132pd %xmm0, %xmm1, %xmm2
+vfmadd132pd (%rax), %xmm1, %xmm2
+
+vfmadd132pd %ymm0, %ymm1, %ymm2
+vfmadd132pd (%rax), %ymm1, %ymm2
+
+vfmadd213pd %xmm0, %xmm1, %xmm2
+vfmadd213pd (%rax), %xmm1, %xmm2
+
+vfmadd213pd %ymm0, %ymm1, %ymm2
+vfmadd213pd (%rax), %ymm1, %ymm2
+
+vfmadd231pd %xmm0, %xmm1, %xmm2
+vfmadd231pd (%rax), %xmm1, %xmm2
+
+vfmadd231pd %ymm0, %ymm1, %ymm2
+vfmadd231pd (%rax), %ymm1, %ymm2
+
+vfmadd132ps %xmm0, %xmm1, %xmm2
+vfmadd132ps (%rax), %xmm1, %xmm2
+
+vfmadd132ps %ymm0, %ymm1, %ymm2
+vfmadd132ps (%rax), %ymm1, %ymm2
+
+vfmadd213ps %xmm0, %xmm1, %xmm2
+vfmadd213ps (%rax), %xmm1, %xmm2
+
+vfmadd213ps %ymm0, %ymm1, %ymm2
+vfmadd213ps (%rax), %ymm1, %ymm2
+
+vfmadd231ps %xmm0, %xmm1, %xmm2
+vfmadd231ps (%rax), %xmm1, %xmm2
+
+vfmadd231ps %ymm0, %ymm1, %ymm2
+vfmadd231ps (%rax), %ymm1, %ymm2
+
+vfmadd132sd %xmm0, %xmm1, %xmm2
+vfmadd132sd (%rax), %xmm1, %xmm2
+
+vfmadd213sd %xmm0, %xmm1, %xmm2
+vfmadd213sd (%rax), %xmm1, %xmm2
+
+vfmadd231sd %xmm0, %xmm1, %xmm2
+vfmadd231sd (%rax), %xmm1, %xmm2
+
+vfmadd132ss %xmm0, %xmm1, %xmm2
+vfmadd132ss (%rax), %xmm1, %xmm2
+
+vfmadd213ss %xmm0, %xmm1, %xmm2
+vfmadd213ss (%rax), %xmm1, %xmm2
+
+vfmadd231ss %xmm0, %xmm1, %xmm2
+vfmadd231ss (%rax), %xmm1, %xmm2
+
+vfmaddsub132pd %xmm0, %xmm1, %xmm2
+vfmaddsub132pd (%rax), %xmm1, %xmm2
+
+vfmaddsub132pd %ymm0, %ymm1, %ymm2
+vfmaddsub132pd (%rax), %ymm1, %ymm2
+
+vfmaddsub213pd %xmm0, %xmm1, %xmm2
+vfmaddsub213pd (%rax), %xmm1, %xmm2
+
+vfmaddsub213pd %ymm0, %ymm1, %ymm2
+vfmaddsub213pd (%rax), %ymm1, %ymm2
+
+vfmaddsub231pd %xmm0, %xmm1, %xmm2
+vfmaddsub231pd (%rax), %xmm1, %xmm2
+
+vfmaddsub231pd %ymm0, %ymm1, %ymm2
+vfmaddsub231pd (%rax), %ymm1, %ymm2
+
+vfmaddsub132ps %xmm0, %xmm1, %xmm2
+vfmaddsub132ps (%rax), %xmm1, %xmm2
+
+vfmaddsub132ps %ymm0, %ymm1, %ymm2
+vfmaddsub132ps (%rax), %ymm1, %ymm2
+
+vfmaddsub213ps %xmm0, %xmm1, %xmm2
+vfmaddsub213ps (%rax), %xmm1, %xmm2
+
+vfmaddsub213ps %ymm0, %ymm1, %ymm2
+vfmaddsub213ps (%rax), %ymm1, %ymm2
+
+vfmaddsub231ps %xmm0, %xmm1, %xmm2
+vfmaddsub231ps (%rax), %xmm1, %xmm2
+
+vfmaddsub231ps %ymm0, %ymm1, %ymm2
+vfmaddsub231ps (%rax), %ymm1, %ymm2
+
+vfmsub132pd %xmm0, %xmm1, %xmm2
+vfmsub132pd (%rax), %xmm1, %xmm2
+
+vfmsub132pd %ymm0, %ymm1, %ymm2
+vfmsub132pd (%rax), %ymm1, %ymm2
+
+vfmsub213pd %xmm0, %xmm1, %xmm2
+vfmsub213pd (%rax), %xmm1, %xmm2
+
+vfmsub213pd %ymm0, %ymm1, %ymm2
+vfmsub213pd (%rax), %ymm1, %ymm2
+
+vfmsub231pd %xmm0, %xmm1, %xmm2
+vfmsub231pd (%rax), %xmm1, %xmm2
+
+vfmsub231pd %ymm0, %ymm1, %ymm2
+vfmsub231pd (%rax), %ymm1, %ymm2
+
+vfmsub132ps %xmm0, %xmm1, %xmm2
+vfmsub132ps (%rax), %xmm1, %xmm2
+
+vfmsub132ps %ymm0, %ymm1, %ymm2
+vfmsub132ps (%rax), %ymm1, %ymm2
+
+vfmsub213ps %xmm0, %xmm1, %xmm2
+vfmsub213ps (%rax), %xmm1, %xmm2
+
+vfmsub213ps %ymm0, %ymm1, %ymm2
+vfmsub213ps (%rax), %ymm1, %ymm2
+
+vfmsub231ps %xmm0, %xmm1, %xmm2
+vfmsub231ps (%rax), %xmm1, %xmm2
+
+vfmsub231ps %ymm0, %ymm1, %ymm2
+vfmsub231ps (%rax), %ymm1, %ymm2
+
+vfmsub132sd %xmm0, %xmm1, %xmm2
+vfmsub132sd (%rax), %xmm1, %xmm2
+
+vfmsub213sd %xmm0, %xmm1, %xmm2
+vfmsub213sd (%rax), %xmm1, %xmm2
+
+vfmsub231sd %xmm0, %xmm1, %xmm2
+vfmsub231sd (%rax), %xmm1, %xmm2
+
+vfmsub132ss %xmm0, %xmm1, %xmm2
+vfmsub132ss (%rax), %xmm1, %xmm2
+
+vfmsub213ss %xmm0, %xmm1, %xmm2
+vfmsub213ss (%rax), %xmm1, %xmm2
+
+vfmsub231ss %xmm0, %xmm1, %xmm2
+vfmsub231ss (%rax), %xmm1, %xmm2
+
+vfmsubadd132pd %xmm0, %xmm1, %xmm2
+vfmsubadd132pd (%rax), %xmm1, %xmm2
+
+vfmsubadd132pd %ymm0, %ymm1, %ymm2
+vfmsubadd132pd (%rax), %ymm1, %ymm2
+
+vfmsubadd213pd %xmm0, %xmm1, %xmm2
+vfmsubadd213pd (%rax), %xmm1, %xmm2
+
+vfmsubadd213pd %ymm0, %ymm1, %ymm2
+vfmsubadd213pd (%rax), %ymm1, %ymm2
+
+vfmsubadd231pd %xmm0, %xmm1, %xmm2
+vfmsubadd231pd (%rax), %xmm1, %xmm2
+
+vfmsubadd231pd %ymm0, %ymm1, %ymm2
+vfmsubadd231pd (%rax), %ymm1, %ymm2
+
+vfmsubadd132ps %xmm0, %xmm1, %xmm2
+vfmsubadd132ps (%rax), %xmm1, %xmm2
+
+vfmsubadd132ps %ymm0, %ymm1, %ymm2
+vfmsubadd132ps (%rax), %ymm1, %ymm2
+
+vfmsubadd213ps %xmm0, %xmm1, %xmm2
+vfmsubadd213ps (%rax), %xmm1, %xmm2
+
+vfmsubadd213ps %ymm0, %ymm1, %ymm2
+vfmsubadd213ps (%rax), %ymm1, %ymm2
+
+vfmsubadd231ps %xmm0, %xmm1, %xmm2
+vfmsubadd231ps (%rax), %xmm1, %xmm2
+
+vfmsubadd231ps %ymm0, %ymm1, %ymm2
+vfmsubadd231ps (%rax), %ymm1, %ymm2
+
+vfnmadd132pd %xmm0, %xmm1, %xmm2
+vfnmadd132pd (%rax), %xmm1, %xmm2
+
+vfnmadd132pd %ymm0, %ymm1, %ymm2
+vfnmadd132pd (%rax), %ymm1, %ymm2
+
+vfnmadd213pd %xmm0, %xmm1, %xmm2
+vfnmadd213pd (%rax), %xmm1, %xmm2
+
+vfnmadd213pd %ymm0, %ymm1, %ymm2
+vfnmadd213pd (%rax), %ymm1, %ymm2
+
+vfnmadd231pd %xmm0, %xmm1, %xmm2
+vfnmadd231pd (%rax), %xmm1, %xmm2
+
+vfnmadd231pd %ymm0, %ymm1, %ymm2
+vfnmadd231pd (%rax), %ymm1, %ymm2
+
+vfnmadd132ps %xmm0, %xmm1, %xmm2
+vfnmadd132ps (%rax), %xmm1, %xmm2
+
+vfnmadd132ps %ymm0, %ymm1, %ymm2
+vfnmadd132ps (%rax), %ymm1, %ymm2
+
+vfnmadd213ps %xmm0, %xmm1, %xmm2
+vfnmadd213ps (%rax), %xmm1, %xmm2
+
+vfnmadd213ps %ymm0, %ymm1, %ymm2
+vfnmadd213ps (%rax), %ymm1, %ymm2
+
+vfnmadd231ps %xmm0, %xmm1, %xmm2
+vfnmadd231ps (%rax), %xmm1, %xmm2
+
+vfnmadd231ps %ymm0, %ymm1, %ymm2
+vfnmadd231ps (%rax), %ymm1, %ymm2
+
+vfnmadd132sd %xmm0, %xmm1, %xmm2
+vfnmadd132sd (%rax), %xmm1, %xmm2
+
+vfnmadd213sd %xmm0, %xmm1, %xmm2
+vfnmadd213sd (%rax), %xmm1, %xmm2
+
+vfnmadd231sd %xmm0, %xmm1, %xmm2
+vfnmadd231sd (%rax), %xmm1, %xmm2
+
+vfnmadd132ss %xmm0, %xmm1, %xmm2
+vfnmadd132ss (%rax), %xmm1, %xmm2
+
+vfnmadd213ss %xmm0, %xmm1, %xmm2
+vfnmadd213ss (%rax), %xmm1, %xmm2
+
+vfnmadd231ss %xmm0, %xmm1, %xmm2
+vfnmadd231ss (%rax), %xmm1, %xmm2
+
+vfnmsub132pd %xmm0, %xmm1, %xmm2
+vfnmsub132pd (%rax), %xmm1, %xmm2
+
+vfnmsub132pd %ymm0, %ymm1, %ymm2
+vfnmsub132pd (%rax), %ymm1, %ymm2
+
+vfnmsub213pd %xmm0, %xmm1, %xmm2
+vfnmsub213pd (%rax), %xmm1, %xmm2
+
+vfnmsub213pd %ymm0, %ymm1, %ymm2
+vfnmsub213pd (%rax), %ymm1, %ymm2
+
+vfnmsub231pd %xmm0, %xmm1, %xmm2
+vfnmsub231pd (%rax), %xmm1, %xmm2
+
+vfnmsub231pd %ymm0, %ymm1, %ymm2
+vfnmsub231pd (%rax), %ymm1, %ymm2
+
+vfnmsub132ps %xmm0, %xmm1, %xmm2
+vfnmsub132ps (%rax), %xmm1, %xmm2
+
+vfnmsub132ps %ymm0, %ymm1, %ymm2
+vfnmsub132ps (%rax), %ymm1, %ymm2
+
+vfnmsub213ps %xmm0, %xmm1, %xmm2
+vfnmsub213ps (%rax), %xmm1, %xmm2
+
+vfnmsub213ps %ymm0, %ymm1, %ymm2
+vfnmsub213ps (%rax), %ymm1, %ymm2
+
+vfnmsub231ps %xmm0, %xmm1, %xmm2
+vfnmsub231ps (%rax), %xmm1, %xmm2
+
+vfnmsub231ps %ymm0, %ymm1, %ymm2
+vfnmsub231ps (%rax), %ymm1, %ymm2
+
+vfnmsub132sd %xmm0, %xmm1, %xmm2
+vfnmsub132sd (%rax), %xmm1, %xmm2
+
+vfnmsub213sd %xmm0, %xmm1, %xmm2
+vfnmsub213sd (%rax), %xmm1, %xmm2
+
+vfnmsub231sd %xmm0, %xmm1, %xmm2
+vfnmsub231sd (%rax), %xmm1, %xmm2
+
+vfnmsub132ss %xmm0, %xmm1, %xmm2
+vfnmsub132ss (%rax), %xmm1, %xmm2
+
+vfnmsub213ss %xmm0, %xmm1, %xmm2
+vfnmsub213ss (%rax), %xmm1, %xmm2
+
+vfnmsub231ss %xmm0, %xmm1, %xmm2
+vfnmsub231ss (%rax), %xmm1, %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 4 1.00 vfmadd132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmadd132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmadd132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfmadd132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfmadd213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmadd213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmadd213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfmadd213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfmadd231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmadd231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmadd231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfmadd231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfmadd132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmadd132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmadd132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfmadd132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfmadd213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmadd213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmadd213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfmadd213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfmadd231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmadd231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmadd231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfmadd231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfmadd132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmadd132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmadd213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmadd213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmadd231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmadd231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmadd132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmadd132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmadd213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmadd213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmadd231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmadd231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmaddsub132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmaddsub132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmaddsub132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfmaddsub132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfmaddsub213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmaddsub213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmaddsub213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfmaddsub213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfmaddsub231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmaddsub231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmaddsub231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfmaddsub231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfmaddsub132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmaddsub132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmaddsub132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfmaddsub132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfmaddsub213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmaddsub213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmaddsub213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfmaddsub213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfmaddsub231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmaddsub231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmaddsub231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfmaddsub231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfmsub132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmsub132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmsub132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfmsub132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfmsub213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmsub213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmsub213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfmsub213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfmsub231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmsub231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmsub231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfmsub231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfmsub132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmsub132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmsub132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfmsub132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfmsub213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmsub213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmsub213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfmsub213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfmsub231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmsub231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmsub231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfmsub231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfmsub132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmsub132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmsub213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmsub213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmsub231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmsub231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmsub132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmsub132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmsub213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmsub213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmsub231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmsub231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmsubadd132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmsubadd132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmsubadd132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfmsubadd132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfmsubadd213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmsubadd213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmsubadd213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfmsubadd213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfmsubadd231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmsubadd231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmsubadd231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfmsubadd231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfmsubadd132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmsubadd132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmsubadd132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfmsubadd132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfmsubadd213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmsubadd213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmsubadd213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfmsubadd213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfmsubadd231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfmsubadd231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfmsubadd231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfmsubadd231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfnmadd132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfnmadd132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfnmadd132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfnmadd132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfnmadd213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfnmadd213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfnmadd213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfnmadd213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfnmadd231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfnmadd231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfnmadd231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfnmadd231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfnmadd132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfnmadd132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfnmadd132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfnmadd132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfnmadd213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfnmadd213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfnmadd213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfnmadd213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfnmadd231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfnmadd231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfnmadd231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfnmadd231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfnmadd132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfnmadd132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfnmadd213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfnmadd213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfnmadd231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfnmadd231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfnmadd132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfnmadd132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfnmadd213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfnmadd213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfnmadd231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfnmadd231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfnmsub132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfnmsub132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfnmsub132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfnmsub132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfnmsub213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfnmsub213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfnmsub213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfnmsub213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfnmsub231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfnmsub231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfnmsub231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfnmsub231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfnmsub132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfnmsub132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfnmsub132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfnmsub132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfnmsub213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfnmsub213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfnmsub213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfnmsub213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfnmsub231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfnmsub231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfnmsub231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vfnmsub231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vfnmsub132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfnmsub132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfnmsub213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfnmsub213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfnmsub231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfnmsub231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfnmsub132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfnmsub132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfnmsub213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfnmsub213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vfnmsub231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vfnmsub231ss (%rax), %xmm1, %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: - - - - - - - - 192.00 192.00 - - 48.00 48.00 - 32.00 32.00 32.00 32.00 32.00 32.00 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmadd132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmadd132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmadd132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmadd132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmadd213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmadd213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmadd213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmadd213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmadd231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmadd231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmadd231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmadd231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmadd132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmadd132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmadd132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmadd132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmadd213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmadd213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmadd213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmadd213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmadd231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmadd231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmadd231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmadd231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmadd132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmadd132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmadd213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmadd213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmadd231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmadd231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmadd132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmadd132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmadd213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmadd213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmadd231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmadd231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmaddsub132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmaddsub132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmaddsub132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmaddsub132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmaddsub213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmaddsub213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmaddsub213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmaddsub213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmaddsub231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmaddsub231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmaddsub231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmaddsub231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmaddsub132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmaddsub132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmaddsub132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmaddsub132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmaddsub213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmaddsub213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmaddsub213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmaddsub213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmaddsub231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmaddsub231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmaddsub231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmaddsub231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmsub132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmsub132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmsub132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmsub132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmsub213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmsub213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmsub213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmsub213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmsub231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmsub231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmsub231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmsub231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmsub132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmsub132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmsub132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmsub132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmsub213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmsub213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmsub213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmsub213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmsub231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmsub231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmsub231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmsub231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmsub132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmsub132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmsub213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmsub213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmsub231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmsub231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmsub132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmsub132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmsub213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmsub213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmsub231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmsub231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmsubadd132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmsubadd132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmsubadd132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmsubadd132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmsubadd213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmsubadd213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmsubadd213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmsubadd213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmsubadd231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmsubadd231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmsubadd231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmsubadd231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmsubadd132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmsubadd132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmsubadd132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmsubadd132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmsubadd213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmsubadd213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmsubadd213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmsubadd213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmsubadd231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmsubadd231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfmsubadd231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfmsubadd231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmadd132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmadd132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmadd132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmadd132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmadd213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmadd213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmadd213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmadd213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmadd231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmadd231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmadd231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmadd231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmadd132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmadd132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmadd132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmadd132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmadd213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmadd213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmadd213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmadd213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmadd231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmadd231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmadd231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmadd231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmadd132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmadd132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmadd213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmadd213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmadd231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmadd231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmadd132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmadd132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmadd213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmadd213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmadd231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmadd231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmsub132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmsub132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmsub132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmsub132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmsub213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmsub213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmsub213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmsub213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmsub231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmsub231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmsub231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmsub231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmsub132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmsub132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmsub132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmsub132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmsub213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmsub213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmsub213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmsub213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmsub231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmsub231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmsub231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmsub231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmsub132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmsub132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmsub213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmsub213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmsub231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmsub231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmsub132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmsub132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmsub213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmsub213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - vfnmsub231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vfnmsub231ss (%rax), %xmm1, %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-fsgsbase.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-fsgsbase.s
new file mode 100644
index 0000000000000..142508c4477e5
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-fsgsbase.s
@@ -0,0 +1,72 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+rdfsbase %eax
+rdfsbase %rax
+
+rdgsbase %eax
+rdgsbase %rax
+
+wrfsbase %edi
+wrfsbase %rdi
+
+wrgsbase %edi
+wrgsbase %rdi
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 100 100 25.00 * * U rdfsbasel %eax
+# CHECK-NEXT: 100 100 25.00 * * U rdfsbaseq %rax
+# CHECK-NEXT: 100 100 25.00 * * U rdgsbasel %eax
+# CHECK-NEXT: 100 100 25.00 * * U rdgsbaseq %rax
+# CHECK-NEXT: 100 100 25.00 * * U wrfsbasel %edi
+# CHECK-NEXT: 100 100 25.00 * * U wrfsbaseq %rdi
+# CHECK-NEXT: 100 100 25.00 * * U wrgsbasel %edi
+# CHECK-NEXT: 100 100 25.00 * * U wrgsbaseq %rdi
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: - - - 200.00 200.00 200.00 200.00 - - - - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - rdfsbasel %eax
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - rdfsbaseq %rax
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - rdgsbasel %eax
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - rdgsbaseq %rax
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - wrfsbasel %edi
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - wrfsbaseq %rdi
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - wrgsbasel %edi
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - wrgsbaseq %rdi
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-lea.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-lea.s
new file mode 100644
index 0000000000000..1545a228d9c55
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-lea.s
@@ -0,0 +1,452 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+lea 0(), %cx
+lea 0(), %ecx
+lea 0(), %rcx
+lea (%eax), %cx
+lea (%eax), %ecx
+lea (%eax), %rcx
+lea (%rax), %cx
+lea (%rax), %ecx
+lea (%rax), %rcx
+lea (, %ebx), %cx
+lea (, %ebx), %ecx
+lea (, %ebx), %rcx
+lea (, %rbx), %cx
+lea (, %rbx), %ecx
+lea (, %rbx), %rcx
+lea (, %ebx, 1), %cx
+lea (, %ebx, 1), %ecx
+lea (, %ebx, 1), %rcx
+lea (, %rbx, 1), %cx
+lea (, %rbx, 1), %ecx
+lea (, %rbx, 1), %rcx
+lea (, %ebx, 2), %cx
+lea (, %ebx, 2), %ecx
+lea (, %ebx, 2), %rcx
+lea (, %rbx, 2), %cx
+lea (, %rbx, 2), %ecx
+lea (, %rbx, 2), %rcx
+lea (%eax, %ebx), %cx
+lea (%eax, %ebx), %ecx
+lea (%eax, %ebx), %rcx
+lea (%rax, %rbx), %cx
+lea (%rax, %rbx), %ecx
+lea (%rax, %rbx), %rcx
+lea (%eax, %ebx, 1), %cx
+lea (%eax, %ebx, 1), %ecx
+lea (%eax, %ebx, 1), %rcx
+lea (%rax, %rbx, 1), %cx
+lea (%rax, %rbx, 1), %ecx
+lea (%rax, %rbx, 1), %rcx
+lea (%eax, %ebx, 2), %cx
+lea (%eax, %ebx, 2), %ecx
+lea (%eax, %ebx, 2), %rcx
+lea (%rax, %rbx, 2), %cx
+lea (%rax, %rbx, 2), %ecx
+lea (%rax, %rbx, 2), %rcx
+
+lea -16(), %cx
+lea -16(), %ecx
+lea -16(), %rcx
+lea -16(%eax), %cx
+lea -16(%eax), %ecx
+lea -16(%eax), %rcx
+lea -16(%rax), %cx
+lea -16(%rax), %ecx
+lea -16(%rax), %rcx
+lea -16(, %ebx), %cx
+lea -16(, %ebx), %ecx
+lea -16(, %ebx), %rcx
+lea -16(, %rbx), %cx
+lea -16(, %rbx), %ecx
+lea -16(, %rbx), %rcx
+lea -16(, %ebx, 1), %cx
+lea -16(, %ebx, 1), %ecx
+lea -16(, %ebx, 1), %rcx
+lea -16(, %rbx, 1), %cx
+lea -16(, %rbx, 1), %ecx
+lea -16(, %rbx, 1), %rcx
+lea -16(, %ebx, 2), %cx
+lea -16(, %ebx, 2), %ecx
+lea -16(, %ebx, 2), %rcx
+lea -16(, %rbx, 2), %cx
+lea -16(, %rbx, 2), %ecx
+lea -16(, %rbx, 2), %rcx
+lea -16(%eax, %ebx), %cx
+lea -16(%eax, %ebx), %ecx
+lea -16(%eax, %ebx), %rcx
+lea -16(%rax, %rbx), %cx
+lea -16(%rax, %rbx), %ecx
+lea -16(%rax, %rbx), %rcx
+lea -16(%eax, %ebx, 1), %cx
+lea -16(%eax, %ebx, 1), %ecx
+lea -16(%eax, %ebx, 1), %rcx
+lea -16(%rax, %rbx, 1), %cx
+lea -16(%rax, %rbx, 1), %ecx
+lea -16(%rax, %rbx, 1), %rcx
+lea -16(%eax, %ebx, 2), %cx
+lea -16(%eax, %ebx, 2), %ecx
+lea -16(%eax, %ebx, 2), %rcx
+lea -16(%rax, %rbx, 2), %cx
+lea -16(%rax, %rbx, 2), %ecx
+lea -16(%rax, %rbx, 2), %rcx
+
+lea 1024(), %cx
+lea 1024(), %ecx
+lea 1024(), %rcx
+lea 1024(%eax), %cx
+lea 1024(%eax), %ecx
+lea 1024(%eax), %rcx
+lea 1024(%rax), %cx
+lea 1024(%rax), %ecx
+lea 1024(%rax), %rcx
+lea 1024(, %ebx), %cx
+lea 1024(, %ebx), %ecx
+lea 1024(, %ebx), %rcx
+lea 1024(, %rbx), %cx
+lea 1024(, %rbx), %ecx
+lea 1024(, %rbx), %rcx
+lea 1024(, %ebx, 1), %cx
+lea 1024(, %ebx, 1), %ecx
+lea 1024(, %ebx, 1), %rcx
+lea 1024(, %rbx, 1), %cx
+lea 1024(, %rbx, 1), %ecx
+lea 1024(, %rbx, 1), %rcx
+lea 1024(, %ebx, 2), %cx
+lea 1024(, %ebx, 2), %ecx
+lea 1024(, %ebx, 2), %rcx
+lea 1024(, %rbx, 2), %cx
+lea 1024(, %rbx, 2), %ecx
+lea 1024(, %rbx, 2), %rcx
+lea 1024(%eax, %ebx), %cx
+lea 1024(%eax, %ebx), %ecx
+lea 1024(%eax, %ebx), %rcx
+lea 1024(%rax, %rbx), %cx
+lea 1024(%rax, %rbx), %ecx
+lea 1024(%rax, %rbx), %rcx
+lea 1024(%eax, %ebx, 1), %cx
+lea 1024(%eax, %ebx, 1), %ecx
+lea 1024(%eax, %ebx, 1), %rcx
+lea 1024(%rax, %rbx, 1), %cx
+lea 1024(%rax, %rbx, 1), %ecx
+lea 1024(%rax, %rbx, 1), %rcx
+lea 1024(%eax, %ebx, 2), %cx
+lea 1024(%eax, %ebx, 2), %ecx
+lea 1024(%eax, %ebx, 2), %rcx
+lea 1024(%rax, %rbx, 2), %cx
+lea 1024(%rax, %rbx, 2), %ecx
+lea 1024(%rax, %rbx, 2), %rcx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 2 2 1.00 leaw 0, %cx
+# CHECK-NEXT: 1 1 0.33 leal 0, %ecx
+# CHECK-NEXT: 1 1 0.33 leaq 0, %rcx
+# CHECK-NEXT: 2 2 1.00 leaw (%eax), %cx
+# CHECK-NEXT: 1 1 0.33 leal (%eax), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq (%eax), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw (%rax), %cx
+# CHECK-NEXT: 1 1 0.33 leal (%rax), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq (%rax), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw (,%ebx), %cx
+# CHECK-NEXT: 1 1 0.33 leal (,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq (,%ebx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw (,%rbx), %cx
+# CHECK-NEXT: 1 1 0.33 leal (,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq (,%rbx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw (,%ebx), %cx
+# CHECK-NEXT: 1 1 0.33 leal (,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq (,%ebx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw (,%rbx), %cx
+# CHECK-NEXT: 1 1 0.33 leal (,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq (,%rbx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw (,%ebx,2), %cx
+# CHECK-NEXT: 2 2 0.25 leal (,%ebx,2), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq (,%ebx,2), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw (,%rbx,2), %cx
+# CHECK-NEXT: 2 2 0.25 leal (,%rbx,2), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq (,%rbx,2), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw (%eax,%ebx), %cx
+# CHECK-NEXT: 1 1 0.33 leal (%eax,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq (%eax,%ebx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw (%rax,%rbx), %cx
+# CHECK-NEXT: 1 1 0.33 leal (%rax,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq (%rax,%rbx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw (%eax,%ebx), %cx
+# CHECK-NEXT: 1 1 0.33 leal (%eax,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq (%eax,%ebx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw (%rax,%rbx), %cx
+# CHECK-NEXT: 1 1 0.33 leal (%rax,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq (%rax,%rbx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw (%eax,%ebx,2), %cx
+# CHECK-NEXT: 2 2 0.25 leal (%eax,%ebx,2), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq (%eax,%ebx,2), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw (%rax,%rbx,2), %cx
+# CHECK-NEXT: 2 2 0.25 leal (%rax,%rbx,2), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq (%rax,%rbx,2), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw -16, %cx
+# CHECK-NEXT: 1 1 0.33 leal -16, %ecx
+# CHECK-NEXT: 1 1 0.33 leaq -16, %rcx
+# CHECK-NEXT: 2 2 1.00 leaw -16(%eax), %cx
+# CHECK-NEXT: 1 1 0.33 leal -16(%eax), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq -16(%eax), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw -16(%rax), %cx
+# CHECK-NEXT: 1 1 0.33 leal -16(%rax), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq -16(%rax), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw -16(,%ebx), %cx
+# CHECK-NEXT: 1 1 0.33 leal -16(,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq -16(,%ebx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw -16(,%rbx), %cx
+# CHECK-NEXT: 1 1 0.33 leal -16(,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq -16(,%rbx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw -16(,%ebx), %cx
+# CHECK-NEXT: 1 1 0.33 leal -16(,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq -16(,%ebx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw -16(,%rbx), %cx
+# CHECK-NEXT: 1 1 0.33 leal -16(,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq -16(,%rbx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw -16(,%ebx,2), %cx
+# CHECK-NEXT: 2 2 0.25 leal -16(,%ebx,2), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq -16(,%ebx,2), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw -16(,%rbx,2), %cx
+# CHECK-NEXT: 2 2 0.25 leal -16(,%rbx,2), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq -16(,%rbx,2), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw -16(%eax,%ebx), %cx
+# CHECK-NEXT: 2 2 0.25 leal -16(%eax,%ebx), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq -16(%eax,%ebx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw -16(%rax,%rbx), %cx
+# CHECK-NEXT: 2 2 0.25 leal -16(%rax,%rbx), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq -16(%rax,%rbx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw -16(%eax,%ebx), %cx
+# CHECK-NEXT: 2 2 0.25 leal -16(%eax,%ebx), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq -16(%eax,%ebx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw -16(%rax,%rbx), %cx
+# CHECK-NEXT: 2 2 0.25 leal -16(%rax,%rbx), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq -16(%rax,%rbx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw -16(%eax,%ebx,2), %cx
+# CHECK-NEXT: 2 2 0.25 leal -16(%eax,%ebx,2), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq -16(%eax,%ebx,2), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw -16(%rax,%rbx,2), %cx
+# CHECK-NEXT: 2 2 0.25 leal -16(%rax,%rbx,2), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq -16(%rax,%rbx,2), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw 1024, %cx
+# CHECK-NEXT: 1 1 0.33 leal 1024, %ecx
+# CHECK-NEXT: 1 1 0.33 leaq 1024, %rcx
+# CHECK-NEXT: 2 2 1.00 leaw 1024(%eax), %cx
+# CHECK-NEXT: 1 1 0.33 leal 1024(%eax), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq 1024(%eax), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw 1024(%rax), %cx
+# CHECK-NEXT: 1 1 0.33 leal 1024(%rax), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq 1024(%rax), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw 1024(,%ebx), %cx
+# CHECK-NEXT: 1 1 0.33 leal 1024(,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq 1024(,%ebx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw 1024(,%rbx), %cx
+# CHECK-NEXT: 1 1 0.33 leal 1024(,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq 1024(,%rbx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw 1024(,%ebx), %cx
+# CHECK-NEXT: 1 1 0.33 leal 1024(,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq 1024(,%ebx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw 1024(,%rbx), %cx
+# CHECK-NEXT: 1 1 0.33 leal 1024(,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq 1024(,%rbx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw 1024(,%ebx,2), %cx
+# CHECK-NEXT: 2 2 0.25 leal 1024(,%ebx,2), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq 1024(,%ebx,2), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw 1024(,%rbx,2), %cx
+# CHECK-NEXT: 2 2 0.25 leal 1024(,%rbx,2), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq 1024(,%rbx,2), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw 1024(%eax,%ebx), %cx
+# CHECK-NEXT: 2 2 0.25 leal 1024(%eax,%ebx), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq 1024(%eax,%ebx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw 1024(%rax,%rbx), %cx
+# CHECK-NEXT: 2 2 0.25 leal 1024(%rax,%rbx), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq 1024(%rax,%rbx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw 1024(%eax,%ebx), %cx
+# CHECK-NEXT: 2 2 0.25 leal 1024(%eax,%ebx), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq 1024(%eax,%ebx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw 1024(%rax,%rbx), %cx
+# CHECK-NEXT: 2 2 0.25 leal 1024(%rax,%rbx), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq 1024(%rax,%rbx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw 1024(%eax,%ebx,2), %cx
+# CHECK-NEXT: 2 2 0.25 leal 1024(%eax,%ebx,2), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq 1024(%eax,%ebx,2), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw 1024(%rax,%rbx,2), %cx
+# CHECK-NEXT: 2 2 0.25 leal 1024(%rax,%rbx,2), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq 1024(%rax,%rbx,2), %rcx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: 16.67 16.67 16.67 55.00 55.00 55.00 55.00 - - - - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw 0, %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal 0, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq 0, %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw (%eax), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal (%eax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq (%eax), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw (%rax), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal (%rax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq (%rax), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw (,%ebx), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal (,%ebx), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq (,%ebx), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw (,%rbx), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal (,%rbx), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq (,%rbx), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw (,%ebx), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal (,%ebx), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq (,%ebx), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw (,%rbx), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal (,%rbx), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq (,%rbx), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw (,%ebx,2), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal (,%ebx,2), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq (,%ebx,2), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw (,%rbx,2), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal (,%rbx,2), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq (,%rbx,2), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw (%eax,%ebx), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal (%eax,%ebx), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq (%eax,%ebx), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw (%rax,%rbx), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal (%rax,%rbx), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq (%rax,%rbx), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw (%eax,%ebx), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal (%eax,%ebx), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq (%eax,%ebx), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw (%rax,%rbx), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal (%rax,%rbx), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq (%rax,%rbx), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw (%eax,%ebx,2), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal (%eax,%ebx,2), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq (%eax,%ebx,2), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw (%rax,%rbx,2), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal (%rax,%rbx,2), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq (%rax,%rbx,2), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw -16, %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal -16, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq -16, %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw -16(%eax), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal -16(%eax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq -16(%eax), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw -16(%rax), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal -16(%rax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq -16(%rax), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw -16(,%ebx), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal -16(,%ebx), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq -16(,%ebx), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw -16(,%rbx), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal -16(,%rbx), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq -16(,%rbx), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw -16(,%ebx), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal -16(,%ebx), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq -16(,%ebx), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw -16(,%rbx), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal -16(,%rbx), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq -16(,%rbx), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw -16(,%ebx,2), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal -16(,%ebx,2), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq -16(,%ebx,2), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw -16(,%rbx,2), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal -16(,%rbx,2), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq -16(,%rbx,2), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw -16(%eax,%ebx), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal -16(%eax,%ebx), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq -16(%eax,%ebx), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw -16(%rax,%rbx), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal -16(%rax,%rbx), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq -16(%rax,%rbx), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw -16(%eax,%ebx), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal -16(%eax,%ebx), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq -16(%eax,%ebx), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw -16(%rax,%rbx), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal -16(%rax,%rbx), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq -16(%rax,%rbx), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw -16(%eax,%ebx,2), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal -16(%eax,%ebx,2), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq -16(%eax,%ebx,2), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw -16(%rax,%rbx,2), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal -16(%rax,%rbx,2), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq -16(%rax,%rbx,2), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw 1024, %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal 1024, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq 1024, %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw 1024(%eax), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal 1024(%eax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq 1024(%eax), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw 1024(%rax), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal 1024(%rax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq 1024(%rax), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw 1024(,%ebx), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal 1024(,%ebx), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq 1024(,%ebx), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw 1024(,%rbx), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal 1024(,%rbx), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq 1024(,%rbx), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw 1024(,%ebx), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal 1024(,%ebx), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq 1024(,%ebx), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw 1024(,%rbx), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal 1024(,%rbx), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq 1024(,%rbx), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw 1024(,%ebx,2), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal 1024(,%ebx,2), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq 1024(,%ebx,2), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw 1024(,%rbx,2), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal 1024(,%rbx,2), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq 1024(,%rbx,2), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw 1024(%eax,%ebx), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal 1024(%eax,%ebx), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq 1024(%eax,%ebx), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw 1024(%rax,%rbx), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal 1024(%rax,%rbx), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq 1024(%rax,%rbx), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw 1024(%eax,%ebx), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal 1024(%eax,%ebx), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq 1024(%eax,%ebx), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw 1024(%rax,%rbx), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal 1024(%rax,%rbx), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq 1024(%rax,%rbx), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw 1024(%eax,%ebx,2), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal 1024(%eax,%ebx,2), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq 1024(%eax,%ebx,2), %rcx
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - leaw 1024(%rax,%rbx,2), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal 1024(%rax,%rbx,2), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq 1024(%rax,%rbx,2), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-lzcnt.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-lzcnt.s
new file mode 100644
index 0000000000000..ffbe414bac6c0
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-lzcnt.s
@@ -0,0 +1,65 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+lzcntw %cx, %cx
+lzcntw (%rax), %cx
+
+lzcntl %eax, %ecx
+lzcntl (%rax), %ecx
+
+lzcntq %rax, %rcx
+lzcntq (%rax), %rcx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 lzcntw %cx, %cx
+# CHECK-NEXT: 1 5 0.33 * lzcntw (%rax), %cx
+# CHECK-NEXT: 1 1 0.25 lzcntl %eax, %ecx
+# CHECK-NEXT: 1 5 0.33 * lzcntl (%rax), %ecx
+# CHECK-NEXT: 1 1 0.25 lzcntq %rax, %rcx
+# CHECK-NEXT: 1 5 0.33 * lzcntq (%rax), %rcx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: 1.00 1.00 1.00 2.25 2.25 2.25 2.25 - - - - - - - - 1.00 1.00 1.00 1.00 1.00 1.00 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - lzcntw %cx, %cx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - lzcntw (%rax), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - lzcntl %eax, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - lzcntl (%rax), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - lzcntq %rax, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - lzcntq (%rax), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-mmx.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-mmx.s
new file mode 100644
index 0000000000000..75dbf95f4caae
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-mmx.s
@@ -0,0 +1,408 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+emms
+
+movd %eax, %mm2
+movd (%rax), %mm2
+
+movd %mm0, %ecx
+movd %mm0, (%rax)
+
+movq %rax, %mm2
+movq (%rax), %mm2
+
+movq %mm0, %rcx
+movq %mm0, (%rax)
+
+packsswb %mm0, %mm2
+packsswb (%rax), %mm2
+
+packssdw %mm0, %mm2
+packssdw (%rax), %mm2
+
+packuswb %mm0, %mm2
+packuswb (%rax), %mm2
+
+paddb %mm0, %mm2
+paddb (%rax), %mm2
+
+paddd %mm0, %mm2
+paddd (%rax), %mm2
+
+paddsb %mm0, %mm2
+paddsb (%rax), %mm2
+
+paddsw %mm0, %mm2
+paddsw (%rax), %mm2
+
+paddusb %mm0, %mm2
+paddusb (%rax), %mm2
+
+paddusw %mm0, %mm2
+paddusw (%rax), %mm2
+
+paddw %mm0, %mm2
+paddw (%rax), %mm2
+
+pand %mm0, %mm2
+pand (%rax), %mm2
+
+pandn %mm0, %mm2
+pandn (%rax), %mm2
+
+pcmpeqb %mm0, %mm2
+pcmpeqb (%rax), %mm2
+
+pcmpeqd %mm0, %mm2
+pcmpeqd (%rax), %mm2
+
+pcmpeqw %mm0, %mm2
+pcmpeqw (%rax), %mm2
+
+pcmpgtb %mm0, %mm2
+pcmpgtb (%rax), %mm2
+
+pcmpgtd %mm0, %mm2
+pcmpgtd (%rax), %mm2
+
+pcmpgtw %mm0, %mm2
+pcmpgtw (%rax), %mm2
+
+pmaddwd %mm0, %mm2
+pmaddwd (%rax), %mm2
+
+pmulhw %mm0, %mm2
+pmulhw (%rax), %mm2
+
+pmullw %mm0, %mm2
+pmullw (%rax), %mm2
+
+por %mm0, %mm2
+por (%rax), %mm2
+
+pslld $1, %mm2
+pslld %mm0, %mm2
+pslld (%rax), %mm2
+
+psllq $1, %mm2
+psllq %mm0, %mm2
+psllq (%rax), %mm2
+
+psllw $1, %mm2
+psllw %mm0, %mm2
+psllw (%rax), %mm2
+
+psrad $1, %mm2
+psrad %mm0, %mm2
+psrad (%rax), %mm2
+
+psraw $1, %mm2
+psraw %mm0, %mm2
+psraw (%rax), %mm2
+
+psrld $1, %mm2
+psrld %mm0, %mm2
+psrld (%rax), %mm2
+
+psrlq $1, %mm2
+psrlq %mm0, %mm2
+psrlq (%rax), %mm2
+
+psrlw $1, %mm2
+psrlw %mm0, %mm2
+psrlw (%rax), %mm2
+
+psubb %mm0, %mm2
+psubb (%rax), %mm2
+
+psubd %mm0, %mm2
+psubd (%rax), %mm2
+
+psubsb %mm0, %mm2
+psubsb (%rax), %mm2
+
+psubsw %mm0, %mm2
+psubsw (%rax), %mm2
+
+psubusb %mm0, %mm2
+psubusb (%rax), %mm2
+
+psubusw %mm0, %mm2
+psubusw (%rax), %mm2
+
+psubw %mm0, %mm2
+psubw (%rax), %mm2
+
+punpckhbw %mm0, %mm2
+punpckhbw (%rax), %mm2
+
+punpckhdq %mm0, %mm2
+punpckhdq (%rax), %mm2
+
+punpckhwd %mm0, %mm2
+punpckhwd (%rax), %mm2
+
+punpcklbw %mm0, %mm2
+punpcklbw (%rax), %mm2
+
+punpckldq %mm0, %mm2
+punpckldq (%rax), %mm2
+
+punpcklwd %mm0, %mm2
+punpcklwd (%rax), %mm2
+
+pxor %mm0, %mm2
+pxor (%rax), %mm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 2 0.25 * * U emms
+# CHECK-NEXT: 2 1 1.00 movd %eax, %mm2
+# CHECK-NEXT: 1 8 0.50 * movd (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 movd %mm0, %ecx
+# CHECK-NEXT: 1 1 1.00 * U movd %mm0, (%rax)
+# CHECK-NEXT: 2 1 1.00 movq %rax, %mm2
+# CHECK-NEXT: 1 8 0.50 * movq (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 movq %mm0, %rcx
+# CHECK-NEXT: 1 1 1.00 * movq %mm0, (%rax)
+# CHECK-NEXT: 1 1 0.50 packsswb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * packsswb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 packssdw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * packssdw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 packuswb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * packuswb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 paddb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * paddb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 paddd %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * paddd (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 paddsb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * paddsb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 paddsw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * paddsw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 paddusb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * paddusb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 paddusw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * paddusw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 paddw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * paddw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pand %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pand (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pandn %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pandn (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pcmpeqb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pcmpeqb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pcmpeqd %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pcmpeqd (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pcmpeqw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pcmpeqw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pcmpgtb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pcmpgtb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pcmpgtd %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pcmpgtd (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pcmpgtw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pcmpgtw (%rax), %mm2
+# CHECK-NEXT: 1 3 0.50 pmaddwd %mm0, %mm2
+# CHECK-NEXT: 1 10 0.50 * pmaddwd (%rax), %mm2
+# CHECK-NEXT: 1 3 0.50 pmulhw %mm0, %mm2
+# CHECK-NEXT: 1 10 0.50 * pmulhw (%rax), %mm2
+# CHECK-NEXT: 1 3 0.50 pmullw %mm0, %mm2
+# CHECK-NEXT: 1 10 0.50 * pmullw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 por %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * por (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 pslld $1, %mm2
+# CHECK-NEXT: 1 1 0.50 pslld %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pslld (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psllq $1, %mm2
+# CHECK-NEXT: 1 1 0.50 psllq %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psllq (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psllw $1, %mm2
+# CHECK-NEXT: 1 1 0.50 psllw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psllw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psrad $1, %mm2
+# CHECK-NEXT: 1 1 0.50 psrad %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psrad (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psraw $1, %mm2
+# CHECK-NEXT: 1 1 0.50 psraw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psraw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psrld $1, %mm2
+# CHECK-NEXT: 1 1 0.50 psrld %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psrld (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psrlq $1, %mm2
+# CHECK-NEXT: 1 1 0.50 psrlq %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psrlq (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psrlw $1, %mm2
+# CHECK-NEXT: 1 1 0.50 psrlw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psrlw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 psubb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psubb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 psubd %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psubd (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psubsb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psubsb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psubsw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psubsw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psubusb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psubusb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psubusw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psubusw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 psubw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psubw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 punpckhbw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * punpckhbw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 punpckhdq %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * punpckhdq (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 punpckhwd %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * punpckhwd (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 punpcklbw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * punpcklbw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 punpckldq %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * punpckldq (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 punpcklwd %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * punpcklwd (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pxor %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pxor (%rax), %mm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - 19.00 37.00 33.00 15.00 27.00 27.00 2.00 16.00 16.00 16.00 15.33 15.33 15.33 1.00 1.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - emms
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 1.00 1.00 0.50 0.50 - - - - - - - - - movd %eax, %mm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - movd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - movd %mm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 movd %mm0, (%rax)
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 1.00 1.00 0.50 0.50 - - - - - - - - - movq %rax, %mm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - movq (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - movq %mm0, %rcx
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 movq %mm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - packsswb %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - packsswb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - packssdw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - packssdw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - packuswb %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - packuswb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - paddb %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - paddb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - paddd %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - paddd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - paddsb %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - paddsb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - paddsw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - paddsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - paddusb %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - paddusb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - paddusw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - paddusw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - paddw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - paddw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pand %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pand (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pandn %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pandn (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pcmpeqb %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pcmpeqb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pcmpeqd %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pcmpeqd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pcmpeqw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pcmpeqw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pcmpgtb %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pcmpgtb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pcmpgtd %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pcmpgtd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pcmpgtw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pcmpgtw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 - - - - - - - - - - - pmaddwd %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pmaddwd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 - - - - - - - - - - - pmulhw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pmulhw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 - - - - - - - - - - - pmullw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pmullw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - por %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - por (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - pslld $1, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - pslld %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pslld (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - psllq $1, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - psllq %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - psllq (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - psllw $1, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - psllw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - psllw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - psrad $1, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - psrad %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - psrad (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - psraw $1, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - psraw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - psraw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - psrld $1, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - psrld %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - psrld (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - psrlq $1, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - psrlq %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - psrlq (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - psrlw $1, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - psrlw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - psrlw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - psubb %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - psubb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - psubd %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - psubd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - psubsb %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - psubsb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - psubsw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - psubsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - psubusb %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - psubusb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - psubusw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - psubusw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - psubw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - psubw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - punpckhbw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - punpckhbw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - punpckhdq %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - punpckhdq (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - punpckhwd %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - punpckhwd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - punpcklbw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - punpcklbw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - punpckldq %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - punpckldq (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - punpcklwd %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - punpcklwd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pxor %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pxor (%rax), %mm2
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-movbe.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-movbe.s
new file mode 100644
index 0000000000000..144e97fbaf58f
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-movbe.s
@@ -0,0 +1,65 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+movbe %cx, (%rax)
+movbe (%rax), %cx
+
+movbe %ecx, (%rax)
+movbe (%rax), %ecx
+
+movbe %rcx, (%rax)
+movbe (%rax), %rcx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 2 1 1.00 * movbew %cx, (%rax)
+# CHECK-NEXT: 1 4 1.00 * movbew (%rax), %cx
+# CHECK-NEXT: 2 1 1.00 * movbel %ecx, (%rax)
+# CHECK-NEXT: 1 5 0.33 * movbel (%rax), %ecx
+# CHECK-NEXT: 2 1 1.00 * movbeq %rcx, (%rax)
+# CHECK-NEXT: 1 5 0.33 * movbeq (%rax), %rcx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: 2.00 2.00 2.00 4.50 4.50 4.50 4.50 - - - - - - - - 2.00 2.00 2.00 1.00 1.00 1.00 1.50 1.50
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 1.00 1.00 1.00 - - - - - - - - 0.33 0.33 0.33 - - - 0.50 0.50 movbew %cx, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 1.00 1.00 1.00 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - movbew (%rax), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 1.00 1.00 1.00 - - - - - - - - 0.33 0.33 0.33 - - - 0.50 0.50 movbel %ecx, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - movbel (%rax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 1.00 1.00 1.00 - - - - - - - - 0.33 0.33 0.33 - - - 0.50 0.50 movbeq %rcx, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - movbeq (%rax), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-mwaitx.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-mwaitx.s
new file mode 100644
index 0000000000000..3b343d733425e
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-mwaitx.s
@@ -0,0 +1,51 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+monitorx
+mwaitx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 100 100 25.00 U monitorx
+# CHECK-NEXT: 100 100 25.00 U mwaitx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: - - - 50.00 50.00 50.00 50.00 - - - - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - monitorx
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - mwaitx
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-pclmul.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-pclmul.s
new file mode 100644
index 0000000000000..2d9f0e9b14e2b
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-pclmul.s
@@ -0,0 +1,51 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+pclmulqdq $11, %xmm0, %xmm2
+pclmulqdq $11, (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 4 4 2.00 pclmulqdq $11, %xmm0, %xmm2
+# CHECK-NEXT: 4 11 2.00 * pclmulqdq $11, (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: - - - - - - - - 4.00 4.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - - - - - - 2.00 2.00 - - - - - - - - - - - - - pclmulqdq $11, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 2.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pclmulqdq $11, (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-popcnt.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-popcnt.s
new file mode 100644
index 0000000000000..cce078f2a8d8e
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-popcnt.s
@@ -0,0 +1,65 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+popcntw %cx, %cx
+popcntw (%rax), %cx
+
+popcntl %eax, %ecx
+popcntl (%rax), %ecx
+
+popcntq %rax, %rcx
+popcntq (%rax), %rcx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 popcntw %cx, %cx
+# CHECK-NEXT: 1 5 0.33 * popcntw (%rax), %cx
+# CHECK-NEXT: 1 1 0.25 popcntl %eax, %ecx
+# CHECK-NEXT: 1 5 0.33 * popcntl (%rax), %ecx
+# CHECK-NEXT: 1 1 0.25 popcntq %rax, %rcx
+# CHECK-NEXT: 1 5 0.33 * popcntq (%rax), %rcx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: 1.00 1.00 1.00 2.25 2.25 2.25 2.25 - - - - - - - - 1.00 1.00 1.00 1.00 1.00 1.00 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - popcntw %cx, %cx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - popcntw (%rax), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - popcntl %eax, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - popcntl (%rax), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - popcntq %rax, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - popcntq (%rax), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-prefetchw.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-prefetchw.s
new file mode 100644
index 0000000000000..5423b6bcff1f7
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-prefetchw.s
@@ -0,0 +1,51 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+prefetch (%rax)
+prefetchw (%rax)
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 5 0.33 * * prefetch (%rax)
+# CHECK-NEXT: 1 5 0.33 * * prefetchw (%rax)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: 0.67 0.67 0.67 - - - - - - - - - - - - 0.67 0.67 0.67 0.67 0.67 0.67 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - prefetch (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - prefetchw (%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-rdrand.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-rdrand.s
new file mode 100644
index 0000000000000..fb09253644496
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-rdrand.s
@@ -0,0 +1,54 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+rdrand %ax
+rdrand %eax
+rdrand %rax
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 100 100 25.00 U rdrandw %ax
+# CHECK-NEXT: 100 100 25.00 U rdrandl %eax
+# CHECK-NEXT: 100 100 25.00 U rdrandq %rax
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: - - - 75.00 75.00 75.00 75.00 - - - - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - rdrandw %ax
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - rdrandl %eax
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - rdrandq %rax
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-rdseed.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-rdseed.s
new file mode 100644
index 0000000000000..f10a90ff9bc4f
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-rdseed.s
@@ -0,0 +1,54 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+rdseed %ax
+rdseed %eax
+rdseed %rax
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 100 100 25.00 U rdseedw %ax
+# CHECK-NEXT: 100 100 25.00 U rdseedl %eax
+# CHECK-NEXT: 100 100 25.00 U rdseedq %rax
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: - - - 75.00 75.00 75.00 75.00 - - - - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - rdseedw %ax
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - rdseedl %eax
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - rdseedq %rax
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-sha.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-sha.s
new file mode 100644
index 0000000000000..360a667edfaa7
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-sha.s
@@ -0,0 +1,93 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+sha1msg1 %xmm0, %xmm2
+sha1msg1 (%rax), %xmm2
+
+sha1msg2 %xmm0, %xmm2
+sha1msg2 (%rax), %xmm2
+
+sha1nexte %xmm0, %xmm2
+sha1nexte (%rax), %xmm2
+
+sha1rnds4 $3, %xmm0, %xmm2
+sha1rnds4 $3, (%rax), %xmm2
+
+sha256msg1 %xmm0, %xmm2
+sha256msg1 (%rax), %xmm2
+
+sha256msg2 %xmm0, %xmm2
+sha256msg2 (%rax), %xmm2
+
+sha256rnds2 %xmm0, %xmm2
+sha256rnds2 (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 2 2 0.50 sha1msg1 %xmm0, %xmm2
+# CHECK-NEXT: 2 6 0.50 * sha1msg1 (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 sha1msg2 %xmm0, %xmm2
+# CHECK-NEXT: 1 5 0.50 * sha1msg2 (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 sha1nexte %xmm0, %xmm2
+# CHECK-NEXT: 1 5 0.50 * sha1nexte (%rax), %xmm2
+# CHECK-NEXT: 1 6 2.00 sha1rnds4 $3, %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * sha1rnds4 $3, (%rax), %xmm2
+# CHECK-NEXT: 2 2 0.75 sha256msg1 %xmm0, %xmm2
+# CHECK-NEXT: 2 6 0.75 * sha256msg1 (%rax), %xmm2
+# CHECK-NEXT: 4 3 2.00 sha256msg2 %xmm0, %xmm2
+# CHECK-NEXT: 5 7 2.00 * sha256msg2 (%rax), %xmm2
+# CHECK-NEXT: 1 4 2.00 sha256rnds2 %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * sha256rnds2 %xmm0, (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: 1.67 1.67 1.67 - - - - - 13.50 12.50 12.50 13.50 1.00 1.00 - 2.33 2.33 2.33 2.33 2.33 2.33 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - sha1msg1 %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - sha1msg1 (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - sha1msg2 %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - sha1msg2 (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - sha1nexte %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - sha1nexte (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 2.00 2.00 2.00 - - - - - - - - - - - sha1rnds4 $3, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - sha1rnds4 $3, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.75 0.75 0.75 0.75 - - - - - - - - - - - sha256msg1 %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.75 0.75 0.75 0.75 - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - sha256msg1 (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 2.00 2.00 2.00 - - - - - - - - - - - sha256msg2 %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 2.00 2.00 2.00 - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - sha256msg2 (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 2.00 2.00 2.00 - - - - - - - - - - - sha256rnds2 %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - sha256rnds2 %xmm0, (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-sse1.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-sse1.s
new file mode 100644
index 0000000000000..2f8a4bc29ad35
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-sse1.s
@@ -0,0 +1,476 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+addps %xmm0, %xmm2
+addps (%rax), %xmm2
+
+addss %xmm0, %xmm2
+addss (%rax), %xmm2
+
+andnps %xmm0, %xmm2
+andnps (%rax), %xmm2
+
+andps %xmm0, %xmm2
+andps (%rax), %xmm2
+
+cmpps $0, %xmm0, %xmm2
+cmpps $0, (%rax), %xmm2
+
+cmpss $0, %xmm0, %xmm2
+cmpss $0, (%rax), %xmm2
+
+comiss %xmm0, %xmm1
+comiss (%rax), %xmm1
+
+cvtpi2ps %mm0, %xmm2
+cvtpi2ps (%rax), %xmm2
+
+cvtps2pi %xmm0, %mm2
+cvtps2pi (%rax), %mm2
+
+cvtsi2ss %ecx, %xmm2
+cvtsi2ss %rcx, %xmm2
+cvtsi2ss (%rax), %xmm2
+cvtsi2ss (%rax), %xmm2
+
+cvtss2si %xmm0, %ecx
+cvtss2si %xmm0, %rcx
+cvtss2si (%rax), %ecx
+cvtss2si (%rax), %rcx
+
+cvttps2pi %xmm0, %mm2
+cvttps2pi (%rax), %mm2
+
+cvttss2si %xmm0, %ecx
+cvttss2si %xmm0, %rcx
+cvttss2si (%rax), %ecx
+cvttss2si (%rax), %rcx
+
+divps %xmm0, %xmm2
+divps (%rax), %xmm2
+
+divss %xmm0, %xmm2
+divss (%rax), %xmm2
+
+ldmxcsr (%rax)
+
+maskmovq %mm0, %mm1
+
+maxps %xmm0, %xmm2
+maxps (%rax), %xmm2
+
+maxss %xmm0, %xmm2
+maxss (%rax), %xmm2
+
+minps %xmm0, %xmm2
+minps (%rax), %xmm2
+
+minss %xmm0, %xmm2
+minss (%rax), %xmm2
+
+movaps %xmm0, %xmm2
+movaps %xmm0, (%rax)
+movaps (%rax), %xmm2
+
+movhlps %xmm0, %xmm2
+movlhps %xmm0, %xmm2
+
+movhps %xmm0, (%rax)
+movhps (%rax), %xmm2
+
+movlps %xmm0, (%rax)
+movlps (%rax), %xmm2
+
+movmskps %xmm0, %rcx
+
+movntps %xmm0, (%rax)
+movntq %mm0, (%rax)
+
+movss %xmm0, %xmm2
+movss %xmm0, (%rax)
+movss (%rax), %xmm2
+
+movups %xmm0, %xmm2
+movups %xmm0, (%rax)
+movups (%rax), %xmm2
+
+mulps %xmm0, %xmm2
+mulps (%rax), %xmm2
+
+mulss %xmm0, %xmm2
+mulss (%rax), %xmm2
+
+orps %xmm0, %xmm2
+orps (%rax), %xmm2
+
+pavgb %mm0, %mm2
+pavgb (%rax), %mm2
+
+pavgw %mm0, %mm2
+pavgw (%rax), %mm2
+
+pextrw $1, %mm0, %rcx
+
+pinsrw $1, %rax, %mm2
+pinsrw $1, (%rax), %mm2
+
+pmaxsw %mm0, %mm2
+pmaxsw (%rax), %mm2
+
+pmaxub %mm0, %mm2
+pmaxub (%rax), %mm2
+
+pminsw %mm0, %mm2
+pminsw (%rax), %mm2
+
+pminub %mm0, %mm2
+pminub (%rax), %mm2
+
+pmovmskb %mm0, %rcx
+
+pmulhuw %mm0, %mm2
+pmulhuw (%rax), %mm2
+
+prefetcht0 (%rax)
+prefetcht1 (%rax)
+prefetcht2 (%rax)
+prefetchnta (%rax)
+
+psadbw %mm0, %mm2
+psadbw (%rax), %mm2
+
+pshufw $1, %mm0, %mm2
+pshufw $1, (%rax), %mm2
+
+rcpps %xmm0, %xmm2
+rcpps (%rax), %xmm2
+
+rcpss %xmm0, %xmm2
+rcpss (%rax), %xmm2
+
+rsqrtps %xmm0, %xmm2
+rsqrtps (%rax), %xmm2
+
+rsqrtss %xmm0, %xmm2
+rsqrtss (%rax), %xmm2
+
+sfence
+
+shufps $1, %xmm0, %xmm2
+shufps $1, (%rax), %xmm2
+
+sqrtps %xmm0, %xmm2
+sqrtps (%rax), %xmm2
+
+sqrtss %xmm0, %xmm2
+sqrtss (%rax), %xmm2
+
+stmxcsr (%rax)
+
+subps %xmm0, %xmm2
+subps (%rax), %xmm2
+
+subss %xmm0, %xmm2
+subss (%rax), %xmm2
+
+ucomiss %xmm0, %xmm1
+ucomiss (%rax), %xmm1
+
+unpckhps %xmm0, %xmm2
+unpckhps (%rax), %xmm2
+
+unpcklps %xmm0, %xmm2
+unpcklps (%rax), %xmm2
+
+xorps %xmm0, %xmm2
+xorps (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 addps %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * addps (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 addss %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * addss (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 andnps %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * andnps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 andps %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * andps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 cmpeqps %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * cmpeqps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 cmpeqss %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * cmpeqss (%rax), %xmm2
+# CHECK-NEXT: 2 4 1.00 comiss %xmm0, %xmm1
+# CHECK-NEXT: 2 11 1.00 * comiss (%rax), %xmm1
+# CHECK-NEXT: 2 3 0.50 cvtpi2ps %mm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * cvtpi2ps (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 cvtps2pi %xmm0, %mm2
+# CHECK-NEXT: 1 10 0.50 * cvtps2pi (%rax), %mm2
+# CHECK-NEXT: 2 4 1.00 cvtsi2ss %ecx, %xmm2
+# CHECK-NEXT: 2 4 1.00 cvtsi2ss %rcx, %xmm2
+# CHECK-NEXT: 1 10 1.00 * cvtsi2ssl (%rax), %xmm2
+# CHECK-NEXT: 1 10 1.00 * cvtsi2ssl (%rax), %xmm2
+# CHECK-NEXT: 2 2 1.00 cvtss2si %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 cvtss2si %xmm0, %rcx
+# CHECK-NEXT: 2 9 1.00 * cvtss2si (%rax), %ecx
+# CHECK-NEXT: 2 9 1.00 * cvtss2si (%rax), %rcx
+# CHECK-NEXT: 1 3 0.50 cvttps2pi %xmm0, %mm2
+# CHECK-NEXT: 1 10 0.50 * cvttps2pi (%rax), %mm2
+# CHECK-NEXT: 2 2 1.00 cvttss2si %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 cvttss2si %xmm0, %rcx
+# CHECK-NEXT: 2 9 1.00 * cvttss2si (%rax), %ecx
+# CHECK-NEXT: 2 9 1.00 * cvttss2si (%rax), %rcx
+# CHECK-NEXT: 1 11 3.00 divps %xmm0, %xmm2
+# CHECK-NEXT: 1 18 3.00 * divps (%rax), %xmm2
+# CHECK-NEXT: 1 11 3.00 divss %xmm0, %xmm2
+# CHECK-NEXT: 1 18 3.00 * divss (%rax), %xmm2
+# CHECK-NEXT: 1 5 1.50 * * U ldmxcsr (%rax)
+# CHECK-NEXT: 1 1 0.50 * * U maskmovq %mm0, %mm1
+# CHECK-NEXT: 1 1 0.50 maxps %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * maxps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 maxss %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * maxss (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 minps %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * minps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 minss %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * minss (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 movaps %xmm0, %xmm2
+# CHECK-NEXT: 1 1 1.00 * movaps %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * movaps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 movhlps %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.50 movlhps %xmm0, %xmm2
+# CHECK-NEXT: 2 2 1.00 * movhps %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * movhps (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 * movlps %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * movlps (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 movmskps %xmm0, %ecx
+# CHECK-NEXT: 1 1 1.00 * movntps %xmm0, (%rax)
+# CHECK-NEXT: 1 1 1.00 * * U movntq %mm0, (%rax)
+# CHECK-NEXT: 1 1 0.50 movss %xmm0, %xmm2
+# CHECK-NEXT: 1 1 1.00 * movss %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * movss (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 movups %xmm0, %xmm2
+# CHECK-NEXT: 1 1 1.00 * movups %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * movups (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 mulps %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * mulps (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 mulss %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * mulss (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 orps %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * orps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pavgb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pavgb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 pavgw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pavgw (%rax), %mm2
+# CHECK-NEXT: 2 1 1.00 pextrw $1, %mm0, %ecx
+# CHECK-NEXT: 2 2 1.00 pinsrw $1, %eax, %mm2
+# CHECK-NEXT: 1 8 1.50 * pinsrw $1, (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pmaxsw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pmaxsw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pmaxub %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pmaxub (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pminsw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pminsw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pminub %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pminub (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 pmovmskb %mm0, %ecx
+# CHECK-NEXT: 1 3 0.50 pmulhuw %mm0, %mm2
+# CHECK-NEXT: 1 10 0.50 * pmulhuw (%rax), %mm2
+# CHECK-NEXT: 1 5 0.33 * * prefetcht0 (%rax)
+# CHECK-NEXT: 1 5 0.33 * * prefetcht1 (%rax)
+# CHECK-NEXT: 1 5 0.33 * * prefetcht2 (%rax)
+# CHECK-NEXT: 1 5 0.33 * * prefetchnta (%rax)
+# CHECK-NEXT: 1 3 0.50 psadbw %mm0, %mm2
+# CHECK-NEXT: 1 10 0.50 * psadbw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 pshufw $1, %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pshufw $1, (%rax), %mm2
+# CHECK-NEXT: 1 3 0.50 rcpps %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * rcpps (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 rcpss %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * rcpss (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.00 rsqrtps %xmm0, %xmm2
+# CHECK-NEXT: 1 10 1.00 * rsqrtps (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.00 rsqrtss %xmm0, %xmm2
+# CHECK-NEXT: 1 10 1.00 * rsqrtss (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 * * U sfence
+# CHECK-NEXT: 1 1 0.50 shufps $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * shufps $1, (%rax), %xmm2
+# CHECK-NEXT: 1 15 5.00 sqrtps %xmm0, %xmm2
+# CHECK-NEXT: 1 22 5.00 * sqrtps (%rax), %xmm2
+# CHECK-NEXT: 1 15 5.00 sqrtss %xmm0, %xmm2
+# CHECK-NEXT: 1 22 5.00 * sqrtss (%rax), %xmm2
+# CHECK-NEXT: 2 2 15.00 * U stmxcsr (%rax)
+# CHECK-NEXT: 1 3 0.50 subps %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * subps (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 subss %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * subss (%rax), %xmm2
+# CHECK-NEXT: 2 4 1.00 ucomiss %xmm0, %xmm1
+# CHECK-NEXT: 2 11 1.00 * ucomiss (%rax), %xmm1
+# CHECK-NEXT: 1 1 0.50 unpckhps %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * unpckhps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 unpcklps %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * unpcklps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 xorps %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * xorps (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: 2.00 2.00 2.00 16.50 16.50 16.50 16.50 - 22.00 64.00 34.00 26.00 33.00 33.00 7.00 22.33 22.33 22.33 19.33 19.33 19.33 4.00 4.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - addps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - addps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - addss %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - addss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - andnps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - andnps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - andps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - andps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - cmpeqps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmpeqps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - cmpeqss %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmpeqss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - comiss %xmm0, %xmm1
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - comiss (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - cvtpi2ps %mm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - cvtpi2ps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - cvtps2pi %xmm0, %mm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - cvtps2pi (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - cvtsi2ss %ecx, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - cvtsi2ss %rcx, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - cvtsi2ssl (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - cvtsi2ssl (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - cvtss2si %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - cvtss2si %xmm0, %rcx
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - cvtss2si (%rax), %ecx
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - cvtss2si (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - cvttps2pi %xmm0, %mm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - cvttps2pi (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - cvttss2si %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - cvttss2si %xmm0, %rcx
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - cvttss2si (%rax), %ecx
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - cvttss2si (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - - - - - - - - - - - divps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 3.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - divps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - - - - - - - - - - - divss %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 3.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - divss (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 1.50 1.50 1.50 1.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - ldmxcsr (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - maskmovq %mm0, %mm1
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - maxps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - maxps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - maxss %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - maxss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - minps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - minps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - minss %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - minss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - movaps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 movaps %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - movaps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - movhlps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - movlhps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 movhps %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - movhps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 movlps %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - movlps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - - - - movmskps %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 movntps %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 movntq %mm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - movss %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 movss %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - movss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - movups %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 movups %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - movups (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - mulps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - mulps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - mulss %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - mulss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - orps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - orps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - pavgb %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pavgb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - pavgw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pavgw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - pextrw $1, %mm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - pinsrw $1, %eax, %mm2
+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pinsrw $1, (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pmaxsw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pmaxsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pmaxub %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pmaxub (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pminsw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pminsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pminub %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pminub (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - - - - pmovmskb %mm0, %ecx
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 - - - - - - - - - - - pmulhuw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pmulhuw (%rax), %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - prefetcht0 (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - prefetcht1 (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - prefetcht2 (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - prefetchnta (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - psadbw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - psadbw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - pshufw $1, %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pshufw $1, (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - rcpps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - rcpps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - rcpss %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - rcpss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - - - - rsqrtps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - rsqrtps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - - - - rsqrtss %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - rsqrtss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - - sfence
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - shufps $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - shufps $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 5.00 - - - - - - - - - - - - - sqrtps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 5.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - sqrtps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 5.00 - - - - - - - - - - - - - sqrtss %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 5.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - sqrtss (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 15.00 15.00 15.00 15.00 - - - - - - - - 0.33 0.33 0.33 - - - 0.50 0.50 stmxcsr (%rax)
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - subps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - subps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - subss %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - subss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - ucomiss %xmm0, %xmm1
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - ucomiss (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - unpckhps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - unpckhps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - unpcklps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - unpcklps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - xorps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - xorps (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-sse2.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-sse2.s
new file mode 100644
index 0000000000000..31100eb177e07
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-sse2.s
@@ -0,0 +1,975 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+addpd %xmm0, %xmm2
+addpd (%rax), %xmm2
+
+addsd %xmm0, %xmm2
+addsd (%rax), %xmm2
+
+andnpd %xmm0, %xmm2
+andnpd (%rax), %xmm2
+
+andpd %xmm0, %xmm2
+andpd (%rax), %xmm2
+
+clflush (%rax)
+
+cmppd $0, %xmm0, %xmm2
+cmppd $0, (%rax), %xmm2
+
+cmpsd $0, %xmm0, %xmm2
+cmpsd $0, (%rax), %xmm2
+
+comisd %xmm0, %xmm1
+comisd (%rax), %xmm1
+
+cvtdq2pd %xmm0, %xmm2
+cvtdq2pd (%rax), %xmm2
+
+cvtdq2ps %xmm0, %xmm2
+cvtdq2ps (%rax), %xmm2
+
+cvtpd2dq %xmm0, %xmm2
+cvtpd2dq (%rax), %xmm2
+
+cvtpd2pi %xmm0, %mm2
+cvtpd2pi (%rax), %mm2
+
+cvtpd2ps %xmm0, %xmm2
+cvtpd2ps (%rax), %xmm2
+
+cvtpi2pd %mm0, %xmm2
+cvtpi2pd (%rax), %xmm2
+
+cvtps2dq %xmm0, %xmm2
+cvtps2dq (%rax), %xmm2
+
+cvtps2pd %xmm0, %xmm2
+cvtps2pd (%rax), %xmm2
+
+cvtsd2si %xmm0, %ecx
+cvtsd2si %xmm0, %rcx
+cvtsd2si (%rax), %ecx
+cvtsd2si (%rax), %rcx
+
+cvtsd2ss %xmm0, %xmm2
+cvtsd2ss (%rax), %xmm2
+
+cvtsi2sd %ecx, %xmm2
+cvtsi2sd %rcx, %xmm2
+cvtsi2sd (%rax), %xmm2
+cvtsi2sd (%rax), %xmm2
+
+cvtss2sd %xmm0, %xmm2
+cvtss2sd (%rax), %xmm2
+
+cvttpd2dq %xmm0, %xmm2
+cvttpd2dq (%rax), %xmm2
+
+cvttpd2pi %xmm0, %mm2
+cvttpd2pi (%rax), %mm2
+
+cvttps2dq %xmm0, %xmm2
+cvttps2dq (%rax), %xmm2
+
+cvttsd2si %xmm0, %ecx
+cvttsd2si %xmm0, %rcx
+cvttsd2si (%rax), %ecx
+cvttsd2si (%rax), %rcx
+
+divpd %xmm0, %xmm2
+divpd (%rax), %xmm2
+
+divsd %xmm0, %xmm2
+divsd (%rax), %xmm2
+
+lfence
+
+maskmovdqu %xmm0, %xmm1
+
+maxpd %xmm0, %xmm2
+maxpd (%rax), %xmm2
+
+maxsd %xmm0, %xmm2
+maxsd (%rax), %xmm2
+
+mfence
+
+minpd %xmm0, %xmm2
+minpd (%rax), %xmm2
+
+minsd %xmm0, %xmm2
+minsd (%rax), %xmm2
+
+movapd %xmm0, %xmm2
+movapd %xmm0, (%rax)
+movapd (%rax), %xmm2
+
+movd %eax, %xmm2
+movd (%rax), %xmm2
+
+movd %xmm0, %ecx
+movd %xmm0, (%rax)
+
+movdqa %xmm0, %xmm2
+movdqa %xmm0, (%rax)
+movdqa (%rax), %xmm2
+
+movdqu %xmm0, %xmm2
+movdqu %xmm0, (%rax)
+movdqu (%rax), %xmm2
+
+movdq2q %xmm0, %mm2
+
+movhpd %xmm0, (%rax)
+movhpd (%rax), %xmm2
+
+movlpd %xmm0, (%rax)
+movlpd (%rax), %xmm2
+
+movmskpd %xmm0, %rcx
+
+movntil %eax, (%rax)
+movntiq %rax, (%rax)
+
+movntdq %xmm0, (%rax)
+movntpd %xmm0, (%rax)
+
+movq %xmm0, %xmm2
+
+movq %rax, %xmm2
+movq (%rax), %xmm2
+
+movq %xmm0, %rcx
+movq %xmm0, (%rax)
+
+movq2dq %mm0, %xmm2
+
+movsd %xmm0, %xmm2
+movsd %xmm0, (%rax)
+movsd (%rax), %xmm2
+
+movupd %xmm0, %xmm2
+movupd %xmm0, (%rax)
+movupd (%rax), %xmm2
+
+mulpd %xmm0, %xmm2
+mulpd (%rax), %xmm2
+
+mulsd %xmm0, %xmm2
+mulsd (%rax), %xmm2
+
+orpd %xmm0, %xmm2
+orpd (%rax), %xmm2
+
+packssdw %xmm0, %xmm2
+packssdw (%rax), %xmm2
+
+packsswb %xmm0, %xmm2
+packsswb (%rax), %xmm2
+
+packuswb %xmm0, %xmm2
+packuswb (%rax), %xmm2
+
+paddb %xmm0, %xmm2
+paddb (%rax), %xmm2
+
+paddd %xmm0, %xmm2
+paddd (%rax), %xmm2
+
+paddq %mm0, %mm2
+paddq (%rax), %mm2
+
+paddq %xmm0, %xmm2
+paddq (%rax), %xmm2
+
+paddsb %xmm0, %xmm2
+paddsb (%rax), %xmm2
+
+paddsw %xmm0, %xmm2
+paddsw (%rax), %xmm2
+
+paddusb %xmm0, %xmm2
+paddusb (%rax), %xmm2
+
+paddusw %xmm0, %xmm2
+paddusw (%rax), %xmm2
+
+paddw %xmm0, %xmm2
+paddw (%rax), %xmm2
+
+pand %xmm0, %xmm2
+pand (%rax), %xmm2
+
+pandn %xmm0, %xmm2
+pandn (%rax), %xmm2
+
+pavgb %xmm0, %xmm2
+pavgb (%rax), %xmm2
+
+pavgw %xmm0, %xmm2
+pavgw (%rax), %xmm2
+
+pcmpeqb %xmm0, %xmm2
+pcmpeqb (%rax), %xmm2
+
+pcmpeqd %xmm0, %xmm2
+pcmpeqd (%rax), %xmm2
+
+pcmpeqw %xmm0, %xmm2
+pcmpeqw (%rax), %xmm2
+
+pcmpgtb %xmm0, %xmm2
+pcmpgtb (%rax), %xmm2
+
+pcmpgtd %xmm0, %xmm2
+pcmpgtd (%rax), %xmm2
+
+pcmpgtw %xmm0, %xmm2
+pcmpgtw (%rax), %xmm2
+
+pextrw $1, %xmm0, %rcx
+
+pinsrw $1, %rax, %xmm0
+pinsrw $1, (%rax), %xmm0
+
+pmaddwd %xmm0, %xmm2
+pmaddwd (%rax), %xmm2
+
+pmaxsw %xmm0, %xmm2
+pmaxsw (%rax), %xmm2
+
+pmaxub %xmm0, %xmm2
+pmaxub (%rax), %xmm2
+
+pminsw %xmm0, %xmm2
+pminsw (%rax), %xmm2
+
+pminub %xmm0, %xmm2
+pminub (%rax), %xmm2
+
+pmovmskb %xmm0, %rcx
+
+pmulhuw %xmm0, %xmm2
+pmulhuw (%rax), %xmm2
+
+pmulhw %xmm0, %xmm2
+pmulhw (%rax), %xmm2
+
+pmullw %xmm0, %xmm2
+pmullw (%rax), %xmm2
+
+pmuludq %mm0, %mm2
+pmuludq (%rax), %mm2
+
+pmuludq %xmm0, %xmm2
+pmuludq (%rax), %xmm2
+
+por %xmm0, %xmm2
+por (%rax), %xmm2
+
+psadbw %xmm0, %xmm2
+psadbw (%rax), %xmm2
+
+pshufd $1, %xmm0, %xmm2
+pshufd $1, (%rax), %xmm2
+
+pshufhw $1, %xmm0, %xmm2
+pshufhw $1, (%rax), %xmm2
+
+pshuflw $1, %xmm0, %xmm2
+pshuflw $1, (%rax), %xmm2
+
+pslld $1, %xmm2
+pslld %xmm0, %xmm2
+pslld (%rax), %xmm2
+
+pslldq $1, %xmm2
+
+psllq $1, %xmm2
+psllq %xmm0, %xmm2
+psllq (%rax), %xmm2
+
+psllw $1, %xmm2
+psllw %xmm0, %xmm2
+psllw (%rax), %xmm2
+
+psrad $1, %xmm2
+psrad %xmm0, %xmm2
+psrad (%rax), %xmm2
+
+psraw $1, %xmm2
+psraw %xmm0, %xmm2
+psraw (%rax), %xmm2
+
+psrld $1, %xmm2
+psrld %xmm0, %xmm2
+psrld (%rax), %xmm2
+
+psrldq $1, %xmm2
+
+psrlq $1, %xmm2
+psrlq %xmm0, %xmm2
+psrlq (%rax), %xmm2
+
+psrlw $1, %xmm2
+psrlw %xmm0, %xmm2
+psrlw (%rax), %xmm2
+
+psubb %xmm0, %xmm2
+psubb (%rax), %xmm2
+
+psubd %xmm0, %xmm2
+psubd (%rax), %xmm2
+
+psubq %mm0, %mm2
+psubq (%rax), %mm2
+
+psubq %xmm0, %xmm2
+psubq (%rax), %xmm2
+
+psubsb %xmm0, %xmm2
+psubsb (%rax), %xmm2
+
+psubsw %xmm0, %xmm2
+psubsw (%rax), %xmm2
+
+psubusb %xmm0, %xmm2
+psubusb (%rax), %xmm2
+
+psubusw %xmm0, %xmm2
+psubusw (%rax), %xmm2
+
+psubw %xmm0, %xmm2
+psubw (%rax), %xmm2
+
+punpckhbw %xmm0, %xmm2
+punpckhbw (%rax), %xmm2
+
+punpckhdq %xmm0, %xmm2
+punpckhdq (%rax), %xmm2
+
+punpckhqdq %xmm0, %xmm2
+punpckhqdq (%rax), %xmm2
+
+punpckhwd %xmm0, %xmm2
+punpckhwd (%rax), %xmm2
+
+punpcklbw %xmm0, %xmm2
+punpcklbw (%rax), %xmm2
+
+punpckldq %xmm0, %xmm2
+punpckldq (%rax), %xmm2
+
+punpcklqdq %xmm0, %xmm2
+punpcklqdq (%rax), %xmm2
+
+punpcklwd %xmm0, %xmm2
+punpcklwd (%rax), %xmm2
+
+pxor %xmm0, %xmm2
+pxor (%rax), %xmm2
+
+shufpd $1, %xmm0, %xmm2
+shufpd $1, (%rax), %xmm2
+
+sqrtpd %xmm0, %xmm2
+sqrtpd (%rax), %xmm2
+
+sqrtsd %xmm0, %xmm2
+sqrtsd (%rax), %xmm2
+
+subpd %xmm0, %xmm2
+subpd (%rax), %xmm2
+
+subsd %xmm0, %xmm2
+subsd (%rax), %xmm2
+
+ucomisd %xmm0, %xmm1
+ucomisd (%rax), %xmm1
+
+unpckhpd %xmm0, %xmm2
+unpckhpd (%rax), %xmm2
+
+unpcklpd %xmm0, %xmm2
+unpcklpd (%rax), %xmm2
+
+xorpd %xmm0, %xmm2
+xorpd (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 addpd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * addpd (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 addsd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * addsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 andnpd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * andnpd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 andpd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * andpd (%rax), %xmm2
+# CHECK-NEXT: 1 5 0.33 * * U clflush (%rax)
+# CHECK-NEXT: 1 1 0.50 cmpeqpd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * cmpeqpd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 cmpeqsd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * cmpeqsd (%rax), %xmm2
+# CHECK-NEXT: 2 4 1.00 comisd %xmm0, %xmm1
+# CHECK-NEXT: 2 11 1.00 * comisd (%rax), %xmm1
+# CHECK-NEXT: 1 3 0.50 cvtdq2pd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * cvtdq2pd (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 cvtdq2ps %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * cvtdq2ps (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 cvtpd2dq %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * cvtpd2dq (%rax), %xmm2
+# CHECK-NEXT: 2 1 1.00 cvtpd2pi %xmm0, %mm2
+# CHECK-NEXT: 2 1 1.00 * cvtpd2pi (%rax), %mm2
+# CHECK-NEXT: 1 3 0.50 cvtpd2ps %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * cvtpd2ps (%rax), %xmm2
+# CHECK-NEXT: 2 2 3.00 cvtpi2pd %mm0, %xmm2
+# CHECK-NEXT: 2 2 3.00 * cvtpi2pd (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 cvtps2dq %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * cvtps2dq (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 cvtps2pd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * cvtps2pd (%rax), %xmm2
+# CHECK-NEXT: 2 2 1.00 cvtsd2si %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 cvtsd2si %xmm0, %rcx
+# CHECK-NEXT: 2 9 1.00 * cvtsd2si (%rax), %ecx
+# CHECK-NEXT: 2 9 1.00 * cvtsd2si (%rax), %rcx
+# CHECK-NEXT: 1 3 0.50 cvtsd2ss %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * cvtsd2ss (%rax), %xmm2
+# CHECK-NEXT: 2 4 1.00 cvtsi2sd %ecx, %xmm2
+# CHECK-NEXT: 2 4 1.00 cvtsi2sd %rcx, %xmm2
+# CHECK-NEXT: 1 10 1.00 * cvtsi2sdl (%rax), %xmm2
+# CHECK-NEXT: 1 10 1.00 * cvtsi2sdl (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 cvtss2sd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * cvtss2sd (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 cvttpd2dq %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * cvttpd2dq (%rax), %xmm2
+# CHECK-NEXT: 2 1 1.00 cvttpd2pi %xmm0, %mm2
+# CHECK-NEXT: 2 1 1.00 * cvttpd2pi (%rax), %mm2
+# CHECK-NEXT: 1 3 0.50 cvttps2dq %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * cvttps2dq (%rax), %xmm2
+# CHECK-NEXT: 2 2 1.00 cvttsd2si %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 cvttsd2si %xmm0, %rcx
+# CHECK-NEXT: 2 9 1.00 * cvttsd2si (%rax), %ecx
+# CHECK-NEXT: 2 9 1.00 * cvttsd2si (%rax), %rcx
+# CHECK-NEXT: 1 13 5.00 divpd %xmm0, %xmm2
+# CHECK-NEXT: 1 20 5.00 * divpd (%rax), %xmm2
+# CHECK-NEXT: 1 13 5.00 divsd %xmm0, %xmm2
+# CHECK-NEXT: 1 20 5.00 * divsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 10.00 * * U lfence
+# CHECK-NEXT: 1 1 1.00 * * U maskmovdqu %xmm0, %xmm1
+# CHECK-NEXT: 1 1 0.50 maxpd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * maxpd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 maxsd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * maxsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 25.00 * * U mfence
+# CHECK-NEXT: 1 1 0.50 minpd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * minpd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 minsd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * minsd (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 movapd %xmm0, %xmm2
+# CHECK-NEXT: 1 1 1.00 * movapd %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * movapd (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 movd %eax, %xmm2
+# CHECK-NEXT: 1 8 0.50 * movd (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 movd %xmm0, %ecx
+# CHECK-NEXT: 1 1 1.00 * movd %xmm0, (%rax)
+# CHECK-NEXT: 1 0 0.25 movdqa %xmm0, %xmm2
+# CHECK-NEXT: 1 1 1.00 * movdqa %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * movdqa (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 movdqu %xmm0, %xmm2
+# CHECK-NEXT: 1 1 1.00 * movdqu %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * movdqu (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 movdq2q %xmm0, %mm2
+# CHECK-NEXT: 2 2 1.00 * movhpd %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * movhpd (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 * movlpd %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * movlpd (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 movmskpd %xmm0, %ecx
+# CHECK-NEXT: 1 1 1.00 * movntil %eax, (%rax)
+# CHECK-NEXT: 1 1 1.00 * movntiq %rax, (%rax)
+# CHECK-NEXT: 1 1 1.00 * movntdq %xmm0, (%rax)
+# CHECK-NEXT: 1 1 1.00 * movntpd %xmm0, (%rax)
+# CHECK-NEXT: 1 1 0.25 movq %xmm0, %xmm2
+# CHECK-NEXT: 1 1 1.00 movq %rax, %xmm2
+# CHECK-NEXT: 1 8 0.50 * movq (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 movq %xmm0, %rcx
+# CHECK-NEXT: 1 1 1.00 * movq %xmm0, (%rax)
+# CHECK-NEXT: 2 1 0.50 movq2dq %mm0, %xmm2
+# CHECK-NEXT: 1 1 0.50 movsd %xmm0, %xmm2
+# CHECK-NEXT: 1 1 1.00 * movsd %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * movsd (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 movupd %xmm0, %xmm2
+# CHECK-NEXT: 1 1 1.00 * movupd %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * movupd (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 mulpd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * mulpd (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 mulsd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * mulsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 orpd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * orpd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 packssdw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * packssdw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 packsswb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * packsswb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 packuswb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * packuswb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 paddb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * paddb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 paddd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * paddd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 paddq %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * paddq (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 paddq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * paddq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 paddsb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * paddsb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 paddsw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * paddsw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 paddusb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * paddusb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 paddusw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * paddusw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 paddw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * paddw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pand %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pand (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pandn %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pandn (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pavgb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pavgb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pavgw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pavgw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pcmpeqb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pcmpeqb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pcmpeqd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pcmpeqd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pcmpeqw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pcmpeqw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pcmpgtb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pcmpgtb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pcmpgtd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pcmpgtd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pcmpgtw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pcmpgtw (%rax), %xmm2
+# CHECK-NEXT: 2 1 1.00 pextrw $1, %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 pinsrw $1, %eax, %xmm0
+# CHECK-NEXT: 1 8 1.50 * pinsrw $1, (%rax), %xmm0
+# CHECK-NEXT: 1 3 0.50 pmaddwd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * pmaddwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pmaxsw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmaxsw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pmaxub %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmaxub (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pminsw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pminsw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pminub %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pminub (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 pmovmskb %xmm0, %ecx
+# CHECK-NEXT: 1 3 0.50 pmulhuw %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * pmulhuw (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 pmulhw %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * pmulhw (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 pmullw %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * pmullw (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 pmuludq %mm0, %mm2
+# CHECK-NEXT: 1 10 0.50 * pmuludq (%rax), %mm2
+# CHECK-NEXT: 1 3 0.50 pmuludq %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * pmuludq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 por %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * por (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 psadbw %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * psadbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pshufd $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pshufd $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pshufhw $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pshufhw $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pshuflw $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pshuflw $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pslld $1, %xmm2
+# CHECK-NEXT: 1 1 0.50 pslld %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pslld (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pslldq $1, %xmm2
+# CHECK-NEXT: 1 1 0.50 psllq $1, %xmm2
+# CHECK-NEXT: 1 1 0.50 psllq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psllq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psllw $1, %xmm2
+# CHECK-NEXT: 1 1 0.50 psllw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psllw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psrad $1, %xmm2
+# CHECK-NEXT: 1 1 0.50 psrad %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psrad (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psraw $1, %xmm2
+# CHECK-NEXT: 1 1 0.50 psraw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psraw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psrld $1, %xmm2
+# CHECK-NEXT: 1 1 0.50 psrld %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psrld (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psrldq $1, %xmm2
+# CHECK-NEXT: 1 1 0.50 psrlq $1, %xmm2
+# CHECK-NEXT: 1 1 0.50 psrlq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psrlq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psrlw $1, %xmm2
+# CHECK-NEXT: 1 1 0.50 psrlw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psrlw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 psubb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psubb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 psubd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psubd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 psubq %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psubq (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 psubq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psubq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psubsb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psubsb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psubsw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psubsw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psubusb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psubusb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psubusw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psubusw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 psubw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psubw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpckhbw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * punpckhbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpckhdq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * punpckhdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpckhqdq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * punpckhqdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpckhwd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * punpckhwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpcklbw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * punpcklbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpckldq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * punpckldq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpcklqdq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * punpcklqdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpcklwd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * punpcklwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pxor %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pxor (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 shufpd $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * shufpd $1, (%rax), %xmm2
+# CHECK-NEXT: 1 21 9.00 sqrtpd %xmm0, %xmm2
+# CHECK-NEXT: 1 28 9.00 * sqrtpd (%rax), %xmm2
+# CHECK-NEXT: 1 21 9.00 sqrtsd %xmm0, %xmm2
+# CHECK-NEXT: 1 28 9.00 * sqrtsd (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 subpd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * subpd (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 subsd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * subsd (%rax), %xmm2
+# CHECK-NEXT: 2 4 1.00 ucomisd %xmm0, %xmm1
+# CHECK-NEXT: 2 11 1.00 * ucomisd (%rax), %xmm1
+# CHECK-NEXT: 1 1 0.50 unpckhpd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * unpckhpd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 unpcklpd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * unpcklpd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 xorpd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * xorpd (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: 1.00 1.00 1.00 25.00 25.00 25.00 25.00 - 42.50 124.00 89.00 61.50 70.50 70.50 12.00 53.67 53.67 53.67 38.33 38.33 38.33 8.00 8.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - addpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - addpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - addsd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - addsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - andnpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - andnpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - andpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - andpd (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - clflush (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - cmpeqpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmpeqpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - cmpeqsd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmpeqsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - comisd %xmm0, %xmm1
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - comisd (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - cvtdq2pd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - cvtdq2pd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - cvtdq2ps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - cvtdq2ps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - cvtpd2dq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - cvtpd2dq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - cvtpd2pi %xmm0, %mm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - cvtpd2pi (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - cvtpd2ps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - cvtpd2ps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 3.00 3.00 - - - - - - - - - - - cvtpi2pd %mm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 3.00 3.00 - - - - - - - - - - - cvtpi2pd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - cvtps2dq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - cvtps2dq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - cvtps2pd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - cvtps2pd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - cvtsd2si %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - cvtsd2si %xmm0, %rcx
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - cvtsd2si (%rax), %ecx
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - cvtsd2si (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - cvtsd2ss %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - cvtsd2ss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - cvtsi2sd %ecx, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - cvtsi2sd %rcx, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - cvtsi2sdl (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - cvtsi2sdl (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - cvtss2sd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - cvtss2sd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - cvttpd2dq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - cvttpd2dq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - cvttpd2pi %xmm0, %mm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - cvttpd2pi (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - cvttps2dq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - cvttps2dq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - cvttsd2si %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 - - - - - - - - - - - cvttsd2si %xmm0, %rcx
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - cvttsd2si (%rax), %ecx
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - cvttsd2si (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - - 5.00 - - - - - - - - - - - - - divpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 5.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - divpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 5.00 - - - - - - - - - - - - - divsd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 5.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - divsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - 10.00 10.00 10.00 - - - - - lfence
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 maskmovdqu %xmm0, %xmm1
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - maxpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - maxpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - maxsd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - maxsd (%rax), %xmm2
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - mfence
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - minpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - minpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - minsd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - minsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - movapd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 movapd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - movapd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - movd %eax, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - movd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - movd %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 movd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - movdqa %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 movdqa %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - movdqa (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - movdqu %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 movdqu %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - movdqu (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - movdq2q %xmm0, %mm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 movhpd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - movhpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 movlpd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - movlpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - - - - movmskpd %xmm0, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.67 0.67 0.67 - - - 1.00 1.00 movntil %eax, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.67 0.67 0.67 - - - 1.00 1.00 movntiq %rax, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 movntdq %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 movntpd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - movq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - movq %rax, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - movq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - movq %xmm0, %rcx
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 movq %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 - - - - - - - - - movq2dq %mm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - movsd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 movsd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - movsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - movupd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 movupd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - movupd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - mulpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - mulpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - mulsd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - mulsd (%rax), %xmm2
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+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - subpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - subpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - subsd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - subsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - ucomisd %xmm0, %xmm1
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - ucomisd (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - unpckhpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - unpckhpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - unpcklpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - unpcklpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - xorpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - xorpd (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-sse3.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-sse3.s
new file mode 100644
index 0000000000000..8110390219c7c
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-sse3.s
@@ -0,0 +1,119 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+addsubpd %xmm0, %xmm2
+addsubpd (%rax), %xmm2
+
+addsubps %xmm0, %xmm2
+addsubps (%rax), %xmm2
+
+haddpd %xmm0, %xmm2
+haddpd (%rax), %xmm2
+
+haddps %xmm0, %xmm2
+haddps (%rax), %xmm2
+
+hsubpd %xmm0, %xmm2
+hsubpd (%rax), %xmm2
+
+hsubps %xmm0, %xmm2
+hsubps (%rax), %xmm2
+
+lddqu (%rax), %xmm2
+
+monitor
+
+movddup %xmm0, %xmm2
+movddup (%rax), %xmm2
+
+movshdup %xmm0, %xmm2
+movshdup (%rax), %xmm2
+
+movsldup %xmm0, %xmm2
+movsldup (%rax), %xmm2
+
+mwait
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 addsubpd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * addsubpd (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 addsubps %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * addsubps (%rax), %xmm2
+# CHECK-NEXT: 4 6 2.00 haddpd %xmm0, %xmm2
+# CHECK-NEXT: 4 13 2.00 * haddpd (%rax), %xmm2
+# CHECK-NEXT: 4 6 2.00 haddps %xmm0, %xmm2
+# CHECK-NEXT: 4 13 2.00 * haddps (%rax), %xmm2
+# CHECK-NEXT: 4 6 2.00 hsubpd %xmm0, %xmm2
+# CHECK-NEXT: 4 13 2.00 * hsubpd (%rax), %xmm2
+# CHECK-NEXT: 4 6 2.00 hsubps %xmm0, %xmm2
+# CHECK-NEXT: 4 13 2.00 * hsubps (%rax), %xmm2
+# CHECK-NEXT: 1 8 0.50 * lddqu (%rax), %xmm2
+# CHECK-NEXT: 100 100 25.00 U monitor
+# CHECK-NEXT: 1 1 0.50 movddup %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * movddup (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 movshdup %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * movshdup (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 movsldup %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * movsldup (%rax), %xmm2
+# CHECK-NEXT: 100 100 25.00 * * U mwait
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: - - - 50.00 50.00 50.00 50.00 - - 3.00 21.00 2.00 5.00 5.00 - 3.33 3.33 3.33 3.33 3.33 3.33 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - addsubpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - addsubpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - addsubps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - addsubps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 2.00 - - - - - - - - - - - - haddpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 2.00 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - haddpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 2.00 - - - - - - - - - - - - haddps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 2.00 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - haddps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 2.00 - - - - - - - - - - - - hsubpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 2.00 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - hsubpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 2.00 - - - - - - - - - - - - hsubps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 2.00 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - hsubps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - lddqu (%rax), %xmm2
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - monitor
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - movddup %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - movddup (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - movshdup %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - movshdup (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - movsldup %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - movsldup (%rax), %xmm2
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - mwait
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-sse41.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-sse41.s
new file mode 100644
index 0000000000000..0cc6c6a5c25ed
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-sse41.s
@@ -0,0 +1,381 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+blendpd $11, %xmm0, %xmm2
+blendpd $11, (%rax), %xmm2
+
+blendps $11, %xmm0, %xmm2
+blendps $11, (%rax), %xmm2
+
+blendvpd %xmm0, %xmm2
+blendvpd (%rax), %xmm2
+
+blendvps %xmm0, %xmm2
+blendvps (%rax), %xmm2
+
+dppd $22, %xmm0, %xmm2
+dppd $22, (%rax), %xmm2
+
+dpps $22, %xmm0, %xmm2
+dpps $22, (%rax), %xmm2
+
+extractps $1, %xmm0, %rcx
+extractps $1, %xmm0, (%rax)
+
+insertps $1, %xmm0, %xmm2
+insertps $1, (%rax), %xmm2
+
+movntdqa (%rax), %xmm2
+
+mpsadbw $1, %xmm0, %xmm2
+mpsadbw $1, (%rax), %xmm2
+
+packusdw %xmm0, %xmm2
+packusdw (%rax), %xmm2
+
+pblendvb %xmm0, %xmm2
+pblendvb (%rax), %xmm2
+
+pblendw $11, %xmm0, %xmm2
+pblendw $11, (%rax), %xmm2
+
+pcmpeqq %xmm0, %xmm2
+pcmpeqq (%rax), %xmm2
+
+pextrb $1, %xmm0, %ecx
+pextrb $1, %xmm0, (%rax)
+
+pextrd $1, %xmm0, %ecx
+pextrd $1, %xmm0, (%rax)
+
+pextrq $1, %xmm0, %rcx
+pextrq $1, %xmm0, (%rax)
+
+pextrw $1, %xmm0, (%rax)
+
+phminposuw %xmm0, %xmm2
+phminposuw (%rax), %xmm2
+
+pinsrb $1, %eax, %xmm1
+pinsrb $1, (%rax), %xmm1
+
+pinsrd $1, %eax, %xmm1
+pinsrd $1, (%rax), %xmm1
+
+pinsrq $1, %rax, %xmm1
+pinsrq $1, (%rax), %xmm1
+
+pmaxsb %xmm0, %xmm2
+pmaxsb (%rax), %xmm2
+
+pmaxsd %xmm0, %xmm2
+pmaxsd (%rax), %xmm2
+
+pmaxud %xmm0, %xmm2
+pmaxud (%rax), %xmm2
+
+pmaxuw %xmm0, %xmm2
+pmaxuw (%rax), %xmm2
+
+pminsb %xmm0, %xmm2
+pminsb (%rax), %xmm2
+
+pminsd %xmm0, %xmm2
+pminsd (%rax), %xmm2
+
+pminud %xmm0, %xmm2
+pminud (%rax), %xmm2
+
+pminuw %xmm0, %xmm2
+pminuw (%rax), %xmm2
+
+pmovsxbd %xmm0, %xmm2
+pmovsxbd (%rax), %xmm2
+
+pmovsxbq %xmm0, %xmm2
+pmovsxbq (%rax), %xmm2
+
+pmovsxbw %xmm0, %xmm2
+pmovsxbw (%rax), %xmm2
+
+pmovsxdq %xmm0, %xmm2
+pmovsxdq (%rax), %xmm2
+
+pmovsxwd %xmm0, %xmm2
+pmovsxwd (%rax), %xmm2
+
+pmovsxwq %xmm0, %xmm2
+pmovsxwq (%rax), %xmm2
+
+pmovzxbd %xmm0, %xmm2
+pmovzxbd (%rax), %xmm2
+
+pmovzxbq %xmm0, %xmm2
+pmovzxbq (%rax), %xmm2
+
+pmovzxbw %xmm0, %xmm2
+pmovzxbw (%rax), %xmm2
+
+pmovzxdq %xmm0, %xmm2
+pmovzxdq (%rax), %xmm2
+
+pmovzxwd %xmm0, %xmm2
+pmovzxwd (%rax), %xmm2
+
+pmovzxwq %xmm0, %xmm2
+pmovzxwq (%rax), %xmm2
+
+pmuldq %xmm0, %xmm2
+pmuldq (%rax), %xmm2
+
+pmulld %xmm0, %xmm2
+pmulld (%rax), %xmm2
+
+ptest %xmm0, %xmm1
+ptest (%rax), %xmm1
+
+roundpd $1, %xmm0, %xmm2
+roundpd $1, (%rax), %xmm2
+
+roundps $1, %xmm0, %xmm2
+roundps $1, (%rax), %xmm2
+
+roundsd $1, %xmm0, %xmm2
+roundsd $1, (%rax), %xmm2
+
+roundss $1, %xmm0, %xmm2
+roundss $1, (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.50 blendpd $11, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * blendpd $11, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 blendps $11, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * blendps $11, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 blendvpd %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * blendvpd %xmm0, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 blendvps %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * blendvps %xmm0, (%rax), %xmm2
+# CHECK-NEXT: 3 9 3.00 dppd $22, %xmm0, %xmm2
+# CHECK-NEXT: 5 16 3.00 * dppd $22, (%rax), %xmm2
+# CHECK-NEXT: 8 15 4.00 dpps $22, %xmm0, %xmm2
+# CHECK-NEXT: 10 22 4.00 * dpps $22, (%rax), %xmm2
+# CHECK-NEXT: 2 1 1.00 extractps $1, %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 * extractps $1, %xmm0, (%rax)
+# CHECK-NEXT: 1 1 0.50 insertps $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * insertps $1, (%rax), %xmm2
+# CHECK-NEXT: 1 8 0.50 * movntdqa (%rax), %xmm2
+# CHECK-NEXT: 4 4 2.00 mpsadbw $1, %xmm0, %xmm2
+# CHECK-NEXT: 6 11 2.00 * mpsadbw $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 packusdw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * packusdw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pblendvb %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pblendvb %xmm0, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pblendw $11, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pblendw $11, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pcmpeqq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pcmpeqq (%rax), %xmm2
+# CHECK-NEXT: 2 1 1.00 pextrb $1, %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 * pextrb $1, %xmm0, (%rax)
+# CHECK-NEXT: 2 1 1.00 pextrd $1, %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 * pextrd $1, %xmm0, (%rax)
+# CHECK-NEXT: 2 1 1.00 pextrq $1, %xmm0, %rcx
+# CHECK-NEXT: 2 2 1.00 * pextrq $1, %xmm0, (%rax)
+# CHECK-NEXT: 2 2 1.00 * pextrw $1, %xmm0, (%rax)
+# CHECK-NEXT: 1 3 0.50 phminposuw %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * phminposuw (%rax), %xmm2
+# CHECK-NEXT: 2 2 1.00 pinsrb $1, %eax, %xmm1
+# CHECK-NEXT: 1 8 1.50 * pinsrb $1, (%rax), %xmm1
+# CHECK-NEXT: 2 2 1.00 pinsrd $1, %eax, %xmm1
+# CHECK-NEXT: 1 8 1.50 * pinsrd $1, (%rax), %xmm1
+# CHECK-NEXT: 2 2 1.00 pinsrq $1, %rax, %xmm1
+# CHECK-NEXT: 1 8 1.50 * pinsrq $1, (%rax), %xmm1
+# CHECK-NEXT: 1 1 0.25 pmaxsb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmaxsb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pmaxsd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmaxsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pmaxud %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmaxud (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pmaxuw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmaxuw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pminsb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pminsb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pminsd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pminsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pminud %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pminud (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pminuw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pminuw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovsxbd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovsxbd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovsxbq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovsxbq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovsxbw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovsxbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovsxdq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovsxdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovsxwd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovsxwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovsxwq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovsxwq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovzxbd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovzxbd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovzxbq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovzxbq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovzxbw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovzxbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovzxdq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovzxdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovzxwd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovzxwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovzxwq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovzxwq (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 pmuldq %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * pmuldq (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 pmulld %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * pmulld (%rax), %xmm2
+# CHECK-NEXT: 2 1 1.00 ptest %xmm0, %xmm1
+# CHECK-NEXT: 2 8 1.00 * ptest (%rax), %xmm1
+# CHECK-NEXT: 1 3 0.50 roundpd $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * roundpd $1, (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 roundps $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * roundps $1, (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 roundsd $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * roundsd $1, (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 roundss $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * roundss $1, (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: - - - - - - - - 31.00 43.00 28.00 16.00 35.50 35.50 7.00 16.33 16.33 16.33 14.67 14.67 14.67 2.50 2.50
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - blendpd $11, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - blendpd $11, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - blendps $11, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - blendps $11, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - blendvpd %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - blendvpd %xmm0, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - blendvps %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - blendvps %xmm0, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 3.00 3.00 - - - - - - - - - - - - - dppd $22, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 3.00 3.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - dppd $22, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 4.00 4.00 - - - - - - - - - - - - - dpps $22, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 4.00 4.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - dpps $22, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - extractps $1, %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 extractps $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - insertps $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - insertps $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - movntdqa (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 2.00 2.00 2.00 - - - - - - - - - - - mpsadbw $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 2.00 2.00 2.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - mpsadbw $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - packusdw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - packusdw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 - - - - - - - - - - - pblendvb %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pblendvb %xmm0, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pblendw $11, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pblendw $11, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pcmpeqq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pcmpeqq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - pextrb $1, %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 pextrb $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - pextrd $1, %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 pextrd $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - pextrq $1, %xmm0, %rcx
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 pextrq $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 pextrw $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - phminposuw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - phminposuw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - pinsrb $1, %eax, %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pinsrb $1, (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - pinsrd $1, %eax, %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pinsrd $1, (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - pinsrq $1, %rax, %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pinsrq $1, (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pmaxsb %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pmaxsb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pmaxsd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pmaxsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pmaxud %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pmaxud (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pmaxuw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pmaxuw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pminsb %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pminsb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pminsd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pminsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pminud %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pminud (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pminuw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pminuw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - pmovsxbd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pmovsxbd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - pmovsxbq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pmovsxbq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - pmovsxbw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pmovsxbw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - pmovsxdq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pmovsxdq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - pmovsxwd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pmovsxwd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - pmovsxwq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pmovsxwq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - pmovzxbd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pmovzxbd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - pmovzxbq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pmovzxbq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - pmovzxbw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pmovzxbw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - pmovzxdq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pmovzxdq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - pmovzxwd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pmovzxwd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - pmovzxwq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pmovzxwq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 - - - - - - - - - - - pmuldq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pmuldq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 - - - - - - - - - - - pmulld %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pmulld (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 1.00 - - - - - - - - ptest %xmm0, %xmm1
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 1.00 1.00 1.00 0.33 0.33 0.33 0.33 0.33 0.33 - - ptest (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - roundpd $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - roundpd $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - roundps $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - roundps $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - roundsd $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - roundsd $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - roundss $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - roundss $1, (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-sse42.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-sse42.s
new file mode 100644
index 0000000000000..873e4f406426e
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-sse42.s
@@ -0,0 +1,114 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+crc32b %al, %ecx
+crc32b (%rax), %ecx
+
+crc32l %eax, %ecx
+crc32l (%rax), %ecx
+
+crc32w %ax, %ecx
+crc32w (%rax), %ecx
+
+crc32b %al, %rcx
+crc32b (%rax), %rcx
+
+crc32q %rax, %rcx
+crc32q (%rax), %rcx
+
+pcmpestri $1, %xmm0, %xmm2
+pcmpestri $1, (%rax), %xmm2
+
+pcmpestrm $1, %xmm0, %xmm2
+pcmpestrm $1, (%rax), %xmm2
+
+pcmpistri $1, %xmm0, %xmm2
+pcmpistri $1, (%rax), %xmm2
+
+pcmpistrm $1, %xmm0, %xmm2
+pcmpistrm $1, (%rax), %xmm2
+
+pcmpgtq %xmm0, %xmm2
+pcmpgtq (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 1.00 crc32b %al, %ecx
+# CHECK-NEXT: 1 7 1.00 * crc32b (%rax), %ecx
+# CHECK-NEXT: 1 3 1.00 crc32l %eax, %ecx
+# CHECK-NEXT: 1 7 1.00 * crc32l (%rax), %ecx
+# CHECK-NEXT: 1 3 1.00 crc32w %ax, %ecx
+# CHECK-NEXT: 1 7 1.00 * crc32w (%rax), %ecx
+# CHECK-NEXT: 1 3 1.00 crc32b %al, %rcx
+# CHECK-NEXT: 1 7 1.00 * crc32b (%rax), %rcx
+# CHECK-NEXT: 1 3 1.00 crc32q %rax, %rcx
+# CHECK-NEXT: 1 7 1.00 * crc32q (%rax), %rcx
+# CHECK-NEXT: 8 6 3.00 pcmpestri $1, %xmm0, %xmm2
+# CHECK-NEXT: 12 13 3.00 * pcmpestri $1, (%rax), %xmm2
+# CHECK-NEXT: 7 6 3.00 pcmpestrm $1, %xmm0, %xmm2
+# CHECK-NEXT: 12 13 3.00 * pcmpestrm $1, (%rax), %xmm2
+# CHECK-NEXT: 4 2 2.00 pcmpistri $1, %xmm0, %xmm2
+# CHECK-NEXT: 4 9 2.00 * pcmpistri $1, (%rax), %xmm2
+# CHECK-NEXT: 3 6 2.00 pcmpistrm $1, %xmm0, %xmm2
+# CHECK-NEXT: 4 13 2.00 * pcmpistrm $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pcmpgtq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pcmpgtq (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: 1.67 1.67 1.67 - 10.00 - - - 20.50 20.50 20.50 20.50 2.50 2.50 - 3.33 3.33 3.33 3.33 3.33 3.33 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - - - - crc32b %al, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - 1.00 - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - crc32b (%rax), %ecx
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - - - - crc32l %eax, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - 1.00 - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - crc32l (%rax), %ecx
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - - - - crc32w %ax, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - 1.00 - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - crc32w (%rax), %ecx
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - - - - crc32b %al, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - 1.00 - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - crc32b (%rax), %rcx
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - - - - crc32q %rax, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - 1.00 - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - crc32q (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - pcmpestri $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 3.00 3.00 3.00 3.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pcmpestri $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - pcmpestrm $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 3.00 3.00 3.00 3.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pcmpestrm $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 2.00 2.00 2.00 - - - - - - - - - - - pcmpistri $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 2.00 2.00 2.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pcmpistri $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 2.00 2.00 2.00 - - - - - - - - - - - pcmpistrm $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 2.00 2.00 2.00 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pcmpistrm $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pcmpgtq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pcmpgtq (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-sse4a.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-sse4a.s
new file mode 100644
index 0000000000000..1c1b0b24222fb
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-sse4a.s
@@ -0,0 +1,65 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+extrq %xmm0, %xmm2
+extrq $22, $2, %xmm2
+
+insertq %xmm0, %xmm2
+insertq $22, $22, %xmm0, %xmm2
+
+movntsd %xmm0, (%rax)
+movntss %xmm0, (%rax)
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 extrq %xmm0, %xmm2
+# CHECK-NEXT: 2 3 0.50 extrq $22, $2, %xmm2
+# CHECK-NEXT: 1 3 0.50 insertq %xmm0, %xmm2
+# CHECK-NEXT: 2 3 0.50 insertq $22, $22, %xmm0, %xmm2
+# CHECK-NEXT: 1 1 1.00 * movntsd %xmm0, (%rax)
+# CHECK-NEXT: 1 1 1.00 * movntss %xmm0, (%rax)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 - 3.00 3.00 2.00 0.67 0.67 0.67 - - - 1.00 1.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - - - - - - - - - extrq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - - - - - - - - - extrq $22, $2, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - - - - - - - - - insertq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - - - - - - - - - insertq $22, $22, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 movntsd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 1.00 0.33 0.33 0.33 - - - 0.50 0.50 movntss %xmm0, (%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-ssse3.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-ssse3.s
new file mode 100644
index 0000000000000..aeec49351a110
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-ssse3.s
@@ -0,0 +1,268 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+pabsb %mm0, %mm2
+pabsb (%rax), %mm2
+
+pabsb %xmm0, %xmm2
+pabsb (%rax), %xmm2
+
+pabsd %mm0, %mm2
+pabsd (%rax), %mm2
+
+pabsd %xmm0, %xmm2
+pabsd (%rax), %xmm2
+
+pabsw %mm0, %mm2
+pabsw (%rax), %mm2
+
+pabsw %xmm0, %xmm2
+pabsw (%rax), %xmm2
+
+palignr $1, %mm0, %mm2
+palignr $1, (%rax), %mm2
+
+palignr $1, %xmm0, %xmm2
+palignr $1, (%rax), %xmm2
+
+phaddd %mm0, %mm2
+phaddd (%rax), %mm2
+
+phaddd %xmm0, %xmm2
+phaddd (%rax), %xmm2
+
+phaddsw %mm0, %mm2
+phaddsw (%rax), %mm2
+
+phaddsw %xmm0, %xmm2
+phaddsw (%rax), %xmm2
+
+phaddw %mm0, %mm2
+phaddw (%rax), %mm2
+
+phaddw %xmm0, %xmm2
+phaddw (%rax), %xmm2
+
+phsubd %mm0, %mm2
+phsubd (%rax), %mm2
+
+phsubd %xmm0, %xmm2
+phsubd (%rax), %xmm2
+
+phsubsw %mm0, %mm2
+phsubsw (%rax), %mm2
+
+phsubsw %xmm0, %xmm2
+phsubsw (%rax), %xmm2
+
+phsubw %mm0, %mm2
+phsubw (%rax), %mm2
+
+phsubw %xmm0, %xmm2
+phsubw (%rax), %xmm2
+
+pmaddubsw %mm0, %mm2
+pmaddubsw (%rax), %mm2
+
+pmaddubsw %xmm0, %xmm2
+pmaddubsw (%rax), %xmm2
+
+pmulhrsw %mm0, %mm2
+pmulhrsw (%rax), %mm2
+
+pmulhrsw %xmm0, %xmm2
+pmulhrsw (%rax), %xmm2
+
+pshufb %mm0, %mm2
+pshufb (%rax), %mm2
+
+pshufb %xmm0, %xmm2
+pshufb (%rax), %xmm2
+
+psignb %mm0, %mm2
+psignb (%rax), %mm2
+
+psignb %xmm0, %xmm2
+psignb (%rax), %xmm2
+
+psignd %mm0, %mm2
+psignd (%rax), %mm2
+
+psignd %xmm0, %xmm2
+psignd (%rax), %xmm2
+
+psignw %mm0, %mm2
+psignw (%rax), %mm2
+
+psignw %xmm0, %xmm2
+psignw (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.50 pabsb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pabsb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 pabsb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pabsb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pabsd %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pabsd (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 pabsd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pabsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pabsw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pabsw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 pabsw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pabsw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 palignr $1, %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * palignr $1, (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 palignr $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * palignr $1, (%rax), %xmm2
+# CHECK-NEXT: 3 2 2.00 phaddd %mm0, %mm2
+# CHECK-NEXT: 4 9 2.00 * phaddd (%rax), %mm2
+# CHECK-NEXT: 4 2 2.00 phaddd %xmm0, %xmm2
+# CHECK-NEXT: 4 9 2.00 * phaddd (%rax), %xmm2
+# CHECK-NEXT: 3 2 2.00 phaddsw %mm0, %mm2
+# CHECK-NEXT: 4 9 2.00 * phaddsw (%rax), %mm2
+# CHECK-NEXT: 4 2 2.00 phaddsw %xmm0, %xmm2
+# CHECK-NEXT: 4 9 2.00 * phaddsw (%rax), %xmm2
+# CHECK-NEXT: 3 2 2.00 phaddw %mm0, %mm2
+# CHECK-NEXT: 4 9 2.00 * phaddw (%rax), %mm2
+# CHECK-NEXT: 4 2 2.00 phaddw %xmm0, %xmm2
+# CHECK-NEXT: 4 9 2.00 * phaddw (%rax), %xmm2
+# CHECK-NEXT: 3 2 2.00 phsubd %mm0, %mm2
+# CHECK-NEXT: 4 9 2.00 * phsubd (%rax), %mm2
+# CHECK-NEXT: 4 2 2.00 phsubd %xmm0, %xmm2
+# CHECK-NEXT: 4 9 2.00 * phsubd (%rax), %xmm2
+# CHECK-NEXT: 3 2 2.00 phsubsw %mm0, %mm2
+# CHECK-NEXT: 4 9 2.00 * phsubsw (%rax), %mm2
+# CHECK-NEXT: 4 2 2.00 phsubsw %xmm0, %xmm2
+# CHECK-NEXT: 4 9 2.00 * phsubsw (%rax), %xmm2
+# CHECK-NEXT: 3 2 2.00 phsubw %mm0, %mm2
+# CHECK-NEXT: 4 9 2.00 * phsubw (%rax), %mm2
+# CHECK-NEXT: 4 2 2.00 phsubw %xmm0, %xmm2
+# CHECK-NEXT: 4 9 2.00 * phsubw (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 pmaddubsw %mm0, %mm2
+# CHECK-NEXT: 1 10 0.50 * pmaddubsw (%rax), %mm2
+# CHECK-NEXT: 1 3 0.50 pmaddubsw %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * pmaddubsw (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 pmulhrsw %mm0, %mm2
+# CHECK-NEXT: 1 10 0.50 * pmulhrsw (%rax), %mm2
+# CHECK-NEXT: 1 3 0.50 pmulhrsw %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * pmulhrsw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pshufb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pshufb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 pshufb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pshufb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psignb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psignb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psignb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psignb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psignd %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psignd (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psignd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psignd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psignw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psignw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psignw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psignw (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: - - - - - - - - 61.00 13.00 7.00 7.00 16.00 16.00 - 10.67 10.67 10.67 10.67 10.67 10.67 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - pabsb %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pabsb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - pabsb %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pabsb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - pabsd %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pabsd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - pabsd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pabsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - pabsw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pabsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - pabsw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pabsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - palignr $1, %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - palignr $1, (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - palignr $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - palignr $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - - - - - phaddd %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - phaddd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - - - - - phaddd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - phaddd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - - - - - phaddsw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - phaddsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - - - - - phaddsw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - phaddsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - - - - - phaddw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - phaddw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - - - - - phaddw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - phaddw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - - - - - phsubd %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - phsubd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - - - - - phsubd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - phsubd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - - - - - phsubsw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - phsubsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - - - - - phsubsw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - phsubsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - - - - - phsubw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - phsubw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - - - - - phsubw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - phsubw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 - - - - - - - - - - - pmaddubsw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pmaddubsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 - - - - - - - - - - - pmaddubsw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pmaddubsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 - - - - - - - - - - - pmulhrsw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pmulhrsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 - - - - - - - - - - - pmulhrsw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pmulhrsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - pshufb %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pshufb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - pshufb %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - pshufb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - psignb %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - psignb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - psignb %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - psignb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - psignd %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - psignd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - psignd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - psignd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - psignw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - psignw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - psignw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - psignw (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-x86_32.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-x86_32.s
new file mode 100644
index 0000000000000..fb09b650840eb
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-x86_32.s
@@ -0,0 +1,93 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=i686-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+aaa
+
+aad
+aad $7
+
+aam
+aam $7
+
+aas
+
+bound %bx, (%eax)
+bound %ebx, (%eax)
+
+daa
+
+das
+
+into
+
+leave
+
+salc
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 100 100 25.00 aaa
+# CHECK-NEXT: 100 100 25.00 aad
+# CHECK-NEXT: 100 100 25.00 aad $7
+# CHECK-NEXT: 100 100 25.00 aam
+# CHECK-NEXT: 100 100 25.00 aam $7
+# CHECK-NEXT: 100 100 25.00 aas
+# CHECK-NEXT: 100 100 25.00 U bound %bx, (%eax)
+# CHECK-NEXT: 100 100 25.00 U bound %ebx, (%eax)
+# CHECK-NEXT: 100 100 25.00 daa
+# CHECK-NEXT: 100 100 25.00 das
+# CHECK-NEXT: 100 100 25.00 U into
+# CHECK-NEXT: 1 1 0.25 * leave
+# CHECK-NEXT: 1 1 0.25 U salc
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: - - - 275.50 275.50 275.50 275.50 - - - - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - aaa
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - aad
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - aad $7
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - aam
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - aam $7
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - aas
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - bound %bx, (%eax)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - bound %ebx, (%eax)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - daa
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - das
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - into
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leave
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - salc
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-x86_64.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-x86_64.s
new file mode 100644
index 0000000000000..275e6b7d6b92a
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-x86_64.s
@@ -0,0 +1,2491 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+adcb $0, %al
+adcb $0, %dil
+adcb $0, (%rax)
+adcb $7, %al
+adcb $7, %dil
+adcb $7, (%rax)
+adcb %sil, %dil
+adcb %sil, (%rax)
+adcb (%rax), %dil
+
+adcw $0, %ax
+adcw $0, %di
+adcw $0, (%rax)
+adcw $511, %ax
+adcw $511, %di
+adcw $511, (%rax)
+adcw $7, %di
+adcw $7, (%rax)
+adcw %si, %di
+adcw %si, (%rax)
+adcw (%rax), %di
+
+adcl $0, %eax
+adcl $0, %edi
+adcl $0, (%rax)
+adcl $665536, %eax
+adcl $665536, %edi
+adcl $665536, (%rax)
+adcl $7, %edi
+adcl $7, (%rax)
+adcl %esi, %edi
+adcl %esi, (%rax)
+adcl (%rax), %edi
+
+adcq $0, %rax
+adcq $0, %rdi
+adcq $0, (%rax)
+adcq $665536, %rax
+adcq $665536, %rdi
+adcq $665536, (%rax)
+adcq $7, %rdi
+adcq $7, (%rax)
+adcq %rsi, %rdi
+adcq %rsi, (%rax)
+adcq (%rax), %rdi
+
+addb $7, %al
+addb $7, %dil
+addb $7, (%rax)
+addb %sil, %dil
+addb %sil, (%rax)
+addb (%rax), %dil
+
+addw $511, %ax
+addw $511, %di
+addw $511, (%rax)
+addw $7, %di
+addw $7, (%rax)
+addw %si, %di
+addw %si, (%rax)
+addw (%rax), %di
+
+addl $665536, %eax
+addl $665536, %edi
+addl $665536, (%rax)
+addl $7, %edi
+addl $7, (%rax)
+addl %esi, %edi
+addl %esi, (%rax)
+addl (%rax), %edi
+
+addq $665536, %rax
+addq $665536, %rdi
+addq $665536, (%rax)
+addq $7, %rdi
+addq $7, (%rax)
+addq %rsi, %rdi
+addq %rsi, (%rax)
+addq (%rax), %rdi
+
+andb $7, %al
+andb $7, %dil
+andb $7, (%rax)
+andb %sil, %dil
+andb %sil, (%rax)
+andb (%rax), %dil
+
+andw $511, %ax
+andw $511, %di
+andw $511, (%rax)
+andw $7, %di
+andw $7, (%rax)
+andw %si, %di
+andw %si, (%rax)
+andw (%rax), %di
+
+andl $665536, %eax
+andl $665536, %edi
+andl $665536, (%rax)
+andl $7, %edi
+andl $7, (%rax)
+andl %esi, %edi
+andl %esi, (%rax)
+andl (%rax), %edi
+
+andq $665536, %rax
+andq $665536, %rdi
+andq $665536, (%rax)
+andq $7, %rdi
+andq $7, (%rax)
+andq %rsi, %rdi
+andq %rsi, (%rax)
+andq (%rax), %rdi
+
+bsfw %si, %di
+bsrw %si, %di
+bsfw (%rax), %di
+bsrw (%rax), %di
+
+bsfl %esi, %edi
+bsrl %esi, %edi
+bsfl (%rax), %edi
+bsrl (%rax), %edi
+
+bsfq %rsi, %rdi
+bsrq %rsi, %rdi
+bsfq (%rax), %rdi
+bsrq (%rax), %rdi
+
+bswap %eax
+bswap %rax
+
+btw %si, %di
+btcw %si, %di
+btrw %si, %di
+btsw %si, %di
+btw %si, (%rax)
+btcw %si, (%rax)
+btrw %si, (%rax)
+btsw %si, (%rax)
+btw $7, %di
+btcw $7, %di
+btrw $7, %di
+btsw $7, %di
+btw $7, (%rax)
+btcw $7, (%rax)
+btrw $7, (%rax)
+btsw $7, (%rax)
+
+btl %esi, %edi
+btcl %esi, %edi
+btrl %esi, %edi
+btsl %esi, %edi
+btl %esi, (%rax)
+btcl %esi, (%rax)
+btrl %esi, (%rax)
+btsl %esi, (%rax)
+btl $7, %edi
+btcl $7, %edi
+btrl $7, %edi
+btsl $7, %edi
+btl $7, (%rax)
+btcl $7, (%rax)
+btrl $7, (%rax)
+btsl $7, (%rax)
+
+btq %rsi, %rdi
+btcq %rsi, %rdi
+btrq %rsi, %rdi
+btsq %rsi, %rdi
+btq %rsi, (%rax)
+btcq %rsi, (%rax)
+btrq %rsi, (%rax)
+btsq %rsi, (%rax)
+btq $7, %rdi
+btcq $7, %rdi
+btrq $7, %rdi
+btsq $7, %rdi
+btq $7, (%rax)
+btcq $7, (%rax)
+btrq $7, (%rax)
+btsq $7, (%rax)
+
+cbw
+cwde
+cdqe
+cwd
+cdq
+cqo
+
+clc
+cld
+cmc
+
+cmpb $7, %al
+cmpb $7, %dil
+cmpb $7, (%rax)
+cmpb %sil, %dil
+cmpb %sil, (%rax)
+cmpb (%rax), %dil
+
+cmpw $511, %ax
+cmpw $511, %di
+cmpw $511, (%rax)
+cmpw $7, %di
+cmpw $7, (%rax)
+cmpw %si, %di
+cmpw %si, (%rax)
+cmpw (%rax), %di
+
+cmpl $665536, %eax
+cmpl $665536, %edi
+cmpl $665536, (%rax)
+cmpl $7, %edi
+cmpl $7, (%rax)
+cmpl %esi, %edi
+cmpl %esi, (%rax)
+cmpl (%rax), %edi
+
+cmpq $665536, %rax
+cmpq $665536, %rdi
+cmpq $665536, (%rax)
+cmpq $7, %rdi
+cmpq $7, (%rax)
+cmpq %rsi, %rdi
+cmpq %rsi, (%rax)
+cmpq (%rax), %rdi
+
+cmpsb
+cmpsw
+cmpsl
+cmpsq
+
+cmpxchgb %cl, %bl
+cmpxchgb %cl, (%rbx)
+
+cmpxchgw %cx, %bx
+cmpxchgw %cx, (%rbx)
+
+cmpxchgl %ecx, %ebx
+cmpxchgl %ecx, (%rbx)
+
+cmpxchgq %rcx, %rbx
+cmpxchgq %rcx, (%rbx)
+
+cpuid
+
+decb %dil
+decb (%rax)
+decw %di
+decw (%rax)
+decl %edi
+decl (%rax)
+decq %rdi
+decq (%rax)
+
+divb %dil
+divb (%rax)
+divw %si
+divw (%rax)
+divl %edx
+divl (%rax)
+divq %rcx
+divq (%rax)
+
+enter $7, $4095
+
+idivb %dil
+idivb (%rax)
+idivw %si
+idivw (%rax)
+idivl %edx
+idivl (%rax)
+idivq %rcx
+idivq (%rax)
+
+imulb %dil
+imulb (%rax)
+
+imulw %di
+imulw (%rax)
+imulw %si, %di
+imulw (%rax), %di
+imulw $511, %si, %di
+imulw $511, (%rax), %di
+imulw $7, %si, %di
+imulw $7, (%rax), %di
+
+imull %edi
+imull (%rax)
+imull %esi, %edi
+imull (%rax), %edi
+imull $665536, %esi, %edi
+imull $665536, (%rax), %edi
+imull $7, %esi, %edi
+imull $7, (%rax), %edi
+
+imulq %rdi
+imulq (%rax)
+imulq %rsi, %rdi
+imulq (%rax), %rdi
+imulq $665536, %rsi, %rdi
+imulq $665536, (%rax), %rdi
+imulq $7, %rsi, %rdi
+imulq $7, (%rax), %rdi
+
+inb $7, %al
+inb %dx, %al
+inw $7, %ax
+inw %dx, %ax
+inl $7, %eax
+inl %dx, %eax
+
+incb %dil
+incb (%rax)
+incw %di
+incw (%rax)
+incl %edi
+incl (%rax)
+incq %rdi
+incq (%rax)
+
+insb
+insw
+insl
+
+int $7
+
+invlpg (%rax)
+invlpga %rax, %ecx
+
+lahf
+
+leave
+
+lodsb
+lodsw
+lodsl
+lodsq
+
+movsb
+movsw
+movsl
+movsq
+
+movsbw %al, %di
+movzbw %al, %di
+movsbw (%rax), %di
+movzbw (%rax), %di
+movsbl %al, %edi
+movzbl %al, %edi
+movsbl (%rax), %edi
+movzbl (%rax), %edi
+movsbq %al, %rdi
+movzbq %al, %rdi
+movsbq (%rax), %rdi
+movzbq (%rax), %rdi
+
+movswl %ax, %edi
+movzwl %ax, %edi
+movswl (%rax), %edi
+movzwl (%rax), %edi
+movswq %ax, %rdi
+movzwq %ax, %rdi
+movswq (%rax), %rdi
+movzwq (%rax), %rdi
+
+movslq %eax, %rdi
+movslq (%rax), %rdi
+
+mulb %dil
+mulb (%rax)
+mulw %si
+mulw (%rax)
+mull %edx
+mull (%rax)
+mulq %rcx
+mulq (%rax)
+
+negb %dil
+negb (%r8)
+negw %si
+negw (%r9)
+negl %edx
+negl (%rax)
+negq %rcx
+negq (%r10)
+
+nop
+nopw %di
+nopw (%rcx)
+nopl %esi
+nopl (%r8)
+nopq %rdx
+nopq (%r9)
+
+notb %dil
+notb (%r8)
+notw %si
+notw (%r9)
+notl %edx
+notl (%rax)
+notq %rcx
+notq (%r10)
+
+orb $7, %al
+orb $7, %dil
+orb $7, (%rax)
+orb %sil, %dil
+orb %sil, (%rax)
+orb (%rax), %dil
+
+orw $511, %ax
+orw $511, %di
+orw $511, (%rax)
+orw $7, %di
+orw $7, (%rax)
+orw %si, %di
+orw %si, (%rax)
+orw (%rax), %di
+
+orl $665536, %eax
+orl $665536, %edi
+orl $665536, (%rax)
+orl $7, %edi
+orl $7, (%rax)
+orl %esi, %edi
+orl %esi, (%rax)
+orl (%rax), %edi
+
+orq $665536, %rax
+orq $665536, %rdi
+orq $665536, (%rax)
+orq $7, %rdi
+orq $7, (%rax)
+orq %rsi, %rdi
+orq %rsi, (%rax)
+orq (%rax), %rdi
+
+outb %al, $7
+outb %al, %dx
+outw %ax, $7
+outw %ax, %dx
+outl %eax, $7
+outl %eax, %dx
+
+outsb
+outsw
+outsl
+
+pause
+
+rclb %dil
+rcrb %dil
+rclb (%rax)
+rcrb (%rax)
+rclb $7, %dil
+rcrb $7, %dil
+rclb $7, (%rax)
+rcrb $7, (%rax)
+rclb %cl, %dil
+rcrb %cl, %dil
+rclb %cl, (%rax)
+rcrb %cl, (%rax)
+
+rclw %di
+rcrw %di
+rclw (%rax)
+rcrw (%rax)
+rclw $7, %di
+rcrw $7, %di
+rclw $7, (%rax)
+rcrw $7, (%rax)
+rclw %cl, %di
+rcrw %cl, %di
+rclw %cl, (%rax)
+rcrw %cl, (%rax)
+
+rcll %edi
+rcrl %edi
+rcll (%rax)
+rcrl (%rax)
+rcll $7, %edi
+rcrl $7, %edi
+rcll $7, (%rax)
+rcrl $7, (%rax)
+rcll %cl, %edi
+rcrl %cl, %edi
+rcll %cl, (%rax)
+rcrl %cl, (%rax)
+
+rclq %rdi
+rcrq %rdi
+rclq (%rax)
+rcrq (%rax)
+rclq $7, %rdi
+rcrq $7, %rdi
+rclq $7, (%rax)
+rcrq $7, (%rax)
+rclq %cl, %rdi
+rcrq %cl, %rdi
+rclq %cl, (%rax)
+rcrq %cl, (%rax)
+
+rdmsr
+rdpmc
+rdtsc
+rdtscp
+
+rolb %dil
+rorb %dil
+rolb (%rax)
+rorb (%rax)
+rolb $7, %dil
+rorb $7, %dil
+rolb $7, (%rax)
+rorb $7, (%rax)
+rolb %cl, %dil
+rorb %cl, %dil
+rolb %cl, (%rax)
+rorb %cl, (%rax)
+
+rolw %di
+rorw %di
+rolw (%rax)
+rorw (%rax)
+rolw $7, %di
+rorw $7, %di
+rolw $7, (%rax)
+rorw $7, (%rax)
+rolw %cl, %di
+rorw %cl, %di
+rolw %cl, (%rax)
+rorw %cl, (%rax)
+
+roll %edi
+rorl %edi
+roll (%rax)
+rorl (%rax)
+roll $7, %edi
+rorl $7, %edi
+roll $7, (%rax)
+rorl $7, (%rax)
+roll %cl, %edi
+rorl %cl, %edi
+roll %cl, (%rax)
+rorl %cl, (%rax)
+
+rolq %rdi
+rorq %rdi
+rolq (%rax)
+rorq (%rax)
+rolq $7, %rdi
+rorq $7, %rdi
+rolq $7, (%rax)
+rorq $7, (%rax)
+rolq %cl, %rdi
+rorq %cl, %rdi
+rolq %cl, (%rax)
+rorq %cl, (%rax)
+
+sahf
+
+sarb %dil
+shlb %dil
+shrb %dil
+sarb (%rax)
+shlb (%rax)
+shrb (%rax)
+sarb $7, %dil
+shlb $7, %dil
+shrb $7, %dil
+sarb $7, (%rax)
+shlb $7, (%rax)
+shrb $7, (%rax)
+sarb %cl, %dil
+shlb %cl, %dil
+shrb %cl, %dil
+sarb %cl, (%rax)
+shlb %cl, (%rax)
+shrb %cl, (%rax)
+
+sarw %di
+shlw %di
+shrw %di
+sarw (%rax)
+shlw (%rax)
+shrw (%rax)
+sarw $7, %di
+shlw $7, %di
+shrw $7, %di
+sarw $7, (%rax)
+shlw $7, (%rax)
+shrw $7, (%rax)
+sarw %cl, %di
+shlw %cl, %di
+shrw %cl, %di
+sarw %cl, (%rax)
+shlw %cl, (%rax)
+shrw %cl, (%rax)
+
+sarl %edi
+shll %edi
+shrl %edi
+sarl (%rax)
+shll (%rax)
+shrl (%rax)
+sarl $7, %edi
+shll $7, %edi
+shrl $7, %edi
+sarl $7, (%rax)
+shll $7, (%rax)
+shrl $7, (%rax)
+sarl %cl, %edi
+shll %cl, %edi
+shrl %cl, %edi
+sarl %cl, (%rax)
+shll %cl, (%rax)
+shrl %cl, (%rax)
+
+sarq %rdi
+shlq %rdi
+shrq %rdi
+sarq (%rax)
+shlq (%rax)
+shrq (%rax)
+sarq $7, %rdi
+shlq $7, %rdi
+shrq $7, %rdi
+sarq $7, (%rax)
+shlq $7, (%rax)
+shrq $7, (%rax)
+sarq %cl, %rdi
+shlq %cl, %rdi
+shrq %cl, %rdi
+sarq %cl, (%rax)
+shlq %cl, (%rax)
+shrq %cl, (%rax)
+
+sbbb $0, %al
+sbbb $0, %dil
+sbbb $0, (%rax)
+sbbb $7, %al
+sbbb $7, %dil
+sbbb $7, (%rax)
+sbbb %sil, %dil
+sbbb %sil, (%rax)
+sbbb (%rax), %dil
+
+sbbw $0, %ax
+sbbw $0, %di
+sbbw $0, (%rax)
+sbbw $511, %ax
+sbbw $511, %di
+sbbw $511, (%rax)
+sbbw $7, %di
+sbbw $7, (%rax)
+sbbw %si, %di
+sbbw %si, (%rax)
+sbbw (%rax), %di
+
+sbbl $0, %eax
+sbbl $0, %edi
+sbbl $0, (%rax)
+sbbl $665536, %eax
+sbbl $665536, %edi
+sbbl $665536, (%rax)
+sbbl $7, %edi
+sbbl $7, (%rax)
+sbbl %esi, %edi
+sbbl %esi, (%rax)
+sbbl (%rax), %edi
+
+sbbq $0, %rax
+sbbq $0, %rdi
+sbbq $0, (%rax)
+sbbq $665536, %rax
+sbbq $665536, %rdi
+sbbq $665536, (%rax)
+sbbq $7, %rdi
+sbbq $7, (%rax)
+sbbq %rsi, %rdi
+sbbq %rsi, (%rax)
+sbbq (%rax), %rdi
+
+scasb
+scasw
+scasl
+scasq
+
+seto %al
+seto (%rax)
+setno %al
+setno (%rax)
+setb %al
+setb (%rax)
+setnb %al
+setnb (%rax)
+setz %al
+setz (%rax)
+setnz %al
+setnz (%rax)
+seta %al
+seta (%rax)
+setna %al
+setna (%rax)
+sets %al
+sets (%rax)
+setns %al
+setns (%rax)
+setp %al
+setp (%rax)
+setnp %al
+setnp (%rax)
+setl %al
+setl (%rax)
+setnl %al
+setnl (%rax)
+setg %al
+setg (%rax)
+setng %al
+setng (%rax)
+
+shldw %cl, %si, %di
+shrdw %cl, %si, %di
+shldw %cl, %si, (%rax)
+shrdw %cl, %si, (%rax)
+shldw $7, %si, %di
+shrdw $7, %si, %di
+shldw $7, %si, (%rax)
+shrdw $7, %si, (%rax)
+
+shldl %cl, %esi, %edi
+shrdl %cl, %esi, %edi
+shldl %cl, %esi, (%rax)
+shrdl %cl, %esi, (%rax)
+shldl $7, %esi, %edi
+shrdl $7, %esi, %edi
+shldl $7, %esi, (%rax)
+shrdl $7, %esi, (%rax)
+
+shldq %cl, %rsi, %rdi
+shrdq %cl, %rsi, %rdi
+shldq %cl, %rsi, (%rax)
+shrdq %cl, %rsi, (%rax)
+shldq $7, %rsi, %rdi
+shrdq $7, %rsi, %rdi
+shldq $7, %rsi, (%rax)
+shrdq $7, %rsi, (%rax)
+
+stc
+std
+
+stosb
+stosw
+stosl
+stosq
+
+subb $7, %al
+subb $7, %dil
+subb $7, (%rax)
+subb %sil, %dil
+subb %sil, (%rax)
+subb (%rax), %dil
+
+subw $511, %ax
+subw $511, %di
+subw $511, (%rax)
+subw $7, %di
+subw $7, (%rax)
+subw %si, %di
+subw %si, (%rax)
+subw (%rax), %di
+
+subl $665536, %eax
+subl $665536, %edi
+subl $665536, (%rax)
+subl $7, %edi
+subl $7, (%rax)
+subl %esi, %edi
+subl %esi, (%rax)
+subl (%rax), %edi
+
+subq $665536, %rax
+subq $665536, %rdi
+subq $665536, (%rax)
+subq $7, %rdi
+subq $7, (%rax)
+subq %rsi, %rdi
+subq %rsi, (%rax)
+subq (%rax), %rdi
+
+testb $7, %al
+testb $7, %dil
+testb $7, (%rax)
+testb %sil, %dil
+testb %sil, (%rax)
+
+testw $511, %ax
+testw $511, %di
+testw $511, (%rax)
+testw $7, %di
+testw $7, (%rax)
+testw %si, %di
+testw %si, (%rax)
+
+testl $665536, %eax
+testl $665536, %edi
+testl $665536, (%rax)
+testl $7, %edi
+testl $7, (%rax)
+testl %esi, %edi
+testl %esi, (%rax)
+
+testq $665536, %rax
+testq $665536, %rdi
+testq $665536, (%rax)
+testq $7, %rdi
+testq $7, (%rax)
+testq %rsi, %rdi
+testq %rsi, (%rax)
+
+ud2
+
+wrmsr
+
+xaddb %bl, %cl
+xaddb %bl, (%rcx)
+
+xaddw %bx, %cx
+xaddw %ax, (%rbx)
+
+xaddl %ebx, %ecx
+xaddl %eax, (%rbx)
+
+xaddq %rbx, %rcx
+xaddq %rax, (%rbx)
+
+xchgb %bl, %cl
+xchgb %bl, (%rbx)
+
+xchgw %ax, %bx
+xchgw %bx, %cx
+xchgw %ax, (%rbx)
+
+xchgl %eax, %ebx
+xchgl %ebx, %ecx
+xchgl %eax, (%rbx)
+
+xchgq %rax, %rbx
+xchgq %rbx, %rcx
+xchgq %rax, (%rbx)
+
+xlatb
+
+xorb $7, %al
+xorb $7, %dil
+xorb $7, (%rax)
+xorb %sil, %dil
+xorb %sil, (%rax)
+xorb (%rax), %dil
+
+xorw $511, %ax
+xorw $511, %di
+xorw $511, (%rax)
+xorw $7, %di
+xorw $7, (%rax)
+xorw %si, %di
+xorw %si, (%rax)
+xorw (%rax), %di
+
+xorl $665536, %eax
+xorl $665536, %edi
+xorl $665536, (%rax)
+xorl $7, %edi
+xorl $7, (%rax)
+xorl %esi, %edi
+xorl %esi, (%rax)
+xorl (%rax), %edi
+
+xorq $665536, %rax
+xorq $665536, %rdi
+xorq $665536, (%rax)
+xorq $7, %rdi
+xorq $7, (%rax)
+xorq %rsi, %rdi
+xorq %rsi, (%rax)
+xorq (%rax), %rdi
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 adcb $0, %al
+# CHECK-NEXT: 1 1 1.00 adcb $0, %dil
+# CHECK-NEXT: 1 6 1.00 * * adcb $0, (%rax)
+# CHECK-NEXT: 1 1 1.00 adcb $7, %al
+# CHECK-NEXT: 1 1 1.00 adcb $7, %dil
+# CHECK-NEXT: 1 6 1.00 * * adcb $7, (%rax)
+# CHECK-NEXT: 1 1 1.00 adcb %sil, %dil
+# CHECK-NEXT: 1 1 1.75 * * adcb %sil, (%rax)
+# CHECK-NEXT: 1 5 1.00 * adcb (%rax), %dil
+# CHECK-NEXT: 1 1 1.00 adcw $0, %ax
+# CHECK-NEXT: 1 1 1.00 adcw $0, %di
+# CHECK-NEXT: 1 6 1.00 * * adcw $0, (%rax)
+# CHECK-NEXT: 1 1 1.00 adcw $511, %ax
+# CHECK-NEXT: 1 1 1.00 adcw $511, %di
+# CHECK-NEXT: 1 6 1.00 * * adcw $511, (%rax)
+# CHECK-NEXT: 1 1 1.00 adcw $7, %di
+# CHECK-NEXT: 1 6 1.00 * * adcw $7, (%rax)
+# CHECK-NEXT: 1 1 1.00 adcw %si, %di
+# CHECK-NEXT: 1 6 1.00 * * adcw %si, (%rax)
+# CHECK-NEXT: 1 5 1.00 * adcw (%rax), %di
+# CHECK-NEXT: 1 1 1.00 adcl $0, %eax
+# CHECK-NEXT: 1 1 1.00 adcl $0, %edi
+# CHECK-NEXT: 1 6 1.00 * * adcl $0, (%rax)
+# CHECK-NEXT: 1 1 1.00 adcl $665536, %eax
+# CHECK-NEXT: 1 1 1.00 adcl $665536, %edi
+# CHECK-NEXT: 1 6 1.00 * * adcl $665536, (%rax)
+# CHECK-NEXT: 1 1 1.00 adcl $7, %edi
+# CHECK-NEXT: 1 6 1.00 * * adcl $7, (%rax)
+# CHECK-NEXT: 1 1 1.00 adcl %esi, %edi
+# CHECK-NEXT: 1 6 1.00 * * adcl %esi, (%rax)
+# CHECK-NEXT: 1 5 1.00 * adcl (%rax), %edi
+# CHECK-NEXT: 1 1 1.00 adcq $0, %rax
+# CHECK-NEXT: 1 1 1.00 adcq $0, %rdi
+# CHECK-NEXT: 1 6 1.00 * * adcq $0, (%rax)
+# CHECK-NEXT: 1 1 1.00 adcq $665536, %rax
+# CHECK-NEXT: 1 1 1.00 adcq $665536, %rdi
+# CHECK-NEXT: 1 6 1.00 * * adcq $665536, (%rax)
+# CHECK-NEXT: 1 1 1.00 adcq $7, %rdi
+# CHECK-NEXT: 1 6 1.00 * * adcq $7, (%rax)
+# CHECK-NEXT: 1 1 1.00 adcq %rsi, %rdi
+# CHECK-NEXT: 1 6 1.00 * * adcq %rsi, (%rax)
+# CHECK-NEXT: 1 5 1.00 * adcq (%rax), %rdi
+# CHECK-NEXT: 1 1 1.00 addb $7, %al
+# CHECK-NEXT: 1 1 0.25 addb $7, %dil
+# CHECK-NEXT: 1 6 0.67 * * addb $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 addb %sil, %dil
+# CHECK-NEXT: 1 6 0.67 * * addb %sil, (%rax)
+# CHECK-NEXT: 1 5 0.33 * addb (%rax), %dil
+# CHECK-NEXT: 1 1 1.00 addw $511, %ax
+# CHECK-NEXT: 1 1 0.25 addw $511, %di
+# CHECK-NEXT: 1 6 0.67 * * addw $511, (%rax)
+# CHECK-NEXT: 1 1 0.25 addw $7, %di
+# CHECK-NEXT: 1 6 0.67 * * addw $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 addw %si, %di
+# CHECK-NEXT: 1 6 0.67 * * addw %si, (%rax)
+# CHECK-NEXT: 1 5 0.33 * addw (%rax), %di
+# CHECK-NEXT: 1 1 1.00 addl $665536, %eax
+# CHECK-NEXT: 1 1 0.25 addl $665536, %edi
+# CHECK-NEXT: 1 6 0.67 * * addl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.25 addl $7, %edi
+# CHECK-NEXT: 1 6 0.67 * * addl $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 addl %esi, %edi
+# CHECK-NEXT: 1 6 0.67 * * addl %esi, (%rax)
+# CHECK-NEXT: 1 5 0.33 * addl (%rax), %edi
+# CHECK-NEXT: 1 1 1.00 addq $665536, %rax
+# CHECK-NEXT: 1 1 0.25 addq $665536, %rdi
+# CHECK-NEXT: 1 6 0.67 * * addq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.25 addq $7, %rdi
+# CHECK-NEXT: 1 6 0.67 * * addq $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 addq %rsi, %rdi
+# CHECK-NEXT: 1 6 0.67 * * addq %rsi, (%rax)
+# CHECK-NEXT: 1 5 0.33 * addq (%rax), %rdi
+# CHECK-NEXT: 1 1 1.00 andb $7, %al
+# CHECK-NEXT: 1 1 0.25 andb $7, %dil
+# CHECK-NEXT: 1 6 0.67 * * andb $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 andb %sil, %dil
+# CHECK-NEXT: 1 6 0.67 * * andb %sil, (%rax)
+# CHECK-NEXT: 1 5 0.33 * andb (%rax), %dil
+# CHECK-NEXT: 1 1 1.00 andw $511, %ax
+# CHECK-NEXT: 1 1 0.25 andw $511, %di
+# CHECK-NEXT: 1 6 0.67 * * andw $511, (%rax)
+# CHECK-NEXT: 1 1 0.25 andw $7, %di
+# CHECK-NEXT: 1 6 0.67 * * andw $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 andw %si, %di
+# CHECK-NEXT: 1 6 0.67 * * andw %si, (%rax)
+# CHECK-NEXT: 1 5 0.33 * andw (%rax), %di
+# CHECK-NEXT: 1 1 1.00 andl $665536, %eax
+# CHECK-NEXT: 1 1 0.25 andl $665536, %edi
+# CHECK-NEXT: 1 6 0.67 * * andl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.25 andl $7, %edi
+# CHECK-NEXT: 1 6 0.67 * * andl $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 andl %esi, %edi
+# CHECK-NEXT: 1 6 0.67 * * andl %esi, (%rax)
+# CHECK-NEXT: 1 5 0.33 * andl (%rax), %edi
+# CHECK-NEXT: 1 1 1.00 andq $665536, %rax
+# CHECK-NEXT: 1 1 0.25 andq $665536, %rdi
+# CHECK-NEXT: 1 6 0.67 * * andq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.25 andq $7, %rdi
+# CHECK-NEXT: 1 6 0.67 * * andq $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 andq %rsi, %rdi
+# CHECK-NEXT: 1 6 0.67 * * andq %rsi, (%rax)
+# CHECK-NEXT: 1 5 0.33 * andq (%rax), %rdi
+# CHECK-NEXT: 6 3 3.00 bsfw %si, %di
+# CHECK-NEXT: 6 4 4.00 bsrw %si, %di
+# CHECK-NEXT: 8 7 3.00 * bsfw (%rax), %di
+# CHECK-NEXT: 8 8 4.00 * bsrw (%rax), %di
+# CHECK-NEXT: 6 3 3.00 bsfl %esi, %edi
+# CHECK-NEXT: 6 4 4.00 bsrl %esi, %edi
+# CHECK-NEXT: 8 7 3.00 * bsfl (%rax), %edi
+# CHECK-NEXT: 8 8 4.00 * bsrl (%rax), %edi
+# CHECK-NEXT: 6 3 3.00 bsfq %rsi, %rdi
+# CHECK-NEXT: 6 4 4.00 bsrq %rsi, %rdi
+# CHECK-NEXT: 8 7 3.00 * bsfq (%rax), %rdi
+# CHECK-NEXT: 8 8 4.00 * bsrq (%rax), %rdi
+# CHECK-NEXT: 1 1 0.25 bswapl %eax
+# CHECK-NEXT: 1 1 0.25 bswapq %rax
+# CHECK-NEXT: 1 1 0.50 btw %si, %di
+# CHECK-NEXT: 2 2 1.00 btcw %si, %di
+# CHECK-NEXT: 2 2 1.00 btrw %si, %di
+# CHECK-NEXT: 2 2 1.00 btsw %si, %di
+# CHECK-NEXT: 7 5 0.50 * btw %si, (%rax)
+# CHECK-NEXT: 9 7 0.67 * * btcw %si, (%rax)
+# CHECK-NEXT: 9 7 0.67 * * btrw %si, (%rax)
+# CHECK-NEXT: 9 7 0.67 * * btsw %si, (%rax)
+# CHECK-NEXT: 1 1 0.50 btw $7, %di
+# CHECK-NEXT: 2 2 1.00 btcw $7, %di
+# CHECK-NEXT: 2 2 1.00 btrw $7, %di
+# CHECK-NEXT: 2 2 1.00 btsw $7, %di
+# CHECK-NEXT: 2 5 0.50 * btw $7, (%rax)
+# CHECK-NEXT: 4 7 0.67 * * btcw $7, (%rax)
+# CHECK-NEXT: 4 7 0.67 * * btrw $7, (%rax)
+# CHECK-NEXT: 4 7 0.67 * * btsw $7, (%rax)
+# CHECK-NEXT: 1 1 0.50 btl %esi, %edi
+# CHECK-NEXT: 2 2 1.00 btcl %esi, %edi
+# CHECK-NEXT: 2 2 1.00 btrl %esi, %edi
+# CHECK-NEXT: 2 2 1.00 btsl %esi, %edi
+# CHECK-NEXT: 7 5 0.50 * btl %esi, (%rax)
+# CHECK-NEXT: 9 7 0.67 * * btcl %esi, (%rax)
+# CHECK-NEXT: 9 7 0.67 * * btrl %esi, (%rax)
+# CHECK-NEXT: 9 7 0.67 * * btsl %esi, (%rax)
+# CHECK-NEXT: 1 1 0.50 btl $7, %edi
+# CHECK-NEXT: 2 2 1.00 btcl $7, %edi
+# CHECK-NEXT: 2 2 1.00 btrl $7, %edi
+# CHECK-NEXT: 2 2 1.00 btsl $7, %edi
+# CHECK-NEXT: 2 5 0.50 * btl $7, (%rax)
+# CHECK-NEXT: 4 7 0.67 * * btcl $7, (%rax)
+# CHECK-NEXT: 4 7 0.67 * * btrl $7, (%rax)
+# CHECK-NEXT: 4 7 0.67 * * btsl $7, (%rax)
+# CHECK-NEXT: 1 1 0.50 btq %rsi, %rdi
+# CHECK-NEXT: 2 2 1.00 btcq %rsi, %rdi
+# CHECK-NEXT: 2 2 1.00 btrq %rsi, %rdi
+# CHECK-NEXT: 2 2 1.00 btsq %rsi, %rdi
+# CHECK-NEXT: 7 5 0.50 * btq %rsi, (%rax)
+# CHECK-NEXT: 9 7 0.67 * * btcq %rsi, (%rax)
+# CHECK-NEXT: 9 7 0.67 * * btrq %rsi, (%rax)
+# CHECK-NEXT: 9 7 0.67 * * btsq %rsi, (%rax)
+# CHECK-NEXT: 1 1 0.50 btq $7, %rdi
+# CHECK-NEXT: 2 2 1.00 btcq $7, %rdi
+# CHECK-NEXT: 2 2 1.00 btrq $7, %rdi
+# CHECK-NEXT: 2 2 1.00 btsq $7, %rdi
+# CHECK-NEXT: 2 5 0.50 * btq $7, (%rax)
+# CHECK-NEXT: 4 7 0.67 * * btcq $7, (%rax)
+# CHECK-NEXT: 4 7 0.67 * * btrq $7, (%rax)
+# CHECK-NEXT: 4 7 0.67 * * btsq $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 cbtw
+# CHECK-NEXT: 1 1 0.25 cwtl
+# CHECK-NEXT: 1 1 0.25 cltq
+# CHECK-NEXT: 1 1 0.25 cwtd
+# CHECK-NEXT: 1 1 0.25 cltd
+# CHECK-NEXT: 1 1 0.25 cqto
+# CHECK-NEXT: 1 1 0.25 U clc
+# CHECK-NEXT: 1 1 0.25 U cld
+# CHECK-NEXT: 1 1 0.25 U cmc
+# CHECK-NEXT: 1 1 0.25 cmpb $7, %al
+# CHECK-NEXT: 1 1 0.25 cmpb $7, %dil
+# CHECK-NEXT: 1 5 0.33 * cmpb $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 cmpb %sil, %dil
+# CHECK-NEXT: 1 5 0.33 * cmpb %sil, (%rax)
+# CHECK-NEXT: 1 5 0.33 * cmpb (%rax), %dil
+# CHECK-NEXT: 1 1 0.25 cmpw $511, %ax
+# CHECK-NEXT: 1 1 0.25 cmpw $511, %di
+# CHECK-NEXT: 1 5 0.33 * cmpw $511, (%rax)
+# CHECK-NEXT: 1 1 0.25 cmpw $7, %di
+# CHECK-NEXT: 1 5 0.33 * cmpw $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 cmpw %si, %di
+# CHECK-NEXT: 1 5 0.33 * cmpw %si, (%rax)
+# CHECK-NEXT: 1 5 0.33 * cmpw (%rax), %di
+# CHECK-NEXT: 1 1 0.25 cmpl $665536, %eax
+# CHECK-NEXT: 1 1 0.25 cmpl $665536, %edi
+# CHECK-NEXT: 1 5 0.33 * cmpl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.25 cmpl $7, %edi
+# CHECK-NEXT: 1 5 0.33 * cmpl $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 cmpl %esi, %edi
+# CHECK-NEXT: 1 5 0.33 * cmpl %esi, (%rax)
+# CHECK-NEXT: 1 5 0.33 * cmpl (%rax), %edi
+# CHECK-NEXT: 1 1 0.25 cmpq $665536, %rax
+# CHECK-NEXT: 1 1 0.25 cmpq $665536, %rdi
+# CHECK-NEXT: 1 5 0.33 * cmpq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.25 cmpq $7, %rdi
+# CHECK-NEXT: 1 5 0.33 * cmpq $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 cmpq %rsi, %rdi
+# CHECK-NEXT: 1 5 0.33 * cmpq %rsi, (%rax)
+# CHECK-NEXT: 1 5 0.33 * cmpq (%rax), %rdi
+# CHECK-NEXT: 100 100 25.00 U cmpsb %es:(%rdi), (%rsi)
+# CHECK-NEXT: 100 100 25.00 U cmpsw %es:(%rdi), (%rsi)
+# CHECK-NEXT: 100 100 25.00 U cmpsl %es:(%rdi), (%rsi)
+# CHECK-NEXT: 100 100 25.00 U cmpsq %es:(%rdi), (%rsi)
+# CHECK-NEXT: 3 3 3.00 cmpxchgb %cl, %bl
+# CHECK-NEXT: 5 7 3.00 * * cmpxchgb %cl, (%rbx)
+# CHECK-NEXT: 5 3 3.00 cmpxchgw %cx, %bx
+# CHECK-NEXT: 6 3 3.00 * * cmpxchgw %cx, (%rbx)
+# CHECK-NEXT: 5 3 3.00 cmpxchgl %ecx, %ebx
+# CHECK-NEXT: 6 3 3.00 * * cmpxchgl %ecx, (%rbx)
+# CHECK-NEXT: 5 3 3.00 cmpxchgq %rcx, %rbx
+# CHECK-NEXT: 6 3 3.00 * * cmpxchgq %rcx, (%rbx)
+# CHECK-NEXT: 100 100 25.00 U cpuid
+# CHECK-NEXT: 1 1 0.25 decb %dil
+# CHECK-NEXT: 1 6 0.67 * * decb (%rax)
+# CHECK-NEXT: 1 1 0.25 decw %di
+# CHECK-NEXT: 1 6 0.67 * * decw (%rax)
+# CHECK-NEXT: 1 1 0.25 decl %edi
+# CHECK-NEXT: 1 6 0.67 * * decl (%rax)
+# CHECK-NEXT: 1 1 0.25 decq %rdi
+# CHECK-NEXT: 1 6 0.67 * * decq (%rax)
+# CHECK-NEXT: 2 10 10.00 U divb %dil
+# CHECK-NEXT: 2 14 10.00 * U divb (%rax)
+# CHECK-NEXT: 2 11 11.00 U divw %si
+# CHECK-NEXT: 2 15 11.00 * U divw (%rax)
+# CHECK-NEXT: 2 13 13.00 U divl %edx
+# CHECK-NEXT: 2 17 13.00 * U divl (%rax)
+# CHECK-NEXT: 2 17 17.00 U divq %rcx
+# CHECK-NEXT: 2 21 17.00 * U divq (%rax)
+# CHECK-NEXT: 100 100 25.00 U enter $7, $4095
+# CHECK-NEXT: 2 10 10.00 U idivb %dil
+# CHECK-NEXT: 2 14 10.00 * U idivb (%rax)
+# CHECK-NEXT: 2 11 11.00 U idivw %si
+# CHECK-NEXT: 2 15 11.00 * U idivw (%rax)
+# CHECK-NEXT: 2 13 13.00 U idivl %edx
+# CHECK-NEXT: 2 17 13.00 * U idivl (%rax)
+# CHECK-NEXT: 2 17 17.00 U idivq %rcx
+# CHECK-NEXT: 2 21 17.00 * U idivq (%rax)
+# CHECK-NEXT: 1 3 3.00 imulb %dil
+# CHECK-NEXT: 1 7 3.00 * imulb (%rax)
+# CHECK-NEXT: 3 3 3.00 imulw %di
+# CHECK-NEXT: 4 7 3.00 * imulw (%rax)
+# CHECK-NEXT: 1 3 1.00 imulw %si, %di
+# CHECK-NEXT: 1 7 1.00 * imulw (%rax), %di
+# CHECK-NEXT: 2 4 4.00 imulw $511, %si, %di
+# CHECK-NEXT: 2 8 4.00 * imulw $511, (%rax), %di
+# CHECK-NEXT: 2 4 4.00 imulw $7, %si, %di
+# CHECK-NEXT: 2 8 4.00 * imulw $7, (%rax), %di
+# CHECK-NEXT: 2 3 3.00 imull %edi
+# CHECK-NEXT: 2 7 3.00 * imull (%rax)
+# CHECK-NEXT: 1 3 1.00 imull %esi, %edi
+# CHECK-NEXT: 1 7 1.00 * imull (%rax), %edi
+# CHECK-NEXT: 1 3 1.00 imull $665536, %esi, %edi
+# CHECK-NEXT: 1 7 1.00 * imull $665536, (%rax), %edi
+# CHECK-NEXT: 1 3 1.00 imull $7, %esi, %edi
+# CHECK-NEXT: 1 7 1.00 * imull $7, (%rax), %edi
+# CHECK-NEXT: 2 3 3.00 imulq %rdi
+# CHECK-NEXT: 2 7 3.00 * imulq (%rax)
+# CHECK-NEXT: 1 3 1.00 imulq %rsi, %rdi
+# CHECK-NEXT: 1 7 1.00 * imulq (%rax), %rdi
+# CHECK-NEXT: 1 3 1.00 imulq $665536, %rsi, %rdi
+# CHECK-NEXT: 1 7 1.00 * imulq $665536, (%rax), %rdi
+# CHECK-NEXT: 1 3 1.00 imulq $7, %rsi, %rdi
+# CHECK-NEXT: 1 7 1.00 * imulq $7, (%rax), %rdi
+# CHECK-NEXT: 100 100 25.00 U inb $7, %al
+# CHECK-NEXT: 100 100 25.00 U inb %dx, %al
+# CHECK-NEXT: 100 100 25.00 U inw $7, %ax
+# CHECK-NEXT: 100 100 25.00 U inw %dx, %ax
+# CHECK-NEXT: 100 100 25.00 U inl $7, %eax
+# CHECK-NEXT: 100 100 25.00 U inl %dx, %eax
+# CHECK-NEXT: 1 1 0.25 incb %dil
+# CHECK-NEXT: 1 6 0.67 * * incb (%rax)
+# CHECK-NEXT: 1 1 0.25 incw %di
+# CHECK-NEXT: 1 6 0.67 * * incw (%rax)
+# CHECK-NEXT: 1 1 0.25 incl %edi
+# CHECK-NEXT: 1 6 0.67 * * incl (%rax)
+# CHECK-NEXT: 1 1 0.25 incq %rdi
+# CHECK-NEXT: 1 6 0.67 * * incq (%rax)
+# CHECK-NEXT: 100 100 25.00 U insb %dx, %es:(%rdi)
+# CHECK-NEXT: 100 100 25.00 U insw %dx, %es:(%rdi)
+# CHECK-NEXT: 100 100 25.00 U insl %dx, %es:(%rdi)
+# CHECK-NEXT: 100 100 25.00 * * U int $7
+# CHECK-NEXT: 100 100 25.00 U invlpg (%rax)
+# CHECK-NEXT: 100 100 25.00 U invlpga
+# CHECK-NEXT: 1 1 1.00 lahf
+# CHECK-NEXT: 1 1 0.25 * leave
+# CHECK-NEXT: 100 100 25.00 U lodsb (%rsi), %al
+# CHECK-NEXT: 100 100 25.00 U lodsw (%rsi), %ax
+# CHECK-NEXT: 100 100 25.00 U lodsl (%rsi), %eax
+# CHECK-NEXT: 100 100 25.00 U lodsq (%rsi), %rax
+# CHECK-NEXT: 100 100 25.00 U movsb (%rsi), %es:(%rdi)
+# CHECK-NEXT: 100 100 25.00 U movsw (%rsi), %es:(%rdi)
+# CHECK-NEXT: 100 100 25.00 U movsl (%rsi), %es:(%rdi)
+# CHECK-NEXT: 100 100 25.00 U movsq (%rsi), %es:(%rdi)
+# CHECK-NEXT: 1 1 1.00 movsbw %al, %di
+# CHECK-NEXT: 1 1 1.00 movzbw %al, %di
+# CHECK-NEXT: 1 5 1.00 * movsbw (%rax), %di
+# CHECK-NEXT: 1 5 1.00 * movzbw (%rax), %di
+# CHECK-NEXT: 1 1 0.25 movsbl %al, %edi
+# CHECK-NEXT: 1 1 0.25 movzbl %al, %edi
+# CHECK-NEXT: 1 5 0.33 * movsbl (%rax), %edi
+# CHECK-NEXT: 1 5 0.33 * movzbl (%rax), %edi
+# CHECK-NEXT: 1 1 0.25 movsbq %al, %rdi
+# CHECK-NEXT: 1 1 0.25 movzbq %al, %rdi
+# CHECK-NEXT: 1 5 0.33 * movsbq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.33 * movzbq (%rax), %rdi
+# CHECK-NEXT: 1 1 0.25 movswl %ax, %edi
+# CHECK-NEXT: 1 1 0.25 movzwl %ax, %edi
+# CHECK-NEXT: 1 5 0.33 * movswl (%rax), %edi
+# CHECK-NEXT: 1 5 0.33 * movzwl (%rax), %edi
+# CHECK-NEXT: 1 1 0.25 movswq %ax, %rdi
+# CHECK-NEXT: 1 1 0.25 movzwq %ax, %rdi
+# CHECK-NEXT: 1 5 0.33 * movswq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.33 * movzwq (%rax), %rdi
+# CHECK-NEXT: 1 1 0.25 movslq %eax, %rdi
+# CHECK-NEXT: 1 5 0.33 * movslq (%rax), %rdi
+# CHECK-NEXT: 1 3 3.00 mulb %dil
+# CHECK-NEXT: 1 7 3.00 * mulb (%rax)
+# CHECK-NEXT: 3 3 3.00 mulw %si
+# CHECK-NEXT: 4 7 3.00 * mulw (%rax)
+# CHECK-NEXT: 2 3 3.00 mull %edx
+# CHECK-NEXT: 2 7 3.00 * mull (%rax)
+# CHECK-NEXT: 2 3 3.00 mulq %rcx
+# CHECK-NEXT: 2 7 3.00 * mulq (%rax)
+# CHECK-NEXT: 1 1 0.25 negb %dil
+# CHECK-NEXT: 1 6 0.67 * * negb (%r8)
+# CHECK-NEXT: 1 1 0.25 negw %si
+# CHECK-NEXT: 1 6 0.67 * * negw (%r9)
+# CHECK-NEXT: 1 1 0.25 negl %edx
+# CHECK-NEXT: 1 6 0.67 * * negl (%rax)
+# CHECK-NEXT: 1 1 0.25 negq %rcx
+# CHECK-NEXT: 1 6 0.67 * * negq (%r10)
+# CHECK-NEXT: 1 0 0.25 nop
+# CHECK-NEXT: 1 0 0.25 nopw %di
+# CHECK-NEXT: 1 0 0.25 nopw (%rcx)
+# CHECK-NEXT: 1 0 0.25 nopl %esi
+# CHECK-NEXT: 1 0 0.25 nopl (%r8)
+# CHECK-NEXT: 1 0 0.25 nopq %rdx
+# CHECK-NEXT: 1 0 0.25 nopq (%r9)
+# CHECK-NEXT: 1 1 0.25 notb %dil
+# CHECK-NEXT: 1 6 0.67 * * notb (%r8)
+# CHECK-NEXT: 1 1 0.25 notw %si
+# CHECK-NEXT: 1 6 0.67 * * notw (%r9)
+# CHECK-NEXT: 1 1 0.25 notl %edx
+# CHECK-NEXT: 1 6 0.67 * * notl (%rax)
+# CHECK-NEXT: 1 1 0.25 notq %rcx
+# CHECK-NEXT: 1 6 0.67 * * notq (%r10)
+# CHECK-NEXT: 1 1 1.00 orb $7, %al
+# CHECK-NEXT: 1 1 0.25 orb $7, %dil
+# CHECK-NEXT: 1 6 0.67 * * orb $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 orb %sil, %dil
+# CHECK-NEXT: 1 6 0.67 * * orb %sil, (%rax)
+# CHECK-NEXT: 1 5 0.33 * orb (%rax), %dil
+# CHECK-NEXT: 1 1 1.00 orw $511, %ax
+# CHECK-NEXT: 1 1 0.25 orw $511, %di
+# CHECK-NEXT: 1 6 0.67 * * orw $511, (%rax)
+# CHECK-NEXT: 1 1 0.25 orw $7, %di
+# CHECK-NEXT: 1 6 0.67 * * orw $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 orw %si, %di
+# CHECK-NEXT: 1 6 0.67 * * orw %si, (%rax)
+# CHECK-NEXT: 1 5 0.33 * orw (%rax), %di
+# CHECK-NEXT: 1 1 1.00 orl $665536, %eax
+# CHECK-NEXT: 1 1 0.25 orl $665536, %edi
+# CHECK-NEXT: 1 6 0.67 * * orl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.25 orl $7, %edi
+# CHECK-NEXT: 1 6 0.67 * * orl $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 orl %esi, %edi
+# CHECK-NEXT: 1 6 0.67 * * orl %esi, (%rax)
+# CHECK-NEXT: 1 5 0.33 * orl (%rax), %edi
+# CHECK-NEXT: 1 1 1.00 orq $665536, %rax
+# CHECK-NEXT: 1 1 0.25 orq $665536, %rdi
+# CHECK-NEXT: 1 6 0.67 * * orq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.25 orq $7, %rdi
+# CHECK-NEXT: 1 6 0.67 * * orq $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 orq %rsi, %rdi
+# CHECK-NEXT: 1 6 0.67 * * orq %rsi, (%rax)
+# CHECK-NEXT: 1 5 0.33 * orq (%rax), %rdi
+# CHECK-NEXT: 100 100 25.00 U outb %al, $7
+# CHECK-NEXT: 100 100 25.00 U outb %al, %dx
+# CHECK-NEXT: 100 100 25.00 U outw %ax, $7
+# CHECK-NEXT: 100 100 25.00 U outw %ax, %dx
+# CHECK-NEXT: 100 100 25.00 U outl %eax, $7
+# CHECK-NEXT: 100 100 25.00 U outl %eax, %dx
+# CHECK-NEXT: 100 100 25.00 U outsb (%rsi), %dx
+# CHECK-NEXT: 100 100 25.00 U outsw (%rsi), %dx
+# CHECK-NEXT: 100 100 25.00 U outsl (%rsi), %dx
+# CHECK-NEXT: 1 0 0.25 * * U pause
+# CHECK-NEXT: 1 1 1.00 rclb %dil
+# CHECK-NEXT: 1 1 1.00 rcrb %dil
+# CHECK-NEXT: 2 5 1.00 * rclb (%rax)
+# CHECK-NEXT: 2 5 1.00 * rcrb (%rax)
+# CHECK-NEXT: 9 4 4.00 rclb $7, %dil
+# CHECK-NEXT: 7 3 3.00 rcrb $7, %dil
+# CHECK-NEXT: 11 8 4.00 * rclb $7, (%rax)
+# CHECK-NEXT: 10 7 4.00 * rcrb $7, (%rax)
+# CHECK-NEXT: 9 4 4.00 rclb %cl, %dil
+# CHECK-NEXT: 7 3 3.00 rcrb %cl, %dil
+# CHECK-NEXT: 11 8 4.00 * rclb %cl, (%rax)
+# CHECK-NEXT: 9 7 4.00 * rcrb %cl, (%rax)
+# CHECK-NEXT: 1 1 1.00 rclw %di
+# CHECK-NEXT: 1 1 1.00 rcrw %di
+# CHECK-NEXT: 2 5 1.00 * rclw (%rax)
+# CHECK-NEXT: 2 5 1.00 * rcrw (%rax)
+# CHECK-NEXT: 9 4 4.00 rclw $7, %di
+# CHECK-NEXT: 7 3 3.00 rcrw $7, %di
+# CHECK-NEXT: 11 8 4.00 * rclw $7, (%rax)
+# CHECK-NEXT: 10 7 4.00 * rcrw $7, (%rax)
+# CHECK-NEXT: 9 4 4.00 rclw %cl, %di
+# CHECK-NEXT: 7 3 3.00 rcrw %cl, %di
+# CHECK-NEXT: 11 8 4.00 * rclw %cl, (%rax)
+# CHECK-NEXT: 9 7 4.00 * rcrw %cl, (%rax)
+# CHECK-NEXT: 1 1 1.00 rcll %edi
+# CHECK-NEXT: 1 1 1.00 rcrl %edi
+# CHECK-NEXT: 2 5 1.00 * rcll (%rax)
+# CHECK-NEXT: 2 5 1.00 * rcrl (%rax)
+# CHECK-NEXT: 9 4 4.00 rcll $7, %edi
+# CHECK-NEXT: 7 3 3.00 rcrl $7, %edi
+# CHECK-NEXT: 11 8 4.00 * rcll $7, (%rax)
+# CHECK-NEXT: 10 7 4.00 * rcrl $7, (%rax)
+# CHECK-NEXT: 9 4 4.00 rcll %cl, %edi
+# CHECK-NEXT: 7 3 3.00 rcrl %cl, %edi
+# CHECK-NEXT: 11 8 4.00 * rcll %cl, (%rax)
+# CHECK-NEXT: 9 7 4.00 * rcrl %cl, (%rax)
+# CHECK-NEXT: 1 1 1.00 rclq %rdi
+# CHECK-NEXT: 1 1 1.00 rcrq %rdi
+# CHECK-NEXT: 2 5 1.00 * rclq (%rax)
+# CHECK-NEXT: 2 5 1.00 * rcrq (%rax)
+# CHECK-NEXT: 9 4 4.00 rclq $7, %rdi
+# CHECK-NEXT: 7 3 3.00 rcrq $7, %rdi
+# CHECK-NEXT: 11 8 4.00 * rclq $7, (%rax)
+# CHECK-NEXT: 10 7 4.00 * rcrq $7, (%rax)
+# CHECK-NEXT: 9 4 4.00 rclq %cl, %rdi
+# CHECK-NEXT: 7 3 3.00 rcrq %cl, %rdi
+# CHECK-NEXT: 11 8 4.00 * rclq %cl, (%rax)
+# CHECK-NEXT: 9 7 4.00 * rcrq %cl, (%rax)
+# CHECK-NEXT: 100 100 25.00 U rdmsr
+# CHECK-NEXT: 100 100 25.00 U rdpmc
+# CHECK-NEXT: 100 100 25.00 U rdtsc
+# CHECK-NEXT: 100 100 25.00 U rdtscp
+# CHECK-NEXT: 1 1 0.50 rolb %dil
+# CHECK-NEXT: 1 1 0.50 rorb %dil
+# CHECK-NEXT: 2 5 0.67 * * rolb (%rax)
+# CHECK-NEXT: 2 5 0.67 * * rorb (%rax)
+# CHECK-NEXT: 1 1 0.50 rolb $7, %dil
+# CHECK-NEXT: 1 1 0.50 rorb $7, %dil
+# CHECK-NEXT: 2 5 0.67 * * rolb $7, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * rorb $7, (%rax)
+# CHECK-NEXT: 1 1 0.50 rolb %cl, %dil
+# CHECK-NEXT: 1 1 0.50 rorb %cl, %dil
+# CHECK-NEXT: 2 5 0.67 * * rolb %cl, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * rorb %cl, (%rax)
+# CHECK-NEXT: 1 1 0.50 rolw %di
+# CHECK-NEXT: 1 1 0.50 rorw %di
+# CHECK-NEXT: 2 5 0.67 * * rolw (%rax)
+# CHECK-NEXT: 2 5 0.67 * * rorw (%rax)
+# CHECK-NEXT: 1 1 0.50 rolw $7, %di
+# CHECK-NEXT: 1 1 0.50 rorw $7, %di
+# CHECK-NEXT: 2 5 0.67 * * rolw $7, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * rorw $7, (%rax)
+# CHECK-NEXT: 1 1 0.50 rolw %cl, %di
+# CHECK-NEXT: 1 1 0.50 rorw %cl, %di
+# CHECK-NEXT: 2 5 0.67 * * rolw %cl, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * rorw %cl, (%rax)
+# CHECK-NEXT: 1 1 0.50 roll %edi
+# CHECK-NEXT: 1 1 0.50 rorl %edi
+# CHECK-NEXT: 2 5 0.67 * * roll (%rax)
+# CHECK-NEXT: 2 5 0.67 * * rorl (%rax)
+# CHECK-NEXT: 1 1 0.50 roll $7, %edi
+# CHECK-NEXT: 1 1 0.50 rorl $7, %edi
+# CHECK-NEXT: 2 5 0.67 * * roll $7, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * rorl $7, (%rax)
+# CHECK-NEXT: 1 1 0.50 roll %cl, %edi
+# CHECK-NEXT: 1 1 0.50 rorl %cl, %edi
+# CHECK-NEXT: 2 5 0.67 * * roll %cl, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * rorl %cl, (%rax)
+# CHECK-NEXT: 1 1 0.50 rolq %rdi
+# CHECK-NEXT: 1 1 0.50 rorq %rdi
+# CHECK-NEXT: 2 5 0.67 * * rolq (%rax)
+# CHECK-NEXT: 2 5 0.67 * * rorq (%rax)
+# CHECK-NEXT: 1 1 0.50 rolq $7, %rdi
+# CHECK-NEXT: 1 1 0.50 rorq $7, %rdi
+# CHECK-NEXT: 2 5 0.67 * * rolq $7, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * rorq $7, (%rax)
+# CHECK-NEXT: 1 1 0.50 rolq %cl, %rdi
+# CHECK-NEXT: 1 1 0.50 rorq %cl, %rdi
+# CHECK-NEXT: 2 5 0.67 * * rolq %cl, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * rorq %cl, (%rax)
+# CHECK-NEXT: 1 1 1.00 sahf
+# CHECK-NEXT: 1 1 0.50 sarb %dil
+# CHECK-NEXT: 1 1 0.50 shlb %dil
+# CHECK-NEXT: 1 1 0.50 shrb %dil
+# CHECK-NEXT: 2 5 0.67 * * sarb (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shlb (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shrb (%rax)
+# CHECK-NEXT: 1 1 0.50 sarb $7, %dil
+# CHECK-NEXT: 1 1 0.50 shlb $7, %dil
+# CHECK-NEXT: 1 1 0.50 shrb $7, %dil
+# CHECK-NEXT: 2 5 0.67 * * sarb $7, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shlb $7, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shrb $7, (%rax)
+# CHECK-NEXT: 1 1 0.50 sarb %cl, %dil
+# CHECK-NEXT: 1 1 0.50 shlb %cl, %dil
+# CHECK-NEXT: 1 1 0.50 shrb %cl, %dil
+# CHECK-NEXT: 2 5 0.67 * * sarb %cl, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shlb %cl, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shrb %cl, (%rax)
+# CHECK-NEXT: 1 1 0.50 sarw %di
+# CHECK-NEXT: 1 1 0.50 shlw %di
+# CHECK-NEXT: 1 1 0.50 shrw %di
+# CHECK-NEXT: 2 5 0.67 * * sarw (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shlw (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shrw (%rax)
+# CHECK-NEXT: 1 1 0.50 sarw $7, %di
+# CHECK-NEXT: 1 1 0.50 shlw $7, %di
+# CHECK-NEXT: 1 1 0.50 shrw $7, %di
+# CHECK-NEXT: 2 5 0.67 * * sarw $7, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shlw $7, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shrw $7, (%rax)
+# CHECK-NEXT: 1 1 0.50 sarw %cl, %di
+# CHECK-NEXT: 1 1 0.50 shlw %cl, %di
+# CHECK-NEXT: 1 1 0.50 shrw %cl, %di
+# CHECK-NEXT: 2 5 0.67 * * sarw %cl, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shlw %cl, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shrw %cl, (%rax)
+# CHECK-NEXT: 1 1 0.50 sarl %edi
+# CHECK-NEXT: 1 1 0.50 shll %edi
+# CHECK-NEXT: 1 1 0.50 shrl %edi
+# CHECK-NEXT: 2 5 0.67 * * sarl (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shll (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shrl (%rax)
+# CHECK-NEXT: 1 1 0.50 sarl $7, %edi
+# CHECK-NEXT: 1 1 0.50 shll $7, %edi
+# CHECK-NEXT: 1 1 0.50 shrl $7, %edi
+# CHECK-NEXT: 2 5 0.67 * * sarl $7, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shll $7, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shrl $7, (%rax)
+# CHECK-NEXT: 1 1 0.50 sarl %cl, %edi
+# CHECK-NEXT: 1 1 0.50 shll %cl, %edi
+# CHECK-NEXT: 1 1 0.50 shrl %cl, %edi
+# CHECK-NEXT: 2 5 0.67 * * sarl %cl, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shll %cl, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shrl %cl, (%rax)
+# CHECK-NEXT: 1 1 0.50 sarq %rdi
+# CHECK-NEXT: 1 1 0.50 shlq %rdi
+# CHECK-NEXT: 1 1 0.50 shrq %rdi
+# CHECK-NEXT: 2 5 0.67 * * sarq (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shlq (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shrq (%rax)
+# CHECK-NEXT: 1 1 0.50 sarq $7, %rdi
+# CHECK-NEXT: 1 1 0.50 shlq $7, %rdi
+# CHECK-NEXT: 1 1 0.50 shrq $7, %rdi
+# CHECK-NEXT: 2 5 0.67 * * sarq $7, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shlq $7, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shrq $7, (%rax)
+# CHECK-NEXT: 1 1 0.50 sarq %cl, %rdi
+# CHECK-NEXT: 1 1 0.50 shlq %cl, %rdi
+# CHECK-NEXT: 1 1 0.50 shrq %cl, %rdi
+# CHECK-NEXT: 2 5 0.67 * * sarq %cl, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shlq %cl, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shrq %cl, (%rax)
+# CHECK-NEXT: 1 1 1.00 sbbb $0, %al
+# CHECK-NEXT: 1 1 1.00 sbbb $0, %dil
+# CHECK-NEXT: 1 6 1.00 * * sbbb $0, (%rax)
+# CHECK-NEXT: 1 1 1.00 sbbb $7, %al
+# CHECK-NEXT: 1 1 1.00 sbbb $7, %dil
+# CHECK-NEXT: 1 6 1.00 * * sbbb $7, (%rax)
+# CHECK-NEXT: 1 1 1.00 sbbb %sil, %dil
+# CHECK-NEXT: 1 1 1.75 * * sbbb %sil, (%rax)
+# CHECK-NEXT: 1 5 1.00 * sbbb (%rax), %dil
+# CHECK-NEXT: 1 1 1.00 sbbw $0, %ax
+# CHECK-NEXT: 1 1 1.00 sbbw $0, %di
+# CHECK-NEXT: 1 6 1.00 * * sbbw $0, (%rax)
+# CHECK-NEXT: 1 1 1.00 sbbw $511, %ax
+# CHECK-NEXT: 1 1 1.00 sbbw $511, %di
+# CHECK-NEXT: 1 6 1.00 * * sbbw $511, (%rax)
+# CHECK-NEXT: 1 1 1.00 sbbw $7, %di
+# CHECK-NEXT: 1 6 1.00 * * sbbw $7, (%rax)
+# CHECK-NEXT: 1 1 1.00 sbbw %si, %di
+# CHECK-NEXT: 1 6 1.00 * * sbbw %si, (%rax)
+# CHECK-NEXT: 1 5 1.00 * sbbw (%rax), %di
+# CHECK-NEXT: 1 1 1.00 sbbl $0, %eax
+# CHECK-NEXT: 1 1 1.00 sbbl $0, %edi
+# CHECK-NEXT: 1 6 1.00 * * sbbl $0, (%rax)
+# CHECK-NEXT: 1 1 1.00 sbbl $665536, %eax
+# CHECK-NEXT: 1 1 1.00 sbbl $665536, %edi
+# CHECK-NEXT: 1 6 1.00 * * sbbl $665536, (%rax)
+# CHECK-NEXT: 1 1 1.00 sbbl $7, %edi
+# CHECK-NEXT: 1 6 1.00 * * sbbl $7, (%rax)
+# CHECK-NEXT: 1 1 1.00 sbbl %esi, %edi
+# CHECK-NEXT: 1 6 1.00 * * sbbl %esi, (%rax)
+# CHECK-NEXT: 1 5 1.00 * sbbl (%rax), %edi
+# CHECK-NEXT: 1 1 1.00 sbbq $0, %rax
+# CHECK-NEXT: 1 1 1.00 sbbq $0, %rdi
+# CHECK-NEXT: 1 6 1.00 * * sbbq $0, (%rax)
+# CHECK-NEXT: 1 1 1.00 sbbq $665536, %rax
+# CHECK-NEXT: 1 1 1.00 sbbq $665536, %rdi
+# CHECK-NEXT: 1 6 1.00 * * sbbq $665536, (%rax)
+# CHECK-NEXT: 1 1 1.00 sbbq $7, %rdi
+# CHECK-NEXT: 1 6 1.00 * * sbbq $7, (%rax)
+# CHECK-NEXT: 1 1 1.00 sbbq %rsi, %rdi
+# CHECK-NEXT: 1 6 1.00 * * sbbq %rsi, (%rax)
+# CHECK-NEXT: 1 5 1.00 * sbbq (%rax), %rdi
+# CHECK-NEXT: 100 100 25.00 U scasb %es:(%rdi), %al
+# CHECK-NEXT: 100 100 25.00 U scasw %es:(%rdi), %ax
+# CHECK-NEXT: 100 100 25.00 U scasl %es:(%rdi), %eax
+# CHECK-NEXT: 100 100 25.00 U scasq %es:(%rdi), %rax
+# CHECK-NEXT: 1 1 1.00 seto %al
+# CHECK-NEXT: 2 2 1.00 * seto (%rax)
+# CHECK-NEXT: 1 1 1.00 setno %al
+# CHECK-NEXT: 2 2 1.00 * setno (%rax)
+# CHECK-NEXT: 1 1 1.00 setb %al
+# CHECK-NEXT: 2 2 1.00 * setb (%rax)
+# CHECK-NEXT: 1 1 1.00 setae %al
+# CHECK-NEXT: 2 2 1.00 * setae (%rax)
+# CHECK-NEXT: 1 1 1.00 sete %al
+# CHECK-NEXT: 2 2 1.00 * sete (%rax)
+# CHECK-NEXT: 1 1 1.00 setne %al
+# CHECK-NEXT: 2 2 1.00 * setne (%rax)
+# CHECK-NEXT: 1 1 1.00 seta %al
+# CHECK-NEXT: 2 2 1.00 * seta (%rax)
+# CHECK-NEXT: 1 1 1.00 setbe %al
+# CHECK-NEXT: 2 2 1.00 * setbe (%rax)
+# CHECK-NEXT: 1 1 1.00 sets %al
+# CHECK-NEXT: 2 2 1.00 * sets (%rax)
+# CHECK-NEXT: 1 1 1.00 setns %al
+# CHECK-NEXT: 2 2 1.00 * setns (%rax)
+# CHECK-NEXT: 1 1 1.00 setp %al
+# CHECK-NEXT: 2 2 1.00 * setp (%rax)
+# CHECK-NEXT: 1 1 1.00 setnp %al
+# CHECK-NEXT: 2 2 1.00 * setnp (%rax)
+# CHECK-NEXT: 1 1 1.00 setl %al
+# CHECK-NEXT: 2 2 1.00 * setl (%rax)
+# CHECK-NEXT: 1 1 1.00 setge %al
+# CHECK-NEXT: 2 2 1.00 * setge (%rax)
+# CHECK-NEXT: 1 1 1.00 setg %al
+# CHECK-NEXT: 2 2 1.00 * setg (%rax)
+# CHECK-NEXT: 1 1 1.00 setle %al
+# CHECK-NEXT: 2 2 1.00 * setle (%rax)
+# CHECK-NEXT: 5 2 1.50 shldw %cl, %si, %di
+# CHECK-NEXT: 5 2 1.50 shrdw %cl, %si, %di
+# CHECK-NEXT: 6 6 2.00 * * shldw %cl, %si, (%rax)
+# CHECK-NEXT: 6 6 2.00 * * shrdw %cl, %si, (%rax)
+# CHECK-NEXT: 4 2 1.50 shldw $7, %si, %di
+# CHECK-NEXT: 4 2 1.50 shrdw $7, %si, %di
+# CHECK-NEXT: 6 6 2.00 * * shldw $7, %si, (%rax)
+# CHECK-NEXT: 6 6 2.00 * * shrdw $7, %si, (%rax)
+# CHECK-NEXT: 5 2 1.50 shldl %cl, %esi, %edi
+# CHECK-NEXT: 5 2 1.50 shrdl %cl, %esi, %edi
+# CHECK-NEXT: 6 6 2.00 * * shldl %cl, %esi, (%rax)
+# CHECK-NEXT: 6 6 2.00 * * shrdl %cl, %esi, (%rax)
+# CHECK-NEXT: 4 2 1.50 shldl $7, %esi, %edi
+# CHECK-NEXT: 4 2 1.50 shrdl $7, %esi, %edi
+# CHECK-NEXT: 6 6 2.00 * * shldl $7, %esi, (%rax)
+# CHECK-NEXT: 6 6 2.00 * * shrdl $7, %esi, (%rax)
+# CHECK-NEXT: 5 2 1.50 shldq %cl, %rsi, %rdi
+# CHECK-NEXT: 5 2 1.50 shrdq %cl, %rsi, %rdi
+# CHECK-NEXT: 6 6 2.00 * * shldq %cl, %rsi, (%rax)
+# CHECK-NEXT: 6 6 2.00 * * shrdq %cl, %rsi, (%rax)
+# CHECK-NEXT: 4 2 1.50 shldq $7, %rsi, %rdi
+# CHECK-NEXT: 4 2 1.50 shrdq $7, %rsi, %rdi
+# CHECK-NEXT: 6 6 2.00 * * shldq $7, %rsi, (%rax)
+# CHECK-NEXT: 6 6 2.00 * * shrdq $7, %rsi, (%rax)
+# CHECK-NEXT: 1 1 0.25 U stc
+# CHECK-NEXT: 1 1 0.25 U std
+# CHECK-NEXT: 100 100 25.00 U stosb %al, %es:(%rdi)
+# CHECK-NEXT: 100 100 25.00 U stosw %ax, %es:(%rdi)
+# CHECK-NEXT: 100 100 25.00 U stosl %eax, %es:(%rdi)
+# CHECK-NEXT: 100 100 25.00 U stosq %rax, %es:(%rdi)
+# CHECK-NEXT: 1 1 1.00 subb $7, %al
+# CHECK-NEXT: 1 1 0.25 subb $7, %dil
+# CHECK-NEXT: 1 6 0.67 * * subb $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 subb %sil, %dil
+# CHECK-NEXT: 1 6 0.67 * * subb %sil, (%rax)
+# CHECK-NEXT: 1 5 0.33 * subb (%rax), %dil
+# CHECK-NEXT: 1 1 1.00 subw $511, %ax
+# CHECK-NEXT: 1 1 0.25 subw $511, %di
+# CHECK-NEXT: 1 6 0.67 * * subw $511, (%rax)
+# CHECK-NEXT: 1 1 0.25 subw $7, %di
+# CHECK-NEXT: 1 6 0.67 * * subw $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 subw %si, %di
+# CHECK-NEXT: 1 6 0.67 * * subw %si, (%rax)
+# CHECK-NEXT: 1 5 0.33 * subw (%rax), %di
+# CHECK-NEXT: 1 1 1.00 subl $665536, %eax
+# CHECK-NEXT: 1 1 0.25 subl $665536, %edi
+# CHECK-NEXT: 1 6 0.67 * * subl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.25 subl $7, %edi
+# CHECK-NEXT: 1 6 0.67 * * subl $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 subl %esi, %edi
+# CHECK-NEXT: 1 6 0.67 * * subl %esi, (%rax)
+# CHECK-NEXT: 1 5 0.33 * subl (%rax), %edi
+# CHECK-NEXT: 1 1 1.00 subq $665536, %rax
+# CHECK-NEXT: 1 1 0.25 subq $665536, %rdi
+# CHECK-NEXT: 1 6 0.67 * * subq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.25 subq $7, %rdi
+# CHECK-NEXT: 1 6 0.67 * * subq $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 subq %rsi, %rdi
+# CHECK-NEXT: 1 6 0.67 * * subq %rsi, (%rax)
+# CHECK-NEXT: 1 5 0.33 * subq (%rax), %rdi
+# CHECK-NEXT: 1 1 0.25 testb $7, %al
+# CHECK-NEXT: 1 1 0.25 testb $7, %dil
+# CHECK-NEXT: 1 5 0.33 * testb $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 testb %sil, %dil
+# CHECK-NEXT: 1 5 0.33 * testb %sil, (%rax)
+# CHECK-NEXT: 1 1 0.25 testw $511, %ax
+# CHECK-NEXT: 1 1 0.25 testw $511, %di
+# CHECK-NEXT: 1 5 0.33 * testw $511, (%rax)
+# CHECK-NEXT: 1 1 0.25 testw $7, %di
+# CHECK-NEXT: 1 5 0.33 * testw $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 testw %si, %di
+# CHECK-NEXT: 1 5 0.33 * testw %si, (%rax)
+# CHECK-NEXT: 1 1 0.25 testl $665536, %eax
+# CHECK-NEXT: 1 1 0.25 testl $665536, %edi
+# CHECK-NEXT: 1 5 0.33 * testl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.25 testl $7, %edi
+# CHECK-NEXT: 1 5 0.33 * testl $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 testl %esi, %edi
+# CHECK-NEXT: 1 5 0.33 * testl %esi, (%rax)
+# CHECK-NEXT: 1 1 0.25 testq $665536, %rax
+# CHECK-NEXT: 1 1 0.25 testq $665536, %rdi
+# CHECK-NEXT: 1 5 0.33 * testq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.25 testq $7, %rdi
+# CHECK-NEXT: 1 5 0.33 * testq $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 testq %rsi, %rdi
+# CHECK-NEXT: 1 5 0.33 * testq %rsi, (%rax)
+# CHECK-NEXT: 100 100 25.00 * U ud2
+# CHECK-NEXT: 100 100 25.00 U wrmsr
+# CHECK-NEXT: 2 0 2.00 xaddb %bl, %cl
+# CHECK-NEXT: 1 5 0.67 * * xaddb %bl, (%rcx)
+# CHECK-NEXT: 2 0 2.00 xaddw %bx, %cx
+# CHECK-NEXT: 1 5 0.67 * * xaddw %ax, (%rbx)
+# CHECK-NEXT: 2 0 2.00 xaddl %ebx, %ecx
+# CHECK-NEXT: 1 5 0.67 * * xaddl %eax, (%rbx)
+# CHECK-NEXT: 2 0 2.00 xaddq %rbx, %rcx
+# CHECK-NEXT: 1 5 0.67 * * xaddq %rax, (%rbx)
+# CHECK-NEXT: 2 1 0.50 xchgb %bl, %cl
+# CHECK-NEXT: 5 7 0.50 * * xchgb %bl, (%rbx)
+# CHECK-NEXT: 2 1 0.50 xchgw %bx, %ax
+# CHECK-NEXT: 2 1 0.50 xchgw %bx, %cx
+# CHECK-NEXT: 5 7 0.50 * * xchgw %ax, (%rbx)
+# CHECK-NEXT: 2 0 2.00 xchgl %ebx, %eax
+# CHECK-NEXT: 2 0 2.00 xchgl %ebx, %ecx
+# CHECK-NEXT: 2 6 0.50 * * xchgl %eax, (%rbx)
+# CHECK-NEXT: 2 0 2.00 xchgq %rbx, %rax
+# CHECK-NEXT: 2 0 2.00 xchgq %rbx, %rcx
+# CHECK-NEXT: 2 6 0.50 * * xchgq %rax, (%rbx)
+# CHECK-NEXT: 1 5 0.33 * xlatb
+# CHECK-NEXT: 1 1 1.00 xorb $7, %al
+# CHECK-NEXT: 1 1 0.25 xorb $7, %dil
+# CHECK-NEXT: 1 6 0.67 * * xorb $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 xorb %sil, %dil
+# CHECK-NEXT: 1 6 0.67 * * xorb %sil, (%rax)
+# CHECK-NEXT: 1 5 0.33 * xorb (%rax), %dil
+# CHECK-NEXT: 1 1 1.00 xorw $511, %ax
+# CHECK-NEXT: 1 1 0.25 xorw $511, %di
+# CHECK-NEXT: 1 6 0.67 * * xorw $511, (%rax)
+# CHECK-NEXT: 1 1 0.25 xorw $7, %di
+# CHECK-NEXT: 1 6 0.67 * * xorw $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 xorw %si, %di
+# CHECK-NEXT: 1 6 0.67 * * xorw %si, (%rax)
+# CHECK-NEXT: 1 5 0.33 * xorw (%rax), %di
+# CHECK-NEXT: 1 1 1.00 xorl $665536, %eax
+# CHECK-NEXT: 1 1 0.25 xorl $665536, %edi
+# CHECK-NEXT: 1 6 0.67 * * xorl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.25 xorl $7, %edi
+# CHECK-NEXT: 1 6 0.67 * * xorl $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 xorl %esi, %edi
+# CHECK-NEXT: 1 6 0.67 * * xorl %esi, (%rax)
+# CHECK-NEXT: 1 5 0.33 * xorl (%rax), %edi
+# CHECK-NEXT: 1 1 1.00 xorq $665536, %rax
+# CHECK-NEXT: 1 1 0.25 xorq $665536, %rdi
+# CHECK-NEXT: 1 6 0.67 * * xorq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.25 xorq $7, %rdi
+# CHECK-NEXT: 1 6 0.67 * * xorq $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 xorq %rsi, %rdi
+# CHECK-NEXT: 1 6 0.67 * * xorq %rsi, (%rax)
+# CHECK-NEXT: 1 5 0.33 * xorq (%rax), %rdi
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: 176.00 176.00 176.00 1677.50 1832.50 1712.50 1475.50 - - - - - - - - 175.33 175.33 175.33 109.00 109.00 109.00 99.50 99.50
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - adcb $0, %al
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - adcb $0, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 1.00 1.00 1.00 1.00 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 adcb $0, (%rax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - adcb $7, %al
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - adcb $7, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 1.00 1.00 1.00 1.00 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 adcb $7, (%rax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - adcb %sil, %dil
+# CHECK-NEXT: 0.33 0.33 0.33 1.75 1.75 1.75 1.75 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 adcb %sil, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 1.00 1.00 1.00 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - adcb (%rax), %dil
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - adcw $0, %ax
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - adcw $0, %di
+# CHECK-NEXT: 0.67 0.67 0.67 1.00 1.00 1.00 1.00 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 adcw $0, (%rax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - adcw $511, %ax
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - adcw $511, %di
+# CHECK-NEXT: 0.67 0.67 0.67 1.00 1.00 1.00 1.00 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 adcw $511, (%rax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - adcw $7, %di
+# CHECK-NEXT: 0.67 0.67 0.67 1.00 1.00 1.00 1.00 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 adcw $7, (%rax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - adcw %si, %di
+# CHECK-NEXT: 0.67 0.67 0.67 1.00 1.00 1.00 1.00 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 adcw %si, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 1.00 1.00 1.00 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - adcw (%rax), %di
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - adcl $0, %eax
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - adcl $0, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 1.00 1.00 1.00 1.00 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 adcl $0, (%rax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - adcl $665536, %eax
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - adcl $665536, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 1.00 1.00 1.00 1.00 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 adcl $665536, (%rax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - adcl $7, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 1.00 1.00 1.00 1.00 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 adcl $7, (%rax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - adcl %esi, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 1.00 1.00 1.00 1.00 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 adcl %esi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 1.00 1.00 1.00 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - adcl (%rax), %edi
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - adcq $0, %rax
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - adcq $0, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 1.00 1.00 1.00 1.00 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 adcq $0, (%rax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - adcq $665536, %rax
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - adcq $665536, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 1.00 1.00 1.00 1.00 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 adcq $665536, (%rax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - adcq $7, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 1.00 1.00 1.00 1.00 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 adcq $7, (%rax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - adcq %rsi, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 1.00 1.00 1.00 1.00 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 adcq %rsi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 1.00 1.00 1.00 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - adcq (%rax), %rdi
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - addb $7, %al
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - addb $7, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 addb $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - addb %sil, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 addb %sil, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - addb (%rax), %dil
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - addw $511, %ax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - addw $511, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 addw $511, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - addw $7, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 addw $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - addw %si, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 addw %si, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - addw (%rax), %di
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - addl $665536, %eax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - addl $665536, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 addl $665536, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - addl $7, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 addl $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - addl %esi, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 addl %esi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - addl (%rax), %edi
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - addq $665536, %rax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - addq $665536, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 addq $665536, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - addq $7, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 addq $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - addq %rsi, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 addq %rsi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - addq (%rax), %rdi
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - andb $7, %al
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - andb $7, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 andb $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - andb %sil, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 andb %sil, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - andb (%rax), %dil
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - andw $511, %ax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - andw $511, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 andw $511, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - andw $7, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 andw $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - andw %si, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 andw %si, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - andw (%rax), %di
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - andl $665536, %eax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - andl $665536, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 andl $665536, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - andl $7, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 andl $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - andl %esi, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 andl %esi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - andl (%rax), %edi
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - andq $665536, %rax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - andq $665536, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 andq $665536, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - andq $7, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 andq $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - andq %rsi, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 andq %rsi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - andq (%rax), %rdi
+# CHECK-NEXT: - - - - 3.00 - - - - - - - - - - - - - - - - - - bsfw %si, %di
+# CHECK-NEXT: - - - - 4.00 - - - - - - - - - - - - - - - - - - bsrw %si, %di
+# CHECK-NEXT: 0.33 0.33 0.33 - 3.00 - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - bsfw (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 - 4.00 - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - bsrw (%rax), %di
+# CHECK-NEXT: - - - - 3.00 - - - - - - - - - - - - - - - - - - bsfl %esi, %edi
+# CHECK-NEXT: - - - - 4.00 - - - - - - - - - - - - - - - - - - bsrl %esi, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 - 3.00 - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - bsfl (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 - 4.00 - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - bsrl (%rax), %edi
+# CHECK-NEXT: - - - - 3.00 - - - - - - - - - - - - - - - - - - bsfq %rsi, %rdi
+# CHECK-NEXT: - - - - 4.00 - - - - - - - - - - - - - - - - - - bsrq %rsi, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 - 3.00 - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - bsfq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 - 4.00 - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - bsrq (%rax), %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - bswapl %eax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - bswapq %rax
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - btw %si, %di
+# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - - - - - - - - - - - - btcw %si, %di
+# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - - - - - - - - - - - - btrw %si, %di
+# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - - - - - - - - - - - - btsw %si, %di
+# CHECK-NEXT: 0.33 0.33 0.33 - 0.50 0.50 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - btw %si, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 btcw %si, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 btrw %si, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 btsw %si, (%rax)
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - btw $7, %di
+# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - - - - - - - - - - - - btcw $7, %di
+# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - - - - - - - - - - - - btrw $7, %di
+# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - - - - - - - - - - - - btsw $7, %di
+# CHECK-NEXT: 0.33 0.33 0.33 - 0.50 0.50 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - btw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 btcw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 btrw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 btsw $7, (%rax)
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - btl %esi, %edi
+# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - - - - - - - - - - - - btcl %esi, %edi
+# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - - - - - - - - - - - - btrl %esi, %edi
+# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - - - - - - - - - - - - btsl %esi, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 - 0.50 0.50 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - btl %esi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 btcl %esi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 btrl %esi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 btsl %esi, (%rax)
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - btl $7, %edi
+# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - - - - - - - - - - - - btcl $7, %edi
+# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - - - - - - - - - - - - btrl $7, %edi
+# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - - - - - - - - - - - - btsl $7, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 - 0.50 0.50 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - btl $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 btcl $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 btrl $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 btsl $7, (%rax)
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - btq %rsi, %rdi
+# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - - - - - - - - - - - - btcq %rsi, %rdi
+# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - - - - - - - - - - - - btrq %rsi, %rdi
+# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - - - - - - - - - - - - btsq %rsi, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 - 0.50 0.50 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - btq %rsi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 btcq %rsi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 btrq %rsi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 btsq %rsi, (%rax)
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - btq $7, %rdi
+# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - - - - - - - - - - - - btcq $7, %rdi
+# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - - - - - - - - - - - - btrq $7, %rdi
+# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - - - - - - - - - - - - btsq $7, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 - 0.50 0.50 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - btq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 btcq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 btrq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 btsq $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cbtw
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cwtl
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cltq
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cwtd
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cltd
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cqto
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - clc
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cld
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmc
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmpb $7, %al
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmpb $7, %dil
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmpb $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmpb %sil, %dil
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmpb %sil, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmpb (%rax), %dil
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmpw $511, %ax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmpw $511, %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmpw $511, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmpw $7, %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmpw $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmpw %si, %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmpw %si, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmpw (%rax), %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmpl $665536, %eax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmpl $665536, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmpl $665536, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmpl $7, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmpl $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmpl %esi, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmpl %esi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmpl (%rax), %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmpq $665536, %rax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmpq $665536, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmpq $665536, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmpq $7, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmpq $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmpq %rsi, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmpq %rsi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmpq (%rax), %rdi
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - cmpsb %es:(%rdi), (%rsi)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - cmpsw %es:(%rdi), (%rsi)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - cmpsl %es:(%rdi), (%rsi)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - cmpsq %es:(%rdi), (%rsi)
+# CHECK-NEXT: - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - - - - - - cmpxchgb %cl, %bl
+# CHECK-NEXT: 0.33 0.33 0.33 3.00 3.00 3.00 3.00 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - cmpxchgb %cl, (%rbx)
+# CHECK-NEXT: - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - - - - - - cmpxchgw %cx, %bx
+# CHECK-NEXT: - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - - - - - - cmpxchgw %cx, (%rbx)
+# CHECK-NEXT: - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - - - - - - cmpxchgl %ecx, %ebx
+# CHECK-NEXT: - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - - - - - - cmpxchgl %ecx, (%rbx)
+# CHECK-NEXT: - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - - - - - - cmpxchgq %rcx, %rbx
+# CHECK-NEXT: - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - - - - - - cmpxchgq %rcx, (%rbx)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - cpuid
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - decb %dil
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+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - decw %di
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+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 decl (%rax)
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - - - - imulw %si, %di
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+# CHECK-NEXT: 0.33 0.33 0.33 - 4.00 - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - imulw $7, (%rax), %di
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - - - - imull %esi, %edi
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+# CHECK-NEXT: 0.33 0.33 0.33 - 1.00 - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - imull $665536, (%rax), %edi
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - - - - imull $7, %esi, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 - 1.00 - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - imull $7, (%rax), %edi
+# CHECK-NEXT: - - - - 3.00 - - - - - - - - - - - - - - - - - - imulq %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 - 3.00 - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - imulq (%rax)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - - - - imulq %rsi, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 - 1.00 - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - imulq (%rax), %rdi
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - - - - imulq $665536, %rsi, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 - 1.00 - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - imulq $665536, (%rax), %rdi
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - - - - imulq $7, %rsi, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 - 1.00 - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - imulq $7, (%rax), %rdi
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - inb $7, %al
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - inb %dx, %al
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - inw $7, %ax
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - inw %dx, %ax
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - inl $7, %eax
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - inl %dx, %eax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - incb %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 incb (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - incw %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 incw (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - incl %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 incl (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - incq %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 incq (%rax)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - insb %dx, %es:(%rdi)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - insw %dx, %es:(%rdi)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - insl %dx, %es:(%rdi)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - int $7
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - invlpg (%rax)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - invlpga
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - - - - lahf
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leave
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - lodsb (%rsi), %al
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - lodsw (%rsi), %ax
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - lodsl (%rsi), %eax
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - lodsq (%rsi), %rax
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - movsb (%rsi), %es:(%rdi)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - movsw (%rsi), %es:(%rdi)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - movsl (%rsi), %es:(%rdi)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - movsq (%rsi), %es:(%rdi)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - movsbw %al, %di
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - movzbw %al, %di
+# CHECK-NEXT: 1.00 1.00 1.00 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - movsbw (%rax), %di
+# CHECK-NEXT: 1.00 1.00 1.00 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - movzbw (%rax), %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - movsbl %al, %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - movzbl %al, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - movsbl (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - movzbl (%rax), %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - movsbq %al, %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - movzbq %al, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - movsbq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - movzbq (%rax), %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - movswl %ax, %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - movzwl %ax, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - movswl (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - movzwl (%rax), %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - movswq %ax, %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - movzwq %ax, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - movswq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - movzwq (%rax), %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - movslq %eax, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - movslq (%rax), %rdi
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+# CHECK-NEXT: 0.33 0.33 0.33 - 3.00 - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - mulb (%rax)
+# CHECK-NEXT: - - - - 3.00 - - - - - - - - - - - - - - - - - - mulw %si
+# CHECK-NEXT: 0.33 0.33 0.33 - 3.00 - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - mulw (%rax)
+# CHECK-NEXT: - - - - 3.00 - - - - - - - - - - - - - - - - - - mull %edx
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+# CHECK-NEXT: 0.33 0.33 0.33 - 3.00 - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - mulq (%rax)
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+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 negw (%r9)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - negl %edx
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 negl (%rax)
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+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 negq (%r10)
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+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - nopw %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - nopw (%rcx)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - nopl %esi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - nopl (%r8)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - nopq %rdx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - nopq (%r9)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - notb %dil
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+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 notw (%r9)
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+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 notl (%rax)
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+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 notq (%r10)
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+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - orb $7, %dil
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+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - orw $511, %di
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+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 orw %si, (%rax)
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+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 orl $7, (%rax)
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+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - orl (%rax), %edi
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - orq $665536, %rax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - orq $665536, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 orq $665536, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - orq $7, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 orq $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - orq %rsi, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 orq %rsi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - orq (%rax), %rdi
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - outb %al, $7
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - outb %al, %dx
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - outw %ax, $7
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - outw %ax, %dx
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - outl %eax, $7
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - outl %eax, %dx
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - outsb (%rsi), %dx
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - outsw (%rsi), %dx
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - outsl (%rsi), %dx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - pause
+# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - - - - - - - - - - - - rclb %dil
+# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - - - - - - - - - - - - rcrb %dil
+# CHECK-NEXT: 0.33 0.33 0.33 - 1.00 1.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - rclb (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - 1.00 1.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - rcrb (%rax)
+# CHECK-NEXT: - - - - 4.00 4.00 - - - - - - - - - - - - - - - - - rclb $7, %dil
+# CHECK-NEXT: - - - - 3.00 3.00 - - - - - - - - - - - - - - - - - rcrb $7, %dil
+# CHECK-NEXT: 0.33 0.33 0.33 - 4.00 4.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - rclb $7, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - 4.00 4.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - rcrb $7, (%rax)
+# CHECK-NEXT: - - - - 4.00 4.00 - - - - - - - - - - - - - - - - - rclb %cl, %dil
+# CHECK-NEXT: - - - - 3.00 3.00 - - - - - - - - - - - - - - - - - rcrb %cl, %dil
+# CHECK-NEXT: 0.33 0.33 0.33 - 4.00 4.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - rclb %cl, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - 4.00 4.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - rcrb %cl, (%rax)
+# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - - - - - - - - - - - - rclw %di
+# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - - - - - - - - - - - - rcrw %di
+# CHECK-NEXT: 0.33 0.33 0.33 - 1.00 1.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - rclw (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - 1.00 1.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - rcrw (%rax)
+# CHECK-NEXT: - - - - 4.00 4.00 - - - - - - - - - - - - - - - - - rclw $7, %di
+# CHECK-NEXT: - - - - 3.00 3.00 - - - - - - - - - - - - - - - - - rcrw $7, %di
+# CHECK-NEXT: 0.33 0.33 0.33 - 4.00 4.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - rclw $7, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - 4.00 4.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - rcrw $7, (%rax)
+# CHECK-NEXT: - - - - 4.00 4.00 - - - - - - - - - - - - - - - - - rclw %cl, %di
+# CHECK-NEXT: - - - - 3.00 3.00 - - - - - - - - - - - - - - - - - rcrw %cl, %di
+# CHECK-NEXT: 0.33 0.33 0.33 - 4.00 4.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - rclw %cl, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - 4.00 4.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - rcrw %cl, (%rax)
+# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - - - - - - - - - - - - rcll %edi
+# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - - - - - - - - - - - - rcrl %edi
+# CHECK-NEXT: 0.33 0.33 0.33 - 1.00 1.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - rcll (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - 1.00 1.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - rcrl (%rax)
+# CHECK-NEXT: - - - - 4.00 4.00 - - - - - - - - - - - - - - - - - rcll $7, %edi
+# CHECK-NEXT: - - - - 3.00 3.00 - - - - - - - - - - - - - - - - - rcrl $7, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 - 4.00 4.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - rcll $7, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - 4.00 4.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - rcrl $7, (%rax)
+# CHECK-NEXT: - - - - 4.00 4.00 - - - - - - - - - - - - - - - - - rcll %cl, %edi
+# CHECK-NEXT: - - - - 3.00 3.00 - - - - - - - - - - - - - - - - - rcrl %cl, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 - 4.00 4.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - rcll %cl, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - 4.00 4.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - rcrl %cl, (%rax)
+# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - - - - - - - - - - - - rclq %rdi
+# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - - - - - - - - - - - - rcrq %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 - 1.00 1.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - rclq (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - 1.00 1.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - rcrq (%rax)
+# CHECK-NEXT: - - - - 4.00 4.00 - - - - - - - - - - - - - - - - - rclq $7, %rdi
+# CHECK-NEXT: - - - - 3.00 3.00 - - - - - - - - - - - - - - - - - rcrq $7, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 - 4.00 4.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - rclq $7, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - 4.00 4.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - rcrq $7, (%rax)
+# CHECK-NEXT: - - - - 4.00 4.00 - - - - - - - - - - - - - - - - - rclq %cl, %rdi
+# CHECK-NEXT: - - - - 3.00 3.00 - - - - - - - - - - - - - - - - - rcrq %cl, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 - 4.00 4.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - rclq %cl, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - 4.00 4.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - rcrq %cl, (%rax)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - rdmsr
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - rdpmc
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - rdtsc
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - rdtscp
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - rolb %dil
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - rorb %dil
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 rolb (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 rorb (%rax)
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - rolb $7, %dil
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - rorb $7, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 rolb $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 rorb $7, (%rax)
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - rolb %cl, %dil
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - rorb %cl, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 rolb %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 rorb %cl, (%rax)
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - rolw %di
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - rorw %di
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 rolw (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 rorw (%rax)
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - rolw $7, %di
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - rorw $7, %di
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 rolw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 rorw $7, (%rax)
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - rolw %cl, %di
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - rorw %cl, %di
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 rolw %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 rorw %cl, (%rax)
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - roll %edi
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - rorl %edi
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 roll (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 rorl (%rax)
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - roll $7, %edi
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - rorl $7, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 roll $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 rorl $7, (%rax)
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - roll %cl, %edi
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - rorl %cl, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 roll %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 rorl %cl, (%rax)
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - rolq %rdi
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - rorq %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 rolq (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 rorq (%rax)
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - rolq $7, %rdi
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - rorq $7, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 rolq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 rorq $7, (%rax)
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - rolq %cl, %rdi
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - rorq %cl, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 rolq %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 rorq %cl, (%rax)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - - - - sahf
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - sarb %dil
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - shlb %dil
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - shrb %dil
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 sarb (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 shlb (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 shrb (%rax)
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - sarb $7, %dil
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - shlb $7, %dil
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - shrb $7, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 sarb $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 shlb $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 shrb $7, (%rax)
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - sarb %cl, %dil
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - shlb %cl, %dil
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - shrb %cl, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 sarb %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 shlb %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 shrb %cl, (%rax)
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - sarw %di
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - shlw %di
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - shrw %di
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 sarw (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 shlw (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 shrw (%rax)
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - sarw $7, %di
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - shlw $7, %di
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - shrw $7, %di
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 sarw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 shlw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 shrw $7, (%rax)
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - sarw %cl, %di
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - shlw %cl, %di
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - shrw %cl, %di
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 sarw %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 shlw %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 shrw %cl, (%rax)
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - sarl %edi
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - shll %edi
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - shrl %edi
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 sarl (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 shll (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 shrl (%rax)
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - sarl $7, %edi
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - shll $7, %edi
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - shrl $7, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 sarl $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 shll $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 shrl $7, (%rax)
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - sarl %cl, %edi
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - shll %cl, %edi
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - shrl %cl, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 sarl %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 shll %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 shrl %cl, (%rax)
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - sarq %rdi
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - shlq %rdi
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - shrq %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 sarq (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 shlq (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 shrq (%rax)
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - sarq $7, %rdi
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - shlq $7, %rdi
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - shrq $7, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 sarq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 shlq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 shrq $7, (%rax)
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - sarq %cl, %rdi
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - shlq %cl, %rdi
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - - - - - - shrq %cl, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 sarq %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 shlq %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 - 0.50 0.50 - - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 shrq %cl, (%rax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - sbbb $0, %al
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - sbbb $0, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 1.00 1.00 1.00 1.00 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 sbbb $0, (%rax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - sbbb $7, %al
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - sbbb $7, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 1.00 1.00 1.00 1.00 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 sbbb $7, (%rax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - sbbb %sil, %dil
+# CHECK-NEXT: 0.33 0.33 0.33 1.75 1.75 1.75 1.75 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 sbbb %sil, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 1.00 1.00 1.00 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - sbbb (%rax), %dil
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - sbbw $0, %ax
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - sbbw $0, %di
+# CHECK-NEXT: 0.67 0.67 0.67 1.00 1.00 1.00 1.00 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 sbbw $0, (%rax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - sbbw $511, %ax
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - sbbw $511, %di
+# CHECK-NEXT: 0.67 0.67 0.67 1.00 1.00 1.00 1.00 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 sbbw $511, (%rax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - sbbw $7, %di
+# CHECK-NEXT: 0.67 0.67 0.67 1.00 1.00 1.00 1.00 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 sbbw $7, (%rax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - sbbw %si, %di
+# CHECK-NEXT: 0.67 0.67 0.67 1.00 1.00 1.00 1.00 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 sbbw %si, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 1.00 1.00 1.00 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - sbbw (%rax), %di
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - sbbl $0, %eax
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - sbbl $0, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 1.00 1.00 1.00 1.00 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 sbbl $0, (%rax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - sbbl $665536, %eax
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - sbbl $665536, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 1.00 1.00 1.00 1.00 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 sbbl $665536, (%rax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - sbbl $7, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 1.00 1.00 1.00 1.00 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 sbbl $7, (%rax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - sbbl %esi, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 1.00 1.00 1.00 1.00 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 sbbl %esi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 1.00 1.00 1.00 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - sbbl (%rax), %edi
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - sbbq $0, %rax
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - sbbq $0, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 1.00 1.00 1.00 1.00 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 sbbq $0, (%rax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - sbbq $665536, %rax
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - sbbq $665536, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 1.00 1.00 1.00 1.00 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 sbbq $665536, (%rax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - sbbq $7, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 1.00 1.00 1.00 1.00 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 sbbq $7, (%rax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - sbbq %rsi, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 1.00 1.00 1.00 1.00 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 sbbq %rsi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 1.00 1.00 1.00 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - sbbq (%rax), %rdi
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - scasb %es:(%rdi), %al
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - scasw %es:(%rdi), %ax
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - scasl %es:(%rdi), %eax
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - scasq %es:(%rdi), %rax
+# CHECK-NEXT: - - - 1.00 - - 1.00 - - - - - - - - - - - - - - - - seto %al
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 - - 1.00 - - - - - - - - 0.33 0.33 0.33 - - - 0.50 0.50 seto (%rax)
+# CHECK-NEXT: - - - 1.00 - - 1.00 - - - - - - - - - - - - - - - - setno %al
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 - - 1.00 - - - - - - - - 0.33 0.33 0.33 - - - 0.50 0.50 setno (%rax)
+# CHECK-NEXT: - - - 1.00 - - 1.00 - - - - - - - - - - - - - - - - setb %al
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 - - 1.00 - - - - - - - - 0.33 0.33 0.33 - - - 0.50 0.50 setb (%rax)
+# CHECK-NEXT: - - - 1.00 - - 1.00 - - - - - - - - - - - - - - - - setae %al
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 - - 1.00 - - - - - - - - 0.33 0.33 0.33 - - - 0.50 0.50 setae (%rax)
+# CHECK-NEXT: - - - 1.00 - - 1.00 - - - - - - - - - - - - - - - - sete %al
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 - - 1.00 - - - - - - - - 0.33 0.33 0.33 - - - 0.50 0.50 sete (%rax)
+# CHECK-NEXT: - - - 1.00 - - 1.00 - - - - - - - - - - - - - - - - setne %al
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 - - 1.00 - - - - - - - - 0.33 0.33 0.33 - - - 0.50 0.50 setne (%rax)
+# CHECK-NEXT: - - - 1.00 - - 1.00 - - - - - - - - - - - - - - - - seta %al
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 - - 1.00 - - - - - - - - 0.33 0.33 0.33 - - - 0.50 0.50 seta (%rax)
+# CHECK-NEXT: - - - 1.00 - - 1.00 - - - - - - - - - - - - - - - - setbe %al
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 - - 1.00 - - - - - - - - 0.33 0.33 0.33 - - - 0.50 0.50 setbe (%rax)
+# CHECK-NEXT: - - - 1.00 - - 1.00 - - - - - - - - - - - - - - - - sets %al
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 - - 1.00 - - - - - - - - 0.33 0.33 0.33 - - - 0.50 0.50 sets (%rax)
+# CHECK-NEXT: - - - 1.00 - - 1.00 - - - - - - - - - - - - - - - - setns %al
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 - - 1.00 - - - - - - - - 0.33 0.33 0.33 - - - 0.50 0.50 setns (%rax)
+# CHECK-NEXT: - - - 1.00 - - 1.00 - - - - - - - - - - - - - - - - setp %al
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 - - 1.00 - - - - - - - - 0.33 0.33 0.33 - - - 0.50 0.50 setp (%rax)
+# CHECK-NEXT: - - - 1.00 - - 1.00 - - - - - - - - - - - - - - - - setnp %al
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 - - 1.00 - - - - - - - - 0.33 0.33 0.33 - - - 0.50 0.50 setnp (%rax)
+# CHECK-NEXT: - - - 1.00 - - 1.00 - - - - - - - - - - - - - - - - setl %al
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 - - 1.00 - - - - - - - - 0.33 0.33 0.33 - - - 0.50 0.50 setl (%rax)
+# CHECK-NEXT: - - - 1.00 - - 1.00 - - - - - - - - - - - - - - - - setge %al
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 - - 1.00 - - - - - - - - 0.33 0.33 0.33 - - - 0.50 0.50 setge (%rax)
+# CHECK-NEXT: - - - 1.00 - - 1.00 - - - - - - - - - - - - - - - - setg %al
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 - - 1.00 - - - - - - - - 0.33 0.33 0.33 - - - 0.50 0.50 setg (%rax)
+# CHECK-NEXT: - - - 1.00 - - 1.00 - - - - - - - - - - - - - - - - setle %al
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 - - 1.00 - - - - - - - - 0.33 0.33 0.33 - - - 0.50 0.50 setle (%rax)
+# CHECK-NEXT: - - - - 1.50 1.50 - - - - - - - - - - - - - - - - - shldw %cl, %si, %di
+# CHECK-NEXT: - - - - 1.50 1.50 - - - - - - - - - - - - - - - - - shrdw %cl, %si, %di
+# CHECK-NEXT: 0.33 0.33 0.33 - 2.00 2.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - shldw %cl, %si, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - 2.00 2.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - shrdw %cl, %si, (%rax)
+# CHECK-NEXT: - - - - 1.50 1.50 - - - - - - - - - - - - - - - - - shldw $7, %si, %di
+# CHECK-NEXT: - - - - 1.50 1.50 - - - - - - - - - - - - - - - - - shrdw $7, %si, %di
+# CHECK-NEXT: 0.33 0.33 0.33 - 2.00 2.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - shldw $7, %si, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - 2.00 2.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - shrdw $7, %si, (%rax)
+# CHECK-NEXT: - - - - 1.50 1.50 - - - - - - - - - - - - - - - - - shldl %cl, %esi, %edi
+# CHECK-NEXT: - - - - 1.50 1.50 - - - - - - - - - - - - - - - - - shrdl %cl, %esi, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 - 2.00 2.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - shldl %cl, %esi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - 2.00 2.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - shrdl %cl, %esi, (%rax)
+# CHECK-NEXT: - - - - 1.50 1.50 - - - - - - - - - - - - - - - - - shldl $7, %esi, %edi
+# CHECK-NEXT: - - - - 1.50 1.50 - - - - - - - - - - - - - - - - - shrdl $7, %esi, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 - 2.00 2.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - shldl $7, %esi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - 2.00 2.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - shrdl $7, %esi, (%rax)
+# CHECK-NEXT: - - - - 1.50 1.50 - - - - - - - - - - - - - - - - - shldq %cl, %rsi, %rdi
+# CHECK-NEXT: - - - - 1.50 1.50 - - - - - - - - - - - - - - - - - shrdq %cl, %rsi, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 - 2.00 2.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - shldq %cl, %rsi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - 2.00 2.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - shrdq %cl, %rsi, (%rax)
+# CHECK-NEXT: - - - - 1.50 1.50 - - - - - - - - - - - - - - - - - shldq $7, %rsi, %rdi
+# CHECK-NEXT: - - - - 1.50 1.50 - - - - - - - - - - - - - - - - - shrdq $7, %rsi, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 - 2.00 2.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - shldq $7, %rsi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - 2.00 2.00 - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - shrdq $7, %rsi, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - stc
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - std
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - stosb %al, %es:(%rdi)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - stosw %ax, %es:(%rdi)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - stosl %eax, %es:(%rdi)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - stosq %rax, %es:(%rdi)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - subb $7, %al
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - subb $7, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 subb $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - subb %sil, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 subb %sil, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - subb (%rax), %dil
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - subw $511, %ax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - subw $511, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 subw $511, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - subw $7, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 subw $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - subw %si, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 subw %si, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - subw (%rax), %di
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - subl $665536, %eax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - subl $665536, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 subl $665536, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - subl $7, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 subl $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - subl %esi, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 subl %esi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - subl (%rax), %edi
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - subq $665536, %rax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - subq $665536, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 subq $665536, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - subq $7, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 subq $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - subq %rsi, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 subq %rsi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - subq (%rax), %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - testb $7, %al
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - testb $7, %dil
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - testb $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - testb %sil, %dil
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - testb %sil, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - testw $511, %ax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - testw $511, %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - testw $511, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - testw $7, %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - testw $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - testw %si, %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - testw %si, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - testl $665536, %eax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - testl $665536, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - testl $665536, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - testl $7, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - testl $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - testl %esi, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - testl %esi, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - testq $665536, %rax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - testq $665536, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - testq $665536, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - testq $7, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - testq $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - testq %rsi, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - testq %rsi, (%rax)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - ud2
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - wrmsr
+# CHECK-NEXT: - - - 2.00 2.00 2.00 2.00 - - - - - - - - - - - - - - - - xaddb %bl, %cl
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 xaddb %bl, (%rcx)
+# CHECK-NEXT: - - - 2.00 2.00 2.00 2.00 - - - - - - - - - - - - - - - - xaddw %bx, %cx
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 xaddw %ax, (%rbx)
+# CHECK-NEXT: - - - 2.00 2.00 2.00 2.00 - - - - - - - - - - - - - - - - xaddl %ebx, %ecx
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 xaddl %eax, (%rbx)
+# CHECK-NEXT: - - - 2.00 2.00 2.00 2.00 - - - - - - - - - - - - - - - - xaddq %rbx, %rcx
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 xaddq %rax, (%rbx)
+# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - - - xchgb %bl, %cl
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - xchgb %bl, (%rbx)
+# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - - - xchgw %bx, %ax
+# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - - - xchgw %bx, %cx
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - xchgw %ax, (%rbx)
+# CHECK-NEXT: - - - 2.00 2.00 2.00 2.00 - - - - - - - - - - - - - - - - xchgl %ebx, %eax
+# CHECK-NEXT: - - - 2.00 2.00 2.00 2.00 - - - - - - - - - - - - - - - - xchgl %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - xchgl %eax, (%rbx)
+# CHECK-NEXT: - - - 2.00 2.00 2.00 2.00 - - - - - - - - - - - - - - - - xchgq %rbx, %rax
+# CHECK-NEXT: - - - 2.00 2.00 2.00 2.00 - - - - - - - - - - - - - - - - xchgq %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - xchgq %rax, (%rbx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - xlatb
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - xorb $7, %al
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - xorb $7, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 xorb $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - xorb %sil, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 xorb %sil, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - xorb (%rax), %dil
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - xorw $511, %ax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - xorw $511, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 xorw $511, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - xorw $7, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 xorw $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - xorw %si, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 xorw %si, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - xorw (%rax), %di
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - xorl $665536, %eax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - xorl $665536, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 xorl $665536, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - xorl $7, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 xorl $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - xorl %esi, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 xorl %esi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - xorl (%rax), %edi
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - xorq $665536, %rax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - xorq $665536, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 xorq $665536, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - xorq $7, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 xorq $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - xorq %rsi, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - - - - 0.67 0.67 0.67 0.33 0.33 0.33 0.50 0.50 xorq %rsi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - xorq (%rax), %rdi
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-x87.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-x87.s
new file mode 100644
index 0000000000000..815593d5cdad1
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-x87.s
@@ -0,0 +1,536 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+f2xm1
+
+fabs
+
+fadd %st, %st(1)
+fadd %st(2)
+fadds (%ecx)
+faddl (%ecx)
+faddp %st(1)
+faddp %st(2)
+fiadds (%ecx)
+fiaddl (%ecx)
+
+fbld (%ecx)
+fbstp (%eax)
+
+fchs
+
+fnclex
+
+fcmovb %st(1), %st
+fcmovbe %st(1), %st
+fcmove %st(1), %st
+fcmovnb %st(1), %st
+fcmovnbe %st(1), %st
+fcmovne %st(1), %st
+fcmovnu %st(1), %st
+fcmovu %st(1), %st
+
+fcom %st(1)
+fcom %st(3)
+fcoms (%ecx)
+fcoml (%eax)
+fcomp %st(1)
+fcomp %st(3)
+fcomps (%ecx)
+fcompl (%eax)
+fcompp
+
+fcomi %st(3)
+fcompi %st(3)
+
+fcos
+
+fdecstp
+
+fdiv %st, %st(1)
+fdiv %st(2)
+fdivs (%ecx)
+fdivl (%eax)
+fdivp %st(1)
+fdivp %st(2)
+fidivs (%ecx)
+fidivl (%eax)
+
+fdivr %st, %st(1)
+fdivr %st(2)
+fdivrs (%ecx)
+fdivrl (%eax)
+fdivrp %st(1)
+fdivrp %st(2)
+fidivrs (%ecx)
+fidivrl (%eax)
+
+ffree %st(0)
+
+ficoms (%ecx)
+ficoml (%eax)
+ficomps (%ecx)
+ficompl (%eax)
+
+filds (%edx)
+fildl (%ecx)
+fildll (%eax)
+
+fincstp
+
+fninit
+
+fists (%edx)
+fistl (%ecx)
+fistps (%edx)
+fistpl (%ecx)
+fistpll (%eax)
+
+fisttps (%edx)
+fisttpl (%ecx)
+fisttpll (%eax)
+
+fld %st(0)
+flds (%edx)
+fldl (%ecx)
+fldt (%eax)
+
+fldcw (%eax)
+fldenv (%eax)
+
+fld1
+fldl2e
+fldl2t
+fldlg2
+fldln2
+fldpi
+fldz
+
+fmul %st, %st(1)
+fmul %st(2)
+fmuls (%ecx)
+fmull (%eax)
+fmulp %st(1)
+fmulp %st(2)
+fimuls (%ecx)
+fimull (%eax)
+
+fnop
+
+fpatan
+
+fprem
+fprem1
+
+fptan
+
+frndint
+
+frstor (%eax)
+
+fnsave (%eax)
+
+fscale
+
+fsin
+
+fsincos
+
+fsqrt
+
+fst %st(0)
+fsts (%edx)
+fstl (%ecx)
+fstp %st(0)
+fstpl (%edx)
+fstpl (%ecx)
+fstpt (%eax)
+
+fnstcw (%eax)
+fnstenv (%eax)
+fnstsw (%eax)
+
+frstor (%eax)
+fsave (%eax)
+
+fsub %st, %st(1)
+fsub %st(2)
+fsubs (%ecx)
+fsubl (%eax)
+fsubp %st(1)
+fsubp %st(2)
+fisubs (%ecx)
+fisubl (%eax)
+
+fsubr %st, %st(1)
+fsubr %st(2)
+fsubrs (%ecx)
+fsubrl (%eax)
+fsubrp %st(1)
+fsubrp %st(2)
+fisubrs (%ecx)
+fisubrl (%eax)
+
+ftst
+
+fucom %st(1)
+fucom %st(3)
+fucomp %st(1)
+fucomp %st(3)
+fucompp
+
+fucomi %st(3)
+fucompi %st(3)
+
+fwait
+
+fxam
+
+fxch %st(1)
+fxch %st(3)
+
+fxrstor (%eax)
+fxsave (%eax)
+
+fxtract
+
+fyl2x
+fyl2xp1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 100 100 25.00 U f2xm1
+# CHECK-NEXT: 1 1 1.00 U fabs
+# CHECK-NEXT: 1 3 0.50 U fadd %st, %st(1)
+# CHECK-NEXT: 1 3 0.50 U fadd %st(2), %st
+# CHECK-NEXT: 1 10 0.50 * U fadds (%ecx)
+# CHECK-NEXT: 1 10 0.50 * U faddl (%ecx)
+# CHECK-NEXT: 1 3 0.50 U faddp %st, %st(1)
+# CHECK-NEXT: 1 3 0.50 U faddp %st, %st(2)
+# CHECK-NEXT: 2 5 6.00 * U fiadds (%ecx)
+# CHECK-NEXT: 2 5 6.00 * U fiaddl (%ecx)
+# CHECK-NEXT: 100 100 25.00 * U fbld (%ecx)
+# CHECK-NEXT: 100 100 25.00 * U fbstp (%eax)
+# CHECK-NEXT: 1 1 1.00 U fchs
+# CHECK-NEXT: 100 100 25.00 U fnclex
+# CHECK-NEXT: 7 7 7.00 U fcmovb %st(1), %st
+# CHECK-NEXT: 7 7 7.00 U fcmovbe %st(1), %st
+# CHECK-NEXT: 7 7 7.00 U fcmove %st(1), %st
+# CHECK-NEXT: 7 7 7.00 U fcmovnb %st(1), %st
+# CHECK-NEXT: 7 7 7.00 U fcmovnbe %st(1), %st
+# CHECK-NEXT: 7 7 7.00 U fcmovne %st(1), %st
+# CHECK-NEXT: 7 7 7.00 U fcmovnu %st(1), %st
+# CHECK-NEXT: 7 7 7.00 U fcmovu %st(1), %st
+# CHECK-NEXT: 1 3 1.00 U fcom %st(1)
+# CHECK-NEXT: 1 3 1.00 U fcom %st(3)
+# CHECK-NEXT: 1 10 1.00 * U fcoms (%ecx)
+# CHECK-NEXT: 1 10 1.00 * U fcoml (%eax)
+# CHECK-NEXT: 1 3 1.00 U fcomp %st(1)
+# CHECK-NEXT: 1 3 1.00 U fcomp %st(3)
+# CHECK-NEXT: 1 10 1.00 * U fcomps (%ecx)
+# CHECK-NEXT: 1 10 1.00 * U fcompl (%eax)
+# CHECK-NEXT: 100 100 25.00 U fcompp
+# CHECK-NEXT: 1 3 1.00 U fcomi %st(3), %st
+# CHECK-NEXT: 1 3 1.00 U fcompi %st(3), %st
+# CHECK-NEXT: 100 100 25.00 U fcos
+# CHECK-NEXT: 100 100 25.00 U fdecstp
+# CHECK-NEXT: 1 11 3.00 U fdiv %st, %st(1)
+# CHECK-NEXT: 1 11 3.00 U fdiv %st(2), %st
+# CHECK-NEXT: 1 18 3.00 * U fdivs (%ecx)
+# CHECK-NEXT: 1 18 3.00 * U fdivl (%eax)
+# CHECK-NEXT: 1 11 3.00 U fdivp %st, %st(1)
+# CHECK-NEXT: 1 11 3.00 U fdivp %st, %st(2)
+# CHECK-NEXT: 2 5 15.50 * U fidivs (%ecx)
+# CHECK-NEXT: 2 5 15.50 * U fidivl (%eax)
+# CHECK-NEXT: 1 11 3.00 U fdivr %st, %st(1)
+# CHECK-NEXT: 1 11 3.00 U fdivr %st(2), %st
+# CHECK-NEXT: 1 18 3.00 * U fdivrs (%ecx)
+# CHECK-NEXT: 1 18 3.00 * U fdivrl (%eax)
+# CHECK-NEXT: 1 11 3.00 U fdivrp %st, %st(1)
+# CHECK-NEXT: 1 11 3.00 U fdivrp %st, %st(2)
+# CHECK-NEXT: 2 5 15.50 * U fidivrs (%ecx)
+# CHECK-NEXT: 2 5 15.50 * U fidivrl (%eax)
+# CHECK-NEXT: 100 100 25.00 U ffree %st(0)
+# CHECK-NEXT: 1 10 1.00 * U ficoms (%ecx)
+# CHECK-NEXT: 1 10 1.00 * U ficoml (%eax)
+# CHECK-NEXT: 1 10 1.00 * U ficomps (%ecx)
+# CHECK-NEXT: 1 10 1.00 * U ficompl (%eax)
+# CHECK-NEXT: 1 5 0.33 * U filds (%edx)
+# CHECK-NEXT: 1 5 0.33 * U fildl (%ecx)
+# CHECK-NEXT: 1 5 0.33 * U fildll (%eax)
+# CHECK-NEXT: 100 100 25.00 U fincstp
+# CHECK-NEXT: 100 100 25.00 U fninit
+# CHECK-NEXT: 1 1 1.00 * U fists (%edx)
+# CHECK-NEXT: 1 1 1.00 * U fistl (%ecx)
+# CHECK-NEXT: 1 1 1.00 * U fistps (%edx)
+# CHECK-NEXT: 1 1 1.00 * U fistpl (%ecx)
+# CHECK-NEXT: 1 1 1.00 * U fistpll (%eax)
+# CHECK-NEXT: 1 1 1.00 * U fisttps (%edx)
+# CHECK-NEXT: 1 1 1.00 * U fisttpl (%ecx)
+# CHECK-NEXT: 1 1 1.00 * U fisttpll (%eax)
+# CHECK-NEXT: 1 1 1.00 U fld %st(0)
+# CHECK-NEXT: 1 5 0.33 * U flds (%edx)
+# CHECK-NEXT: 1 5 0.33 * U fldl (%ecx)
+# CHECK-NEXT: 1 5 0.33 * U fldt (%eax)
+# CHECK-NEXT: 1 5 0.33 * U fldcw (%eax)
+# CHECK-NEXT: 100 100 25.00 * U fldenv (%eax)
+# CHECK-NEXT: 1 11 1.00 U fld1
+# CHECK-NEXT: 1 11 1.00 U fldl2e
+# CHECK-NEXT: 1 11 1.00 U fldl2t
+# CHECK-NEXT: 1 11 1.00 U fldlg2
+# CHECK-NEXT: 1 11 1.00 U fldln2
+# CHECK-NEXT: 1 11 1.00 U fldpi
+# CHECK-NEXT: 1 8 1.00 U fldz
+# CHECK-NEXT: 1 3 0.50 U fmul %st, %st(1)
+# CHECK-NEXT: 1 3 0.50 U fmul %st(2), %st
+# CHECK-NEXT: 1 10 0.50 * U fmuls (%ecx)
+# CHECK-NEXT: 1 10 0.50 * U fmull (%eax)
+# CHECK-NEXT: 1 3 0.50 U fmulp %st, %st(1)
+# CHECK-NEXT: 1 3 0.50 U fmulp %st, %st(2)
+# CHECK-NEXT: 2 5 6.00 * U fimuls (%ecx)
+# CHECK-NEXT: 2 5 6.00 * U fimull (%eax)
+# CHECK-NEXT: 1 0 0.25 U fnop
+# CHECK-NEXT: 100 100 25.00 U fpatan
+# CHECK-NEXT: 100 100 25.00 U fprem
+# CHECK-NEXT: 100 100 25.00 U fprem1
+# CHECK-NEXT: 100 100 25.00 U fptan
+# CHECK-NEXT: 100 100 25.00 U frndint
+# CHECK-NEXT: 100 100 25.00 * U frstor (%eax)
+# CHECK-NEXT: 100 100 25.00 * U fnsave (%eax)
+# CHECK-NEXT: 100 100 25.00 U fscale
+# CHECK-NEXT: 100 100 25.00 U fsin
+# CHECK-NEXT: 100 100 25.00 U fsincos
+# CHECK-NEXT: 1 22 23.00 U fsqrt
+# CHECK-NEXT: 1 1 1.00 U fst %st(0)
+# CHECK-NEXT: 1 1 1.00 * U fsts (%edx)
+# CHECK-NEXT: 1 1 1.00 * U fstl (%ecx)
+# CHECK-NEXT: 1 1 1.00 U fstp %st(0)
+# CHECK-NEXT: 1 1 1.00 * U fstpl (%edx)
+# CHECK-NEXT: 1 1 1.00 * U fstpl (%ecx)
+# CHECK-NEXT: 1 1 1.00 * U fstpt (%eax)
+# CHECK-NEXT: 1 1 0.25 * U fnstcw (%eax)
+# CHECK-NEXT: 100 100 25.00 * U fnstenv (%eax)
+# CHECK-NEXT: 100 100 25.00 * U fnstsw (%eax)
+# CHECK-NEXT: 100 100 25.00 * U frstor (%eax)
+# CHECK-NEXT: 100 100 25.00 U wait
+# CHECK-NEXT: 100 100 25.00 * U fnsave (%eax)
+# CHECK-NEXT: 1 3 0.50 U fsub %st, %st(1)
+# CHECK-NEXT: 1 3 0.50 U fsub %st(2), %st
+# CHECK-NEXT: 1 10 0.50 * U fsubs (%ecx)
+# CHECK-NEXT: 1 10 0.50 * U fsubl (%eax)
+# CHECK-NEXT: 1 3 0.50 U fsubp %st, %st(1)
+# CHECK-NEXT: 1 3 0.50 U fsubp %st, %st(2)
+# CHECK-NEXT: 2 5 6.00 * U fisubs (%ecx)
+# CHECK-NEXT: 2 5 6.00 * U fisubl (%eax)
+# CHECK-NEXT: 1 3 0.50 U fsubr %st, %st(1)
+# CHECK-NEXT: 1 3 0.50 U fsubr %st(2), %st
+# CHECK-NEXT: 1 10 0.50 * U fsubrs (%ecx)
+# CHECK-NEXT: 1 10 0.50 * U fsubrl (%eax)
+# CHECK-NEXT: 1 3 0.50 U fsubrp %st, %st(1)
+# CHECK-NEXT: 1 3 0.50 U fsubrp %st, %st(2)
+# CHECK-NEXT: 2 5 6.00 * U fisubrs (%ecx)
+# CHECK-NEXT: 2 5 6.00 * U fisubrl (%eax)
+# CHECK-NEXT: 1 3 1.00 U ftst
+# CHECK-NEXT: 1 3 1.00 U fucom %st(1)
+# CHECK-NEXT: 1 3 1.00 U fucom %st(3)
+# CHECK-NEXT: 1 3 1.00 U fucomp %st(1)
+# CHECK-NEXT: 1 3 1.00 U fucomp %st(3)
+# CHECK-NEXT: 1 3 1.00 U fucompp
+# CHECK-NEXT: 1 3 1.00 U fucomi %st(3), %st
+# CHECK-NEXT: 1 3 1.00 U fucompi %st(3), %st
+# CHECK-NEXT: 100 100 25.00 U wait
+# CHECK-NEXT: 100 100 25.00 U fxam
+# CHECK-NEXT: 1 1 1.00 U fxch %st(1)
+# CHECK-NEXT: 1 1 1.00 U fxch %st(3)
+# CHECK-NEXT: 100 100 25.00 * * U fxrstor (%eax)
+# CHECK-NEXT: 100 100 25.00 * * U fxsave (%eax)
+# CHECK-NEXT: 100 100 25.00 U fxtract
+# CHECK-NEXT: 100 100 25.00 U fyl2x
+# CHECK-NEXT: 100 100 25.00 U fyl2xp1
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: 10.67 10.67 10.67 886.50 886.50 886.50 886.50 - 137.00 203.00 119.00 119.00 13.50 13.50 - 24.00 24.00 24.00 15.33 15.33 15.33 13.00 13.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - f2xm1
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - fabs
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - fadd %st, %st(1)
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - fadd %st(2), %st
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - fadds (%ecx)
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - faddl (%ecx)
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - faddp %st, %st(1)
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - faddp %st, %st(2)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 6.00 6.00 6.00 6.00 - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - fiadds (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 6.00 6.00 6.00 6.00 - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - fiaddl (%ecx)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - fbld (%ecx)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - fbstp (%eax)
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - fchs
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - fnclex
+# CHECK-NEXT: - - - 7.00 7.00 7.00 7.00 - - - - - - - - - - - - - - - - fcmovb %st(1), %st
+# CHECK-NEXT: - - - 7.00 7.00 7.00 7.00 - - - - - - - - - - - - - - - - fcmovbe %st(1), %st
+# CHECK-NEXT: - - - 7.00 7.00 7.00 7.00 - - - - - - - - - - - - - - - - fcmove %st(1), %st
+# CHECK-NEXT: - - - 7.00 7.00 7.00 7.00 - - - - - - - - - - - - - - - - fcmovnb %st(1), %st
+# CHECK-NEXT: - - - 7.00 7.00 7.00 7.00 - - - - - - - - - - - - - - - - fcmovnbe %st(1), %st
+# CHECK-NEXT: - - - 7.00 7.00 7.00 7.00 - - - - - - - - - - - - - - - - fcmovne %st(1), %st
+# CHECK-NEXT: - - - 7.00 7.00 7.00 7.00 - - - - - - - - - - - - - - - - fcmovnu %st(1), %st
+# CHECK-NEXT: - - - 7.00 7.00 7.00 7.00 - - - - - - - - - - - - - - - - fcmovu %st(1), %st
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - fcom %st(1)
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - fcom %st(3)
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - fcoms (%ecx)
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - fcoml (%eax)
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - fcomp %st(1)
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - fcomp %st(3)
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - fcomps (%ecx)
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - fcompl (%eax)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - fcompp
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - fcomi %st(3), %st
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - fcompi %st(3), %st
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - fcos
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - fdecstp
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - - - - - - - - - - - fdiv %st, %st(1)
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - - - - - - - - - - - fdiv %st(2), %st
+# CHECK-NEXT: - - - - - - - - - 3.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - fdivs (%ecx)
+# CHECK-NEXT: - - - - - - - - - 3.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - fdivl (%eax)
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - - - - - - - - - - - fdivp %st, %st(1)
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - - - - - - - - - - - fdivp %st, %st(2)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 15.50 15.50 15.50 15.50 - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - fidivs (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 15.50 15.50 15.50 15.50 - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - fidivl (%eax)
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - - - - - - - - - - - fdivr %st, %st(1)
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - - - - - - - - - - - fdivr %st(2), %st
+# CHECK-NEXT: - - - - - - - - - 3.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - fdivrs (%ecx)
+# CHECK-NEXT: - - - - - - - - - 3.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - fdivrl (%eax)
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - - - - - - - - - - - fdivrp %st, %st(1)
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - - - - - - - - - - - fdivrp %st, %st(2)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 15.50 15.50 15.50 15.50 - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - fidivrs (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 15.50 15.50 15.50 15.50 - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - fidivrl (%eax)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - ffree %st(0)
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - ficoms (%ecx)
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - ficoml (%eax)
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - ficomps (%ecx)
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - ficompl (%eax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - filds (%edx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - fildl (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - fildll (%eax)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - fincstp
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - fninit
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.67 0.67 0.67 - - - 1.00 1.00 fists (%edx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.67 0.67 0.67 - - - 1.00 1.00 fistl (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.67 0.67 0.67 - - - 1.00 1.00 fistps (%edx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.67 0.67 0.67 - - - 1.00 1.00 fistpl (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.67 0.67 0.67 - - - 1.00 1.00 fistpll (%eax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.67 0.67 0.67 - - - 1.00 1.00 fisttps (%edx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.67 0.67 0.67 - - - 1.00 1.00 fisttpl (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.67 0.67 0.67 - - - 1.00 1.00 fisttpll (%eax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - fld %st(0)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - flds (%edx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - fldl (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - fldt (%eax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - fldcw (%eax)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - fldenv (%eax)
+# CHECK-NEXT: - - - - - - - - - 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - fld1
+# CHECK-NEXT: - - - - - - - - - 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - fldl2e
+# CHECK-NEXT: - - - - - - - - - 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - fldl2t
+# CHECK-NEXT: - - - - - - - - - 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - fldlg2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - fldln2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - fldpi
+# CHECK-NEXT: - - - - - - - - - 1.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - fldz
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - fmul %st, %st(1)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - fmul %st(2), %st
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - fmuls (%ecx)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - fmull (%eax)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - fmulp %st, %st(1)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - fmulp %st, %st(2)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 6.00 6.00 6.00 6.00 - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - fimuls (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 6.00 6.00 6.00 6.00 - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - fimull (%eax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - fnop
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - fpatan
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - fprem
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - fprem1
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - fptan
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - frndint
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - frstor (%eax)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - fnsave (%eax)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - fscale
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - fsin
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - fsincos
+# CHECK-NEXT: - - - - - - - - - 23.00 - - - - - - - - - - - - - fsqrt
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - fst %st(0)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.67 0.67 0.67 - - - 1.00 1.00 fsts (%edx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.67 0.67 0.67 - - - 1.00 1.00 fstl (%ecx)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - fstp %st(0)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.67 0.67 0.67 - - - 1.00 1.00 fstpl (%edx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.67 0.67 0.67 - - - 1.00 1.00 fstpl (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - 0.67 0.67 0.67 - - - 1.00 1.00 fstpt (%eax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - fnstcw (%eax)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - fnstenv (%eax)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - fnstsw (%eax)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - frstor (%eax)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - wait
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - fnsave (%eax)
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - fsub %st, %st(1)
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - fsub %st(2), %st
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - fsubs (%ecx)
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - fsubl (%eax)
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - fsubp %st, %st(1)
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - fsubp %st, %st(2)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 6.00 6.00 6.00 6.00 - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - fisubs (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 6.00 6.00 6.00 6.00 - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - fisubl (%eax)
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - fsubr %st, %st(1)
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - fsubr %st(2), %st
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - fsubrs (%ecx)
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - fsubrl (%eax)
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - fsubrp %st, %st(1)
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - fsubrp %st, %st(2)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 6.00 6.00 6.00 6.00 - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - fisubrs (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 6.00 6.00 6.00 6.00 - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - fisubrl (%eax)
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - ftst
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - fucom %st(1)
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - fucom %st(3)
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - fucomp %st(1)
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - fucomp %st(3)
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - fucompp
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - fucomi %st(3), %st
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 - - - - - - - - - - - - - fucompi %st(3), %st
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - wait
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - fxam
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - fxch %st(1)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - fxch %st(3)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - fxrstor (%eax)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - fxsave (%eax)
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - fxtract
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - fyl2x
+# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - fyl2xp1
diff --git a/llvm/test/tools/llvm-mca/X86/cpus.s b/llvm/test/tools/llvm-mca/X86/cpus.s
index d422adc157613..0eea27d4e2e55 100644
--- a/llvm/test/tools/llvm-mca/X86/cpus.s
+++ b/llvm/test/tools/llvm-mca/X86/cpus.s
@@ -4,6 +4,7 @@
# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=btver2 -resource-pressure=false -instruction-info=false < %s | FileCheck --check-prefixes=ALL,BTVER2 %s
# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=znver1 -resource-pressure=false -instruction-info=false < %s | FileCheck --check-prefixes=ALL,ZNVER1 %s
# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=znver2 -resource-pressure=false -instruction-info=false < %s | FileCheck --check-prefixes=ALL,ZNVER2 %s
+# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=znver3 -resource-pressure=false -instruction-info=false < %s | FileCheck --check-prefixes=ALL,ZNVER3 %s
# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=sandybridge -resource-pressure=false -instruction-info=false < %s | FileCheck --check-prefixes=ALL,SANDYBRIDGE %s
# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=ivybridge -resource-pressure=false -instruction-info=false < %s | FileCheck --check-prefixes=ALL,IVYBRIDGE %s
# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=haswell -resource-pressure=false -instruction-info=false < %s | FileCheck --check-prefixes=ALL,HASWELL %s
@@ -84,3 +85,8 @@ add %edi, %eax
# ZNVER2-NEXT: uOps Per Cycle: 0.97
# ZNVER2-NEXT: IPC: 0.97
# ZNVER2-NEXT: Block RThroughput: 0.3
+
+# ZNVER3: Dispatch Width: 6
+# ZNVER3-NEXT: uOps Per Cycle: 0.97
+# ZNVER3-NEXT: IPC: 0.97
+# ZNVER3-NEXT: Block RThroughput: 0.3
diff --git a/llvm/test/tools/llvm-mca/X86/in-order-cpu.s b/llvm/test/tools/llvm-mca/X86/in-order-cpu.s
index be69c38abf876..fcf4422bbbb4a 100644
--- a/llvm/test/tools/llvm-mca/X86/in-order-cpu.s
+++ b/llvm/test/tools/llvm-mca/X86/in-order-cpu.s
@@ -1,3 +1,5 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=atom -o /dev/null 2>&1 | FileCheck %s
-# CHECK: warning: support for in-order CPU 'atom' is experimental.
movsbw %al, %di
+
+# CHECK: warning: support for in-order CPU 'atom' is experimental.
diff --git a/llvm/test/tools/llvm-mca/X86/read-after-ld-1.s b/llvm/test/tools/llvm-mca/X86/read-after-ld-1.s
index e7d8dc0b015b1..ae5a9e676700b 100644
--- a/llvm/test/tools/llvm-mca/X86/read-after-ld-1.s
+++ b/llvm/test/tools/llvm-mca/X86/read-after-ld-1.s
@@ -8,6 +8,7 @@
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefixes=ALL,BTVER2
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefixes=ALL,ZNVER1
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver2 -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefixes=ALL,ZNVER2
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefixes=ALL,ZNVER3
vdivps %xmm0, %xmm1, %xmm1
vaddps (%rax), %xmm1, %xmm1
@@ -42,6 +43,9 @@ vaddps (%rax), %xmm1, %xmm1
# ZNVER2-NEXT: Total Cycles: 21
# ZNVER2-NEXT: Total uOps: 2
+# ZNVER3-NEXT: Total Cycles: 17
+# ZNVER3-NEXT: Total uOps: 2
+
# BARCELONA: Dispatch Width: 4
# BARCELONA-NEXT: uOps Per Cycle: 0.15
# BARCELONA-NEXT: IPC: 0.10
@@ -87,6 +91,11 @@ vaddps (%rax), %xmm1, %xmm1
# ZNVER2-NEXT: IPC: 0.10
# ZNVER2-NEXT: Block RThroughput: 1.0
+# ZNVER3: Dispatch Width: 6
+# ZNVER3-NEXT: uOps Per Cycle: 0.12
+# ZNVER3-NEXT: IPC: 0.12
+# ZNVER3-NEXT: Block RThroughput: 3.0
+
# ALL: Timeline view:
# BARCELONA-NEXT: 0123456789
@@ -116,6 +125,9 @@ vaddps (%rax), %xmm1, %xmm1
# ZNVER2-NEXT: 0123456789
# ZNVER2-NEXT: Index 0123456789 0
+# ZNVER3-NEXT: 0123456
+# ZNVER3-NEXT: Index 0123456789
+
# BARCELONA: [0,0] DeeeeeeeeeeeeeeER . vdivps %xmm0, %xmm1, %xmm1
# BARCELONA-NEXT: [0,1] D========eeeeeeeeeER vaddps (%rax), %xmm1, %xmm1
@@ -143,6 +155,9 @@ vaddps (%rax), %xmm1, %xmm1
# ZNVER2: [0,0] DeeeeeeeeeeeeeeeER . vdivps %xmm0, %xmm1, %xmm1
# ZNVER2-NEXT: [0,1] D========eeeeeeeeeeER vaddps (%rax), %xmm1, %xmm1
+# ZNVER3: [0,0] DeeeeeeeeeeeER .. vdivps %xmm0, %xmm1, %xmm1
+# ZNVER3-NEXT: [0,1] D====eeeeeeeeeeER vaddps (%rax), %xmm1, %xmm1
+
# ALL: Average Wait times (based on the timeline view):
# ALL-NEXT: [0]: Executions
# ALL-NEXT: [1]: Average time spent waiting in a scheduler's queue
@@ -178,3 +193,6 @@ vaddps (%rax), %xmm1, %xmm1
# ZNVER2-NEXT: 1. 1 9.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1
# ZNVER2-NEXT: 1 5.0 0.5 0.0 <total>
+
+# ZNVER3-NEXT: 1. 1 5.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1
+# ZNVER3-NEXT: 1 3.0 0.5 0.0 <total>
diff --git a/llvm/test/tools/llvm-mca/X86/register-file-statistics.s b/llvm/test/tools/llvm-mca/X86/register-file-statistics.s
index 4f4d40e4df3f5..9e3f71af052f9 100644
--- a/llvm/test/tools/llvm-mca/X86/register-file-statistics.s
+++ b/llvm/test/tools/llvm-mca/X86/register-file-statistics.s
@@ -5,6 +5,7 @@
# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -all-stats=false -all-views=false -register-file-stats < %s | FileCheck --check-prefixes=ALL,BTVER2 %s
# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1 -all-stats=false -all-views=false -register-file-stats < %s | FileCheck --check-prefixes=ALL,ZNVER1 %s
# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=znver2 -iterations=1 -all-stats=false -all-views=false -register-file-stats < %s | FileCheck --check-prefixes=ALL,ZNVER2 %s
+# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=znver3 -iterations=1 -all-stats=false -all-views=false -register-file-stats < %s | FileCheck --check-prefixes=ALL,ZNVER3 %s
# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=sandybridge -iterations=1 -all-stats=false -all-views=false -register-file-stats < %s | FileCheck --check-prefixes=ALL %s
# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=ivybridge -iterations=1 -all-stats=false -all-views=false -register-file-stats < %s | FileCheck --check-prefixes=ALL %s
# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=haswell -iterations=1 -all-stats=false -all-views=false -register-file-stats < %s | FileCheck --check-prefixes=ALL %s
@@ -44,6 +45,11 @@ xor %eax, %ebx
# ZNVER2-NEXT: Total number of mappings created: 0
# ZNVER2-NEXT: Max number of mappings used: 0
+# ZNVER3: * Register File #1 -- Zn3FpPRF:
+# ZNVER3-NEXT: Number of physical registers: 160
+# ZNVER3-NEXT: Total number of mappings created: 0
+# ZNVER3-NEXT: Max number of mappings used: 0
+
# BDVER2: * Register File #2 -- PdIntegerPRF:
# BDVER2-NEXT: Number of physical registers: 96
# BDVER2-NEXT: Total number of mappings created: 2
@@ -63,3 +69,8 @@ xor %eax, %ebx
# ZNVER2-NEXT: Number of physical registers: 168
# ZNVER2-NEXT: Total number of mappings created: 2
# ZNVER2-NEXT: Max number of mappings used: 2
+
+# ZNVER3: * Register File #2 -- Zn3IntegerPRF:
+# ZNVER3-NEXT: Number of physical registers: 192
+# ZNVER3-NEXT: Total number of mappings created: 2
+# ZNVER3-NEXT: Max number of mappings used: 2
diff --git a/llvm/test/tools/llvm-mca/X86/scheduler-queue-usage.s b/llvm/test/tools/llvm-mca/X86/scheduler-queue-usage.s
index 509e5f695eda6..d3d4bf25e39ad 100644
--- a/llvm/test/tools/llvm-mca/X86/scheduler-queue-usage.s
+++ b/llvm/test/tools/llvm-mca/X86/scheduler-queue-usage.s
@@ -4,6 +4,7 @@
# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,BTVER2 %s
# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,ZNVER1 %s
# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=znver2 -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,ZNVER2 %s
+# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=znver3 -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,ZNVER3 %s
# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=sandybridge -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,SNB %s
# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=ivybridge -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,IVB %s
# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=haswell -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,HSW %s
@@ -95,6 +96,12 @@ xor %eax, %ebx
# ZNVER2-NEXT: [3] Maximum number of used buffer entries.
# ZNVER2-NEXT: [4] Total number of buffer entries.
+# ZNVER3: Scheduler's queue usage:
+# ZNVER3-NEXT: [1] Resource name.
+# ZNVER3-NEXT: [2] Average number of used buffer entries.
+# ZNVER3-NEXT: [3] Maximum number of used buffer entries.
+# ZNVER3-NEXT: [4] Total number of buffer entries.
+
# BARCELONA: [1] [2] [3] [4]
# BARCELONA-NEXT: SBPortAny 0 1 54
@@ -139,3 +146,9 @@ xor %eax, %ebx
# ZNVER2-NEXT: Zn2AGU 0 0 28
# ZNVER2-NEXT: Zn2ALU 0 1 64
# ZNVER2-NEXT: Zn2FPU 0 0 36
+
+# ZNVER3: [1] [2] [3] [4]
+# ZNVER3-NEXT: Zn3FP 0 0 64
+# ZNVER3-NEXT: Zn3Int 0 1 96
+# ZNVER3-NEXT: Zn3Load 0 0 72
+# ZNVER3-NEXT: Zn3Store 0 0 64
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