[PATCH] D101163: [AArch64] Prevent spilling between ldxr/stxr pairs

[Eli Friedman via Phabricator via llvm-commits]

efriedma accepted this revision.
efriedma added a comment.
This revision is now accepted and ready to land.

LGTM with one minor comment.



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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:16691
+  // At -O0, fast-regalloc cannot cope with the live vregs necessary to
+  // implement cmpxchg without spilling. If the address being exchanged is also
+  // on the stack and close enough to the spill slot, this can lead to a
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"implement cmpxchg" doesn't seem right; should be "implement atomicrmw"?   (Also "address being exchanged".)


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Comment at: llvm/test/Transforms/AtomicExpand/AArch64/expand-atomicrmw-xchg-fp.ll:3
+; RUN: opt -O1 -S -mtriple=aarch64-- -atomic-expand %s | FileCheck %s
+; RUN: opt -O1 -S -mtriple=aarch64-- -mattr=+outline-atomics -atomic-expand %s | FileCheck %s --check-prefix=OUTLINE-ATOMICS
 
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LemonBoy wrote:
> efriedma wrote:
> > I don't think this change is necessary?
> At O0 there's no `llvm.aarch64.ldaxr.p0f16` nor `stxr` being emitted after this patch, I've left the test unchanged by bumping up the opt level.
Oh, I see, this is opt, not llc.  I guess it's fine.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101163/new/

https://reviews.llvm.org/D101163