[PATCH] D101636: [AArch64] Sets the preferred function alignment for Cortex-A53/A55

[Stelios Ioannou via Phabricator via llvm-commits]

stelios-arm updated this revision to Diff 341954.
stelios-arm added a comment.

Modified the Cortex-A53 test and added one for Cortex-A55.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101636/new/

https://reviews.llvm.org/D101636

Files:
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/test/CodeGen/AArch64/preferred-function-alignment.ll


Index: llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
===================================================================
--- llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
+++ llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
@@ -1,6 +1,7 @@
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=generic < %s | FileCheck --check-prefixes=ALIGN2,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a35 < %s | FileCheck --check-prefixes=ALIGN2,CHECK %s
-; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a53 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a53 < %s | FileCheck --check-prefixes=ALIGN4,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a55 < %s | FileCheck --check-prefixes=ALIGN4,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a57 < %s | FileCheck --check-prefixes=ALIGN4,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a65 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a65ae < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
Index: llvm/lib/Target/AArch64/AArch64Subtarget.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+++ llvm/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -89,9 +89,8 @@
   case CortexA35:
     break;
   case CortexA53:
-    PrefFunctionLogAlignment = 3;
-    break;
   case CortexA55:
+    PrefFunctionLogAlignment = 4;
     break;
   case CortexA57:
     MaxInterleaveFactor = 4;


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