[llvm] 7a86645 - [VE] VP intrinsics are legal

[Simon Moll via llvm-commits]

Author: Simon Moll
Date: 2021-04-30T15:47:55+02:00
New Revision: 7a8664561116cd3c1ce2e66826c479649ae741b9

URL: https://github.com/llvm/llvm-project/commit/7a8664561116cd3c1ce2e66826c479649ae741b9
DIFF: https://github.com/llvm/llvm-project/commit/7a8664561116cd3c1ce2e66826c479649ae741b9.diff

LOG: [VE] VP intrinsics are legal

Added: 
    

Modified: 
    llvm/lib/Target/VE/VETargetTransformInfo.h

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/VE/VETargetTransformInfo.h b/llvm/lib/Target/VE/VETargetTransformInfo.h
index 6730c43258d22..6e6f4d2490754 100644
--- a/llvm/lib/Target/VE/VETargetTransformInfo.h
+++ b/llvm/lib/Target/VE/VETargetTransformInfo.h
@@ -64,6 +64,14 @@ class VETTIImpl : public BasicTTIImplBase<VETTIImpl> {
     llvm_unreachable("Unsupported register kind");
   }
 
+  /// \returns How the target needs this vector-predicated operation to be
+  /// transformed.
+  TargetTransformInfo::VPLegalization
+  getVPLegalizationStrategy(const VPIntrinsic &PI) const {
+    using VPLegalization = TargetTransformInfo::VPLegalization;
+    return VPLegalization(VPLegalization::Legal, VPLegalization::Legal);
+  }
+
   unsigned getMinVectorRegisterBitWidth() const {
     // TODO report vregs once vector isel is stable.
     return 0;