[PATCH] D101605: [PowerPC] Remove extra swap for extract+vperm on LE

[Qiu Chaofan via Phabricator via llvm-commits]

qiucf created this revision.
qiucf added reviewers: nemanjai, jsji, PowerPC.
Herald added subscribers: shchenz, kbarton, hiraditya.
qiucf requested review of this revision.
Herald added a project: LLVM.
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This is a simple fix on LE. On BE, vector shuffles are categorized into different ops. We may need more work to eliminate these in tablegen/pre-isel.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D101605

Files:
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/vec_extract_p9.ll


Index: llvm/test/CodeGen/PowerPC/vec_extract_p9.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/vec_extract_p9.ll
+++ llvm/test/CodeGen/PowerPC/vec_extract_p9.ll
@@ -182,10 +182,9 @@
 ; CHECK-LE-NEXT:    addi 3, 3, .LCPI9_0 at toc@l
 ; CHECK-LE-NEXT:    lxvx 36, 0, 3
 ; CHECK-LE-NEXT:    addis 3, 2, .LCPI9_1 at toc@ha
-; CHECK-LE-NEXT:    lfs 1, .LCPI9_1 at toc@l(3)
-; CHECK-LE-NEXT:    vperm 2, 2, 3, 4
-; CHECK-LE-NEXT:    xxswapd 0, 34
-; CHECK-LE-NEXT:    xsadddp 1, 0, 1
+; CHECK-LE-NEXT:    lfs 0, .LCPI9_1 at toc@l(3)
+; CHECK-LE-NEXT:    vperm 2, 3, 2, 4
+; CHECK-LE-NEXT:    xsadddp 1, 34, 0
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test10:
Index: llvm/lib/Target/PowerPC/PPCInstrVSX.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -2938,6 +2938,9 @@
                                    (SUBREG_TO_REG (i64 1), $A, sub_64), 0),
                          (SUBREG_TO_REG (i64 1), $A, sub_64)>;
 
+def : Pat<(f64 (extractelt (v2f64 (bitconvert (v16i8
+                 (PPCvperm v16i8:$A, v16i8:$B, v16i8:$C)))), 0)),
+          (f64 (EXTRACT_SUBREG (VPERM $B, $A, $C), sub_64))>;
 def : Pat<(f64 (extractelt v2f64:$S, 0)),
           (f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>;
 def : Pat<(f64 (extractelt v2f64:$S, 1)),
@@ -2951,6 +2954,7 @@
 def : Pat<(PPCst_vec_be v2i64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>;
 def : Pat<(v4i32 (PPCld_vec_be xoaddr:$src)), (LXVW4X xoaddr:$src)>;
 def : Pat<(PPCst_vec_be v4i32:$rS, xoaddr:$dst), (STXVW4X $rS, xoaddr:$dst)>;
+
 def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),
           (f64 (XSCVSXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>;
 def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),


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