[llvm] 1cf3d68 - VirtRegMap: Add pass option to not clear virt regs

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2021-04-29T21:08:47-04:00
New Revision: 1cf3d68f9731199b3f753c5a87826c40a4d2168b

URL: https://github.com/llvm/llvm-project/commit/1cf3d68f9731199b3f753c5a87826c40a4d2168b
DIFF: https://github.com/llvm/llvm-project/commit/1cf3d68f9731199b3f753c5a87826c40a4d2168b.diff

LOG: VirtRegMap: Add pass option to not clear virt regs

In a future change it will be possible to run register
allocation with a specific set of register classes,
so some of the remaining virtual registers will still
be meaningful.

Added: 
    

Modified: 
    llvm/include/llvm/CodeGen/Passes.h
    llvm/lib/CodeGen/VirtRegMap.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/include/llvm/CodeGen/Passes.h b/llvm/include/llvm/CodeGen/Passes.h
index c01f5290d14f2..6b7a73dd28ab4 100644
--- a/llvm/include/llvm/CodeGen/Passes.h
+++ b/llvm/include/llvm/CodeGen/Passes.h
@@ -150,6 +150,7 @@ namespace llvm {
   /// VirtRegRewriter pass. Rewrite virtual registers to physical registers as
   /// assigned in VirtRegMap.
   extern char &VirtRegRewriterID;
+  FunctionPass *createVirtRegRewriter(bool ClearVirtRegs = true);
 
   /// UnreachableMachineBlockElimination - This pass removes unreachable
   /// machine basic blocks.

diff  --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp
index 0e6eadbca215f..18822337e656d 100644
--- a/llvm/lib/CodeGen/VirtRegMap.cpp
+++ b/llvm/lib/CodeGen/VirtRegMap.cpp
@@ -181,6 +181,7 @@ class VirtRegRewriter : public MachineFunctionPass {
   SlotIndexes *Indexes;
   LiveIntervals *LIS;
   VirtRegMap *VRM;
+  bool ClearVirtRegs;
 
   void rewrite();
   void addMBBLiveIns();
@@ -192,16 +193,21 @@ class VirtRegRewriter : public MachineFunctionPass {
 
 public:
   static char ID;
-
-  VirtRegRewriter() : MachineFunctionPass(ID) {}
+  VirtRegRewriter(bool ClearVirtRegs_ = true) :
+    MachineFunctionPass(ID),
+    ClearVirtRegs(ClearVirtRegs_) {}
 
   void getAnalysisUsage(AnalysisUsage &AU) const override;
 
   bool runOnMachineFunction(MachineFunction&) override;
 
   MachineFunctionProperties getSetProperties() const override {
-    return MachineFunctionProperties().set(
+    if (ClearVirtRegs) {
+      return MachineFunctionProperties().set(
         MachineFunctionProperties::Property::NoVRegs);
+    }
+
+    return MachineFunctionProperties();
   }
 };
 
@@ -257,10 +263,13 @@ bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
   // Write out new DBG_VALUE instructions.
   getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
 
-  // All machine operands and other references to virtual registers have been
-  // replaced. Remove the virtual registers and release all the transient data.
-  VRM->clearAllVirt();
-  MRI->clearVirtRegs();
+  if (ClearVirtRegs) {
+    // All machine operands and other references to virtual registers have been
+    // replaced. Remove the virtual registers and release all the transient data.
+    VRM->clearAllVirt();
+    MRI->clearVirtRegs();
+  }
+
   return true;
 }
 
@@ -591,3 +600,7 @@ void VirtRegRewriter::rewrite() {
     }
   }
 }
+
+FunctionPass *llvm::createVirtRegRewriter(bool ClearVirtRegs) {
+  return new VirtRegRewriter(ClearVirtRegs);
+}