[llvm] ae3377c - [AIX][TLS] Add ASM portion changes to support TLSGD relocations to XCOFF objects

Victor Huang via llvm-commits llvm-commits at lists.llvm.org
Thu Apr 29 11:20:35 PDT 2021


Author: Victor Huang
Date: 2021-04-29T13:18:59-05:00
New Revision: ae3377c55343e83e7768f612398dda942b83a06e

URL: https://github.com/llvm/llvm-project/commit/ae3377c55343e83e7768f612398dda942b83a06e
DIFF: https://github.com/llvm/llvm-project/commit/ae3377c55343e83e7768f612398dda942b83a06e.diff

LOG: [AIX][TLS] Add ASM portion changes to support TLSGD relocations to XCOFF objects

- Add new variantKinds for the symbol's variable offset and region handle
- Print the proper relocation specifier @gd in the asm streamer when emitting
  the TC Entry for the variable offset for the symbol
- Fix the switch section failure between the TC Entry of variable offset and
  region handle
- Put .__tls_get_addr symbol in the ProgramCodeSects with XTY_ER property

Reviewed by: sfertile

Differential Revision: https://reviews.llvm.org/D100956

Added: 
    

Modified: 
    llvm/include/llvm/MC/MCExpr.h
    llvm/lib/MC/MCExpr.cpp
    llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
    llvm/lib/Target/PowerPC/PPC.h
    llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
    llvm/lib/Target/PowerPC/PPCISelLowering.cpp
    llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
    llvm/test/CodeGen/PowerPC/aix-tls-gd-double.ll
    llvm/test/CodeGen/PowerPC/aix-tls-gd-int.ll
    llvm/test/CodeGen/PowerPC/aix-tls-gd-longlong.ll

Removed: 
    


################################################################################
diff  --git a/llvm/include/llvm/MC/MCExpr.h b/llvm/include/llvm/MC/MCExpr.h
index eb631094ebc4d..38cca2413e1eb 100644
--- a/llvm/include/llvm/MC/MCExpr.h
+++ b/llvm/include/llvm/MC/MCExpr.h
@@ -296,6 +296,8 @@ class MCSymbolRefExpr : public MCExpr {
     VK_PPC_GOT_TLSGD_HI,    // symbol at got@tlsgd at h
     VK_PPC_GOT_TLSGD_HA,    // symbol at got@tlsgd at ha
     VK_PPC_TLSGD,           // symbol at tlsgd
+    VK_PPC_AIX_TLSGD,       // symbol at gd
+    VK_PPC_AIX_TLSGDM,      // symbol at m
     VK_PPC_GOT_TLSLD,       // symbol at got@tlsld
     VK_PPC_GOT_TLSLD_LO,    // symbol at got@tlsld at l
     VK_PPC_GOT_TLSLD_HI,    // symbol at got@tlsld at h

diff  --git a/llvm/lib/MC/MCExpr.cpp b/llvm/lib/MC/MCExpr.cpp
index a18bb2d4a30bc..55b20a37f6520 100644
--- a/llvm/lib/MC/MCExpr.cpp
+++ b/llvm/lib/MC/MCExpr.cpp
@@ -322,6 +322,10 @@ StringRef MCSymbolRefExpr::getVariantKindName(VariantKind Kind) {
   case VK_PPC_GOT_TLSGD_HI: return "got at tlsgd@h";
   case VK_PPC_GOT_TLSGD_HA: return "got at tlsgd@ha";
   case VK_PPC_TLSGD: return "tlsgd";
+  case VK_PPC_AIX_TLSGD:
+    return "gd";
+  case VK_PPC_AIX_TLSGDM:
+    return "m";
   case VK_PPC_GOT_TLSLD: return "got at tlsld";
   case VK_PPC_GOT_TLSLD_LO: return "got at tlsld@l";
   case VK_PPC_GOT_TLSLD_HI: return "got at tlsld@h";

diff  --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
index 15810b59faf47..23d80e71a4deb 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
@@ -145,11 +145,14 @@ class PPCTargetAsmStreamer : public PPCTargetStreamer {
       MCSymbolXCOFF *TCSym =
           cast<MCSectionXCOFF>(Streamer.getCurrentSectionOnly())
               ->getQualNameSymbol();
-      // If the variant kind is TLSGD the entry represents the region handle for
-      // the symbol, we prefix the name with a dot and we add the @m
-      // relocation specifier.
-      if (Kind == MCSymbolRefExpr::VariantKind::VK_PPC_TLSGD)
-        OS << "\t.tc ." << TCSym->getName() << "," << XSym->getName() << "@m\n";
+      // If the variant kind is VK_PPC_AIX_TLSGDM the entry represents the
+      // region handle for the symbol, we add the relocation specifier @m.
+      // If the variant kind is VK_PPC_AIX_TLSGD the entry represents the
+      // variable offset for the symbol, we add the relocation specifier @gd.
+      if (Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGD ||
+          Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGDM)
+        OS << "\t.tc " << TCSym->getName() << "," << XSym->getName() << "@"
+           << MCSymbolRefExpr::getVariantKindName(Kind) << '\n';
       else
         OS << "\t.tc " << TCSym->getName() << "," << XSym->getName() << '\n';
 

diff  --git a/llvm/lib/Target/PowerPC/PPC.h b/llvm/lib/Target/PowerPC/PPC.h
index 264582b244a7f..8339046e8c267 100644
--- a/llvm/lib/Target/PowerPC/PPC.h
+++ b/llvm/lib/Target/PowerPC/PPC.h
@@ -116,7 +116,8 @@ FunctionPass *createPPCCTRLoops();
     MO_PCREL_OPT_FLAG = 16,
 
     /// MO_TLSGD_FLAG - If this bit is set the symbol reference is relative to
-    /// TLS General Dynamic model.
+    /// TLS General Dynamic model for Linux and the variable offset of TLS
+    /// General Dynamic model for AIX.
     MO_TLSGD_FLAG = 32,
 
     /// MO_TPREL_FLAG - If this bit is set the symbol reference is relative to
@@ -127,6 +128,10 @@ FunctionPass *createPPCCTRLoops();
     /// TLS Local Dynamic model.
     MO_TLSLD_FLAG = 128,
 
+    /// MO_TLSGDM_FLAG - If this bit is set the symbol reference is relative
+    /// to the region handle of TLS General Dynamic model for AIX.
+    MO_TLSGDM_FLAG = 256,
+
     /// MO_GOT_TLSGD_PCREL_FLAG - A combintaion of flags, if these bits are set
     /// they should produce the relocation @got at tlsgd@pcrel.
     /// Fix up is VK_PPC_GOT_TLSGD_PCREL

diff  --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
index aa0707abf6169..289a0f3704b4e 100644
--- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -522,12 +522,20 @@ void PPCAsmPrinter::LowerPATCHPOINT(StackMaps &SM, const MachineInstr &MI) {
     EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::NOP));
 }
 
+/// This helper function creates the TlsGetAddr MCSymbol for AIX. We will
+/// create the csect and use the qual-name symbol instead of creating just the
+/// external symbol.
+static MCSymbol *createMCSymbolForTlsGetAddr(MCContext &Ctx) {
+  return Ctx
+      .getXCOFFSection(".__tls_get_addr", SectionKind::getText(),
+                       XCOFF::CsectProperties(XCOFF::XMC_PR, XCOFF::XTY_ER))
+      ->getQualNameSymbol();
+}
+
 /// EmitTlsCall -- Given a GETtls[ld]ADDR[32] instruction, print a
 /// call to __tls_get_addr to the current output stream.
 void PPCAsmPrinter::EmitTlsCall(const MachineInstr *MI,
                                 MCSymbolRefExpr::VariantKind VK) {
-  StringRef Name = Subtarget->isAIXABI() ? ".__tls_get_addr" : "__tls_get_addr";
-  MCSymbol *TlsGetAddr = OutContext.getOrCreateSymbol(Name);
   MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
   unsigned Opcode = PPC::BL8_NOP_TLS;
 
@@ -558,13 +566,15 @@ void PPCAsmPrinter::EmitTlsCall(const MachineInstr *MI,
     assert(MI->getOperand(2).isReg() &&
            MI->getOperand(2).getReg() == VarOffsetReg &&
            "GETtls[ld]ADDR[32] must read GPR4");
-    MCSymbol *TlsGetAddrA = OutContext.getOrCreateSymbol(Name);
+    MCSymbol *TlsGetAddr = createMCSymbolForTlsGetAddr(OutContext);
     const MCExpr *TlsRef = MCSymbolRefExpr::create(
-        TlsGetAddrA, MCSymbolRefExpr::VK_None, OutContext);
+        TlsGetAddr, MCSymbolRefExpr::VK_None, OutContext);
     EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::BLA).addExpr(TlsRef));
     return;
   }
 
+  MCSymbol *TlsGetAddr = OutContext.getOrCreateSymbol("__tls_get_addr");
+
   if (Subtarget->is32BitELFABI() && isPositionIndependent())
     Kind = MCSymbolRefExpr::VK_PLT;
 
@@ -673,10 +683,12 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr *MI) {
   };
   auto GetVKForMO = [&](const MachineOperand &MO) {
     // For GD TLS access on AIX, we have two TOC entries for the symbol (one for
-    // the offset and the other for the region handle). They are 
diff erentiated
-    // by the presence of the PPCII::MO_TLSGD_FLAG.
-    if (IsAIX && (MO.getTargetFlags() & PPCII::MO_TLSGD_FLAG))
-      return MCSymbolRefExpr::VariantKind::VK_PPC_TLSGD;
+    // the variable offset and the other for the region handle). They are
+    // 
diff erentiated by MO_TLSGD_FLAG and MO_TLSGDM_FLAG.
+    if (MO.getTargetFlags() & PPCII::MO_TLSGDM_FLAG)
+      return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGDM;
+    if (MO.getTargetFlags() & PPCII::MO_TLSGD_FLAG)
+      return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGD;
     return MCSymbolRefExpr::VariantKind::VK_None;
   };
 
@@ -2232,9 +2244,22 @@ void PPCAIXAsmPrinter::emitEndOfAsmFile(Module &M) {
       static_cast<PPCTargetStreamer *>(OutStreamer->getTargetStreamer());
 
   for (auto &I : TOC) {
-    // Setup the csect for the current TC entry.
-    MCSectionXCOFF *TCEntry = cast<MCSectionXCOFF>(
-        getObjFileLowering().getSectionForTOCEntry(I.first.first, TM));
+    MCSectionXCOFF *TCEntry;
+    // Setup the csect for the current TC entry. If the variant kind is
+    // VK_PPC_AIX_TLSGDM the entry represents the region handle, we create a
+    // new symbol to prefix the name with a dot.
+    if (I.first.second == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGDM) {
+      SmallString<128> Name;
+      StringRef Prefix = ".";
+      Name += Prefix;
+      Name += I.first.first->getName();
+      MCSymbol *S = OutContext.getOrCreateSymbol(Name);
+      TCEntry = cast<MCSectionXCOFF>(
+          getObjFileLowering().getSectionForTOCEntry(S, TM));
+    } else {
+      TCEntry = cast<MCSectionXCOFF>(
+          getObjFileLowering().getSectionForTOCEntry(I.first.first, TM));
+    }
     OutStreamer->SwitchSection(TCEntry);
 
     OutStreamer->emitLabel(I.second);
@@ -2317,7 +2342,7 @@ void PPCAIXAsmPrinter::emitInstruction(const MachineInstr *MI) {
   case PPC::GETtlsADDR32AIX: {
     // The reference to .__tls_get_addr is unknown to the assembler
     // so we need to emit an external symbol reference.
-    MCSymbol *TlsGetAddr = OutContext.getOrCreateSymbol(".__tls_get_addr");
+    MCSymbol *TlsGetAddr = createMCSymbolForTlsGetAddr(OutContext);
     ExtSymSDNodeSymbols.insert(TlsGetAddr);
     break;
   }

diff  --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index e0001bc07ebe2..1547fc30ba1f7 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -3146,11 +3146,12 @@ SDValue PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
   // all the GlobalTLSAddress nodes are lowered with this model.
   // We need to generate two TOC entries, one for the variable offset, one for
   // the region handle. The global address for the TOC entry of the region
-  // handle is created with the MO_TLSGD_FLAG flag so we can easily identify
-  // this entry and add the right relocation.
-  SDValue VariableOffsetTGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
-  SDValue RegionHandleTGA =
+  // handle is created with the MO_TLSGDM_FLAG flag and the global address
+  // for the TOC entry of the variable offset is created with MO_TLSGD_FLAG.
+  SDValue VariableOffsetTGA =
       DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TLSGD_FLAG);
+  SDValue RegionHandleTGA =
+      DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TLSGDM_FLAG);
   SDValue VariableOffset = getTOCEntry(DAG, dl, VariableOffsetTGA);
   SDValue RegionHandle = getTOCEntry(DAG, dl, RegionHandleTGA);
   return DAG.getNode(PPCISD::TLSGD_AIX, dl, PtrVT, VariableOffset,

diff  --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 155b22f5630bc..d9ed506c8e608 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -2893,6 +2893,7 @@ PPCInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
       {MO_TLSGD_FLAG, "ppc-tlsgd"},
       {MO_TLSLD_FLAG, "ppc-tlsld"},
       {MO_TPREL_FLAG, "ppc-tprel"},
+      {MO_TLSGDM_FLAG, "ppc-tlsgdm"},
       {MO_GOT_TLSGD_PCREL_FLAG, "ppc-got-tlsgd-pcrel"},
       {MO_GOT_TLSLD_PCREL_FLAG, "ppc-got-tlsld-pcrel"},
       {MO_GOT_TPREL_PCREL_FLAG, "ppc-got-tprel-pcrel"}};

diff  --git a/llvm/test/CodeGen/PowerPC/aix-tls-gd-double.ll b/llvm/test/CodeGen/PowerPC/aix-tls-gd-double.ll
index b38c2e34e04ac..22a0505dad34c 100644
--- a/llvm/test/CodeGen/PowerPC/aix-tls-gd-double.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-tls-gd-double.ll
@@ -26,7 +26,7 @@ define void @storesTGUninit(double %Val) #0 {
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    lwz 3, L..C0(2)
 ; SMALL32-NEXT:    lwz 4, L..C1(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    stfd 1, 0(3)
 ; SMALL32-NEXT:    addi 1, 1, 32
 ; SMALL32-NEXT:    lwz 0, 8(1)
@@ -42,7 +42,7 @@ define void @storesTGUninit(double %Val) #0 {
 ; LARGE32-NEXT:    addis 4, L..C1 at u(2)
 ; LARGE32-NEXT:    lwz 3, L..C0 at l(3)
 ; LARGE32-NEXT:    lwz 4, L..C1 at l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    stfd 1, 0(3)
 ; LARGE32-NEXT:    addi 1, 1, 32
 ; LARGE32-NEXT:    lwz 0, 8(1)
@@ -56,7 +56,7 @@ define void @storesTGUninit(double %Val) #0 {
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    ld 3, L..C0(2)
 ; SMALL64-NEXT:    ld 4, L..C1(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    stfd 1, 0(3)
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
@@ -72,7 +72,7 @@ define void @storesTGUninit(double %Val) #0 {
 ; LARGE64-NEXT:    addis 4, L..C1 at u(2)
 ; LARGE64-NEXT:    ld 3, L..C0 at l(3)
 ; LARGE64-NEXT:    ld 4, L..C1 at l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    stfd 1, 0(3)
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
@@ -92,7 +92,7 @@ define void @storesTGInit(double %Val) #0 {
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    lwz 3, L..C2(2)
 ; SMALL32-NEXT:    lwz 4, L..C3(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    stfd 1, 0(3)
 ; SMALL32-NEXT:    addi 1, 1, 32
 ; SMALL32-NEXT:    lwz 0, 8(1)
@@ -108,7 +108,7 @@ define void @storesTGInit(double %Val) #0 {
 ; LARGE32-NEXT:    addis 4, L..C3 at u(2)
 ; LARGE32-NEXT:    lwz 3, L..C2 at l(3)
 ; LARGE32-NEXT:    lwz 4, L..C3 at l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    stfd 1, 0(3)
 ; LARGE32-NEXT:    addi 1, 1, 32
 ; LARGE32-NEXT:    lwz 0, 8(1)
@@ -122,7 +122,7 @@ define void @storesTGInit(double %Val) #0 {
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    ld 3, L..C2(2)
 ; SMALL64-NEXT:    ld 4, L..C3(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    stfd 1, 0(3)
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
@@ -138,7 +138,7 @@ define void @storesTGInit(double %Val) #0 {
 ; LARGE64-NEXT:    addis 4, L..C3 at u(2)
 ; LARGE64-NEXT:    ld 3, L..C2 at l(3)
 ; LARGE64-NEXT:    ld 4, L..C3 at l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    stfd 1, 0(3)
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
@@ -158,7 +158,7 @@ define void @storesTIInit(double %Val) #0 {
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    lwz 3, L..C4(2)
 ; SMALL32-NEXT:    lwz 4, L..C5(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    stfd 1, 0(3)
 ; SMALL32-NEXT:    addi 1, 1, 32
 ; SMALL32-NEXT:    lwz 0, 8(1)
@@ -174,7 +174,7 @@ define void @storesTIInit(double %Val) #0 {
 ; LARGE32-NEXT:    addis 4, L..C5 at u(2)
 ; LARGE32-NEXT:    lwz 3, L..C4 at l(3)
 ; LARGE32-NEXT:    lwz 4, L..C5 at l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    stfd 1, 0(3)
 ; LARGE32-NEXT:    addi 1, 1, 32
 ; LARGE32-NEXT:    lwz 0, 8(1)
@@ -188,7 +188,7 @@ define void @storesTIInit(double %Val) #0 {
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    ld 3, L..C4(2)
 ; SMALL64-NEXT:    ld 4, L..C5(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    stfd 1, 0(3)
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
@@ -204,7 +204,7 @@ define void @storesTIInit(double %Val) #0 {
 ; LARGE64-NEXT:    addis 4, L..C5 at u(2)
 ; LARGE64-NEXT:    ld 3, L..C4 at l(3)
 ; LARGE64-NEXT:    ld 4, L..C5 at l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    stfd 1, 0(3)
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
@@ -224,7 +224,7 @@ define void @storesTWInit(double %Val) #0 {
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    lwz 3, L..C6(2)
 ; SMALL32-NEXT:    lwz 4, L..C7(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    stfd 1, 0(3)
 ; SMALL32-NEXT:    addi 1, 1, 32
 ; SMALL32-NEXT:    lwz 0, 8(1)
@@ -240,7 +240,7 @@ define void @storesTWInit(double %Val) #0 {
 ; LARGE32-NEXT:    addis 4, L..C7 at u(2)
 ; LARGE32-NEXT:    lwz 3, L..C6 at l(3)
 ; LARGE32-NEXT:    lwz 4, L..C7 at l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    stfd 1, 0(3)
 ; LARGE32-NEXT:    addi 1, 1, 32
 ; LARGE32-NEXT:    lwz 0, 8(1)
@@ -254,7 +254,7 @@ define void @storesTWInit(double %Val) #0 {
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    ld 3, L..C6(2)
 ; SMALL64-NEXT:    ld 4, L..C7(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    stfd 1, 0(3)
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
@@ -270,7 +270,7 @@ define void @storesTWInit(double %Val) #0 {
 ; LARGE64-NEXT:    addis 4, L..C7 at u(2)
 ; LARGE64-NEXT:    ld 3, L..C6 at l(3)
 ; LARGE64-NEXT:    ld 4, L..C7 at l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    stfd 1, 0(3)
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
@@ -290,7 +290,7 @@ define double @loadsTGUninit() #1 {
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    lwz 3, L..C0(2)
 ; SMALL32-NEXT:    lwz 4, L..C1(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    lwz 4, L..C8(2)
 ; SMALL32-NEXT:    lfd 0, 0(3)
 ; SMALL32-NEXT:    lfd 1, 0(4)
@@ -309,7 +309,7 @@ define double @loadsTGUninit() #1 {
 ; LARGE32-NEXT:    addis 4, L..C1 at u(2)
 ; LARGE32-NEXT:    lwz 3, L..C0 at l(3)
 ; LARGE32-NEXT:    lwz 4, L..C1 at l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    lfd 0, 0(3)
 ; LARGE32-NEXT:    addis 3, L..C8 at u(2)
 ; LARGE32-NEXT:    lwz 3, L..C8 at l(3)
@@ -327,7 +327,7 @@ define double @loadsTGUninit() #1 {
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    ld 3, L..C0(2)
 ; SMALL64-NEXT:    ld 4, L..C1(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    ld 4, L..C8(2)
 ; SMALL64-NEXT:    lfd 0, 0(3)
 ; SMALL64-NEXT:    lfd 1, 0(4)
@@ -346,7 +346,7 @@ define double @loadsTGUninit() #1 {
 ; LARGE64-NEXT:    addis 4, L..C1 at u(2)
 ; LARGE64-NEXT:    ld 3, L..C0 at l(3)
 ; LARGE64-NEXT:    ld 4, L..C1 at l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    addis 4, L..C8 at u(2)
 ; LARGE64-NEXT:    lfd 0, 0(3)
 ; LARGE64-NEXT:    ld 3, L..C8 at l(4)
@@ -372,7 +372,7 @@ define double @loadsTGInit() #1 {
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    lwz 3, L..C2(2)
 ; SMALL32-NEXT:    lwz 4, L..C3(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    lwz 4, L..C8(2)
 ; SMALL32-NEXT:    lfd 0, 0(3)
 ; SMALL32-NEXT:    lfd 1, 0(4)
@@ -391,7 +391,7 @@ define double @loadsTGInit() #1 {
 ; LARGE32-NEXT:    addis 4, L..C3 at u(2)
 ; LARGE32-NEXT:    lwz 3, L..C2 at l(3)
 ; LARGE32-NEXT:    lwz 4, L..C3 at l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    lfd 0, 0(3)
 ; LARGE32-NEXT:    addis 3, L..C8 at u(2)
 ; LARGE32-NEXT:    lwz 3, L..C8 at l(3)
@@ -409,7 +409,7 @@ define double @loadsTGInit() #1 {
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    ld 3, L..C2(2)
 ; SMALL64-NEXT:    ld 4, L..C3(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    ld 4, L..C8(2)
 ; SMALL64-NEXT:    lfd 0, 0(3)
 ; SMALL64-NEXT:    lfd 1, 0(4)
@@ -428,7 +428,7 @@ define double @loadsTGInit() #1 {
 ; LARGE64-NEXT:    addis 4, L..C3 at u(2)
 ; LARGE64-NEXT:    ld 3, L..C2 at l(3)
 ; LARGE64-NEXT:    ld 4, L..C3 at l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    addis 4, L..C8 at u(2)
 ; LARGE64-NEXT:    lfd 0, 0(3)
 ; LARGE64-NEXT:    ld 3, L..C8 at l(4)
@@ -454,7 +454,7 @@ define double @loadsTIInit() #1 {
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    lwz 3, L..C4(2)
 ; SMALL32-NEXT:    lwz 4, L..C5(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    lwz 4, L..C8(2)
 ; SMALL32-NEXT:    lfd 0, 0(3)
 ; SMALL32-NEXT:    lfd 1, 0(4)
@@ -473,7 +473,7 @@ define double @loadsTIInit() #1 {
 ; LARGE32-NEXT:    addis 4, L..C5 at u(2)
 ; LARGE32-NEXT:    lwz 3, L..C4 at l(3)
 ; LARGE32-NEXT:    lwz 4, L..C5 at l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    lfd 0, 0(3)
 ; LARGE32-NEXT:    addis 3, L..C8 at u(2)
 ; LARGE32-NEXT:    lwz 3, L..C8 at l(3)
@@ -491,7 +491,7 @@ define double @loadsTIInit() #1 {
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    ld 3, L..C4(2)
 ; SMALL64-NEXT:    ld 4, L..C5(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    ld 4, L..C8(2)
 ; SMALL64-NEXT:    lfd 0, 0(3)
 ; SMALL64-NEXT:    lfd 1, 0(4)
@@ -510,7 +510,7 @@ define double @loadsTIInit() #1 {
 ; LARGE64-NEXT:    addis 4, L..C5 at u(2)
 ; LARGE64-NEXT:    ld 3, L..C4 at l(3)
 ; LARGE64-NEXT:    ld 4, L..C5 at l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    addis 4, L..C8 at u(2)
 ; LARGE64-NEXT:    lfd 0, 0(3)
 ; LARGE64-NEXT:    ld 3, L..C8 at l(4)
@@ -536,7 +536,7 @@ define double @loadsTWInit() #1 {
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    lwz 3, L..C6(2)
 ; SMALL32-NEXT:    lwz 4, L..C7(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    lwz 4, L..C8(2)
 ; SMALL32-NEXT:    lfd 0, 0(3)
 ; SMALL32-NEXT:    lfd 1, 0(4)
@@ -555,7 +555,7 @@ define double @loadsTWInit() #1 {
 ; LARGE32-NEXT:    addis 4, L..C7 at u(2)
 ; LARGE32-NEXT:    lwz 3, L..C6 at l(3)
 ; LARGE32-NEXT:    lwz 4, L..C7 at l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    lfd 0, 0(3)
 ; LARGE32-NEXT:    addis 3, L..C8 at u(2)
 ; LARGE32-NEXT:    lwz 3, L..C8 at l(3)
@@ -573,7 +573,7 @@ define double @loadsTWInit() #1 {
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    ld 3, L..C6(2)
 ; SMALL64-NEXT:    ld 4, L..C7(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    ld 4, L..C8(2)
 ; SMALL64-NEXT:    lfd 0, 0(3)
 ; SMALL64-NEXT:    lfd 1, 0(4)
@@ -592,7 +592,7 @@ define double @loadsTWInit() #1 {
 ; LARGE64-NEXT:    addis 4, L..C7 at u(2)
 ; LARGE64-NEXT:    ld 3, L..C6 at l(3)
 ; LARGE64-NEXT:    ld 4, L..C7 at l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    addis 4, L..C8 at u(2)
 ; LARGE64-NEXT:    lfd 0, 0(3)
 ; LARGE64-NEXT:    ld 3, L..C8 at l(4)
@@ -609,25 +609,32 @@ entry:
   ret double %add
 }
 
+; External symbol reference checks for .__tls_get_addr
+
+; SMALL32: .extern .__tls_get_addr[PR]
+; SMALL64: .extern .__tls_get_addr[PR]
+; LARGE32: .extern .__tls_get_addr[PR]
+; LARGE64: .extern .__tls_get_addr[PR]
+
 ; TOC entry checks
 
 ; SMALL32-LABEL:  .toc
 ; SMALL32-LABEL:  L..C0:
 ; SMALL32-NEXT:   .tc .TGUninit[TC],TGUninit[TL]@m
 ; SMALL32-LABEL:  L..C1:
-; SMALL32-NEXT:   .tc TGUninit[TC],TGUninit[TL]
+; SMALL32-NEXT:   .tc TGUninit[TC],TGUninit[TL]@gd
 ; SMALL32-LABEL:  L..C2:
 ; SMALL32-NEXT:   .tc .TGInit[TC],TGInit[TL]@m
 ; SMALL32-LABEL:  L..C3:
-; SMALL32-NEXT:   .tc TGInit[TC],TGInit[TL]
+; SMALL32-NEXT:   .tc TGInit[TC],TGInit[TL]@gd
 ; SMALL32-LABEL:  L..C4:
 ; SMALL32-NEXT:   .tc .TIInit[TC],TIInit[TL]@m
 ; SMALL32-LABEL:  L..C5:
-; SMALL32-NEXT:   .tc TIInit[TC],TIInit[TL]
+; SMALL32-NEXT:   .tc TIInit[TC],TIInit[TL]@gd
 ; SMALL32-LABEL:  L..C6:
 ; SMALL32-NEXT:   .tc .TWInit[TC],TWInit[TL]@m
 ; SMALL32-LABEL:  L..C7:
-; SMALL32-NEXT:   .tc TWInit[TC],TWInit[TL]
+; SMALL32-NEXT:   .tc TWInit[TC],TWInit[TL]@gd
 ; SMALL32-LABEL:  L..C8:
 ; SMALL32-NEXT:   .tc GInit[TC],GInit[RW]
 
@@ -635,19 +642,19 @@ entry:
 ; LARGE32-LABEL:  L..C0:
 ; LARGE32-NEXT:   .tc .TGUninit[TE],TGUninit[TL]@m
 ; LARGE32-LABEL:  L..C1:
-; LARGE32-NEXT:   .tc TGUninit[TE],TGUninit[TL]
+; LARGE32-NEXT:   .tc TGUninit[TE],TGUninit[TL]@gd
 ; LARGE32-LABEL:  L..C2:
 ; LARGE32-NEXT:   .tc .TGInit[TE],TGInit[TL]@m
 ; LARGE32-LABEL:  L..C3:
-; LARGE32-NEXT:   .tc TGInit[TE],TGInit[TL]
+; LARGE32-NEXT:   .tc TGInit[TE],TGInit[TL]@gd
 ; LARGE32-LABEL:  L..C4:
 ; LARGE32-NEXT:   .tc .TIInit[TE],TIInit[TL]@m
 ; LARGE32-LABEL:  L..C5:
-; LARGE32-NEXT:   .tc TIInit[TE],TIInit[TL]
+; LARGE32-NEXT:   .tc TIInit[TE],TIInit[TL]@gd
 ; LARGE32-LABEL:  L..C6:
 ; LARGE32-NEXT:   .tc .TWInit[TE],TWInit[TL]@m
 ; LARGE32-LABEL:  L..C7:
-; LARGE32-NEXT:   .tc TWInit[TE],TWInit[TL]
+; LARGE32-NEXT:   .tc TWInit[TE],TWInit[TL]@gd
 ; LARGE32-LABEL:  L..C8:
 ; LARGE32-NEXT:   .tc GInit[TE],GInit[RW]
 
@@ -655,19 +662,19 @@ entry:
 ; SMALL64-LABEL:  L..C0:
 ; SMALL64-NEXT:  .tc .TGUninit[TC],TGUninit[TL]@m
 ; SMALL64-LABEL:  L..C1:
-; SMALL64-NEXT:  .tc TGUninit[TC],TGUninit[TL]
+; SMALL64-NEXT:  .tc TGUninit[TC],TGUninit[TL]@gd
 ; SMALL64-LABEL:  L..C2:
 ; SMALL64-NEXT:  .tc .TGInit[TC],TGInit[TL]@m
 ; SMALL64-LABEL:  L..C3:
-; SMALL64-NEXT:  .tc TGInit[TC],TGInit[TL]
+; SMALL64-NEXT:  .tc TGInit[TC],TGInit[TL]@gd
 ; SMALL64-LABEL:  L..C4:
 ; SMALL64-NEXT:  .tc .TIInit[TC],TIInit[TL]@m
 ; SMALL64-LABEL:  L..C5:
-; SMALL64-NEXT:  .tc TIInit[TC],TIInit[TL]
+; SMALL64-NEXT:  .tc TIInit[TC],TIInit[TL]@gd
 ; SMALL64-LABEL:  L..C6:
 ; SMALL64-NEXT:  .tc .TWInit[TC],TWInit[TL]@m
 ; SMALL64-LABEL:  L..C7:
-; SMALL64-NEXT:  .tc TWInit[TC],TWInit[TL]
+; SMALL64-NEXT:  .tc TWInit[TC],TWInit[TL]@gd
 ; SMALL64-LABEL:  L..C8:
 ; SMALL64-NEXT:  .tc GInit[TC],GInit[RW]
 
@@ -675,19 +682,19 @@ entry:
 ; LARGE64-LABEL:  L..C0:
 ; LARGE64-NEXT:  .tc .TGUninit[TE],TGUninit[TL]@m
 ; LARGE64-LABEL:  L..C1:
-; LARGE64-NEXT:  .tc TGUninit[TE],TGUninit[TL]
+; LARGE64-NEXT:  .tc TGUninit[TE],TGUninit[TL]@gd
 ; LARGE64-LABEL:  L..C2:
 ; LARGE64-NEXT:  .tc .TGInit[TE],TGInit[TL]@m
 ; LARGE64-LABEL:  L..C3:
-; LARGE64-NEXT:  .tc TGInit[TE],TGInit[TL]
+; LARGE64-NEXT:  .tc TGInit[TE],TGInit[TL]@gd
 ; LARGE64-LABEL:  L..C4:
 ; LARGE64-NEXT:  .tc .TIInit[TE],TIInit[TL]@m
 ; LARGE64-LABEL:  L..C5:
-; LARGE64-NEXT:  .tc TIInit[TE],TIInit[TL]
+; LARGE64-NEXT:  .tc TIInit[TE],TIInit[TL]@gd
 ; LARGE64-LABEL:  L..C6:
 ; LARGE64-NEXT:  .tc .TWInit[TE],TWInit[TL]@m
 ; LARGE64-LABEL:  L..C7:
-; LARGE64-NEXT:  .tc TWInit[TE],TWInit[TL]
+; LARGE64-NEXT:  .tc TWInit[TE],TWInit[TL]@gd
 ; LARGE64-LABEL:  L..C8:
 ; LARGE64-NEXT:  .tc GInit[TE],GInit[RW]
 

diff  --git a/llvm/test/CodeGen/PowerPC/aix-tls-gd-int.ll b/llvm/test/CodeGen/PowerPC/aix-tls-gd-int.ll
index 300e9b2463c92..17c0d78cc881b 100644
--- a/llvm/test/CodeGen/PowerPC/aix-tls-gd-int.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-tls-gd-int.ll
@@ -27,7 +27,7 @@ define void @storesTGUninit(i32 %Val) #0 {
 ; SMALL32-NEXT:    mr 6, 3
 ; SMALL32-NEXT:    lwz 3, L..C0(2)
 ; SMALL32-NEXT:    lwz 4, L..C1(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    stw 6, 0(3)
 ; SMALL32-NEXT:    addi 1, 1, 32
 ; SMALL32-NEXT:    lwz 0, 8(1)
@@ -44,7 +44,7 @@ define void @storesTGUninit(i32 %Val) #0 {
 ; LARGE32-NEXT:    addis 4, L..C1 at u(2)
 ; LARGE32-NEXT:    lwz 3, L..C0 at l(3)
 ; LARGE32-NEXT:    lwz 4, L..C1 at l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    stw 6, 0(3)
 ; LARGE32-NEXT:    addi 1, 1, 32
 ; LARGE32-NEXT:    lwz 0, 8(1)
@@ -59,7 +59,7 @@ define void @storesTGUninit(i32 %Val) #0 {
 ; SMALL64-NEXT:    mr 6, 3
 ; SMALL64-NEXT:    ld 3, L..C0(2)
 ; SMALL64-NEXT:    ld 4, L..C1(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    stw 6, 0(3)
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
@@ -76,7 +76,7 @@ define void @storesTGUninit(i32 %Val) #0 {
 ; LARGE64-NEXT:    addis 4, L..C1 at u(2)
 ; LARGE64-NEXT:    ld 3, L..C0 at l(3)
 ; LARGE64-NEXT:    ld 4, L..C1 at l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    stw 6, 0(3)
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
@@ -97,7 +97,7 @@ define void @storesTGInit(i32 %Val) #0 {
 ; SMALL32-NEXT:    mr 6, 3
 ; SMALL32-NEXT:    lwz 3, L..C2(2)
 ; SMALL32-NEXT:    lwz 4, L..C3(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    stw 6, 0(3)
 ; SMALL32-NEXT:    addi 1, 1, 32
 ; SMALL32-NEXT:    lwz 0, 8(1)
@@ -114,7 +114,7 @@ define void @storesTGInit(i32 %Val) #0 {
 ; LARGE32-NEXT:    addis 4, L..C3 at u(2)
 ; LARGE32-NEXT:    lwz 3, L..C2 at l(3)
 ; LARGE32-NEXT:    lwz 4, L..C3 at l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    stw 6, 0(3)
 ; LARGE32-NEXT:    addi 1, 1, 32
 ; LARGE32-NEXT:    lwz 0, 8(1)
@@ -129,7 +129,7 @@ define void @storesTGInit(i32 %Val) #0 {
 ; SMALL64-NEXT:    mr 6, 3
 ; SMALL64-NEXT:    ld 3, L..C2(2)
 ; SMALL64-NEXT:    ld 4, L..C3(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    stw 6, 0(3)
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
@@ -146,7 +146,7 @@ define void @storesTGInit(i32 %Val) #0 {
 ; LARGE64-NEXT:    addis 4, L..C3 at u(2)
 ; LARGE64-NEXT:    ld 3, L..C2 at l(3)
 ; LARGE64-NEXT:    ld 4, L..C3 at l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    stw 6, 0(3)
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
@@ -167,7 +167,7 @@ define void @storesTIUninit(i32 %Val) #0 {
 ; SMALL32-NEXT:    mr 6, 3
 ; SMALL32-NEXT:    lwz 3, L..C4(2)
 ; SMALL32-NEXT:    lwz 4, L..C5(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    stw 6, 0(3)
 ; SMALL32-NEXT:    addi 1, 1, 32
 ; SMALL32-NEXT:    lwz 0, 8(1)
@@ -184,7 +184,7 @@ define void @storesTIUninit(i32 %Val) #0 {
 ; LARGE32-NEXT:    addis 4, L..C5 at u(2)
 ; LARGE32-NEXT:    lwz 3, L..C4 at l(3)
 ; LARGE32-NEXT:    lwz 4, L..C5 at l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    stw 6, 0(3)
 ; LARGE32-NEXT:    addi 1, 1, 32
 ; LARGE32-NEXT:    lwz 0, 8(1)
@@ -199,7 +199,7 @@ define void @storesTIUninit(i32 %Val) #0 {
 ; SMALL64-NEXT:    mr 6, 3
 ; SMALL64-NEXT:    ld 3, L..C4(2)
 ; SMALL64-NEXT:    ld 4, L..C5(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    stw 6, 0(3)
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
@@ -216,7 +216,7 @@ define void @storesTIUninit(i32 %Val) #0 {
 ; LARGE64-NEXT:    addis 4, L..C5 at u(2)
 ; LARGE64-NEXT:    ld 3, L..C4 at l(3)
 ; LARGE64-NEXT:    ld 4, L..C5 at l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    stw 6, 0(3)
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
@@ -237,7 +237,7 @@ define void @storesTWUninit(i32 %Val) #0 {
 ; SMALL32-NEXT:    mr 6, 3
 ; SMALL32-NEXT:    lwz 3, L..C6(2)
 ; SMALL32-NEXT:    lwz 4, L..C7(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    stw 6, 0(3)
 ; SMALL32-NEXT:    addi 1, 1, 32
 ; SMALL32-NEXT:    lwz 0, 8(1)
@@ -254,7 +254,7 @@ define void @storesTWUninit(i32 %Val) #0 {
 ; LARGE32-NEXT:    addis 4, L..C7 at u(2)
 ; LARGE32-NEXT:    lwz 3, L..C6 at l(3)
 ; LARGE32-NEXT:    lwz 4, L..C7 at l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    stw 6, 0(3)
 ; LARGE32-NEXT:    addi 1, 1, 32
 ; LARGE32-NEXT:    lwz 0, 8(1)
@@ -269,7 +269,7 @@ define void @storesTWUninit(i32 %Val) #0 {
 ; SMALL64-NEXT:    mr 6, 3
 ; SMALL64-NEXT:    ld 3, L..C6(2)
 ; SMALL64-NEXT:    ld 4, L..C7(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    stw 6, 0(3)
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
@@ -286,7 +286,7 @@ define void @storesTWUninit(i32 %Val) #0 {
 ; LARGE64-NEXT:    addis 4, L..C7 at u(2)
 ; LARGE64-NEXT:    ld 3, L..C6 at l(3)
 ; LARGE64-NEXT:    ld 4, L..C7 at l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    stw 6, 0(3)
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
@@ -306,7 +306,7 @@ define i32 @loadsTGUninit() #1 {
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    lwz 3, L..C0(2)
 ; SMALL32-NEXT:    lwz 4, L..C1(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    lwz 4, L..C8(2)
 ; SMALL32-NEXT:    lwz 3, 0(3)
 ; SMALL32-NEXT:    lwz 4, 0(4)
@@ -325,7 +325,7 @@ define i32 @loadsTGUninit() #1 {
 ; LARGE32-NEXT:    addis 4, L..C1 at u(2)
 ; LARGE32-NEXT:    lwz 3, L..C0 at l(3)
 ; LARGE32-NEXT:    lwz 4, L..C1 at l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    lwz 3, 0(3)
 ; LARGE32-NEXT:    addis 4, L..C8 at u(2)
 ; LARGE32-NEXT:    lwz 4, L..C8 at l(4)
@@ -343,7 +343,7 @@ define i32 @loadsTGUninit() #1 {
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    ld 3, L..C0(2)
 ; SMALL64-NEXT:    ld 4, L..C1(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    ld 4, L..C8(2)
 ; SMALL64-NEXT:    lwz 3, 0(3)
 ; SMALL64-NEXT:    lwz 4, 0(4)
@@ -362,7 +362,7 @@ define i32 @loadsTGUninit() #1 {
 ; LARGE64-NEXT:    addis 4, L..C1 at u(2)
 ; LARGE64-NEXT:    ld 3, L..C0 at l(3)
 ; LARGE64-NEXT:    ld 4, L..C1 at l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    addis 4, L..C8 at u(2)
 ; LARGE64-NEXT:    lwz 3, 0(3)
 ; LARGE64-NEXT:    ld 4, L..C8 at l(4)
@@ -388,7 +388,7 @@ define i32 @loadsTGInit() #1 {
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    lwz 3, L..C2(2)
 ; SMALL32-NEXT:    lwz 4, L..C3(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    lwz 4, L..C8(2)
 ; SMALL32-NEXT:    lwz 3, 0(3)
 ; SMALL32-NEXT:    lwz 4, 0(4)
@@ -407,7 +407,7 @@ define i32 @loadsTGInit() #1 {
 ; LARGE32-NEXT:    addis 4, L..C3 at u(2)
 ; LARGE32-NEXT:    lwz 3, L..C2 at l(3)
 ; LARGE32-NEXT:    lwz 4, L..C3 at l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    lwz 3, 0(3)
 ; LARGE32-NEXT:    addis 4, L..C8 at u(2)
 ; LARGE32-NEXT:    lwz 4, L..C8 at l(4)
@@ -425,7 +425,7 @@ define i32 @loadsTGInit() #1 {
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    ld 3, L..C2(2)
 ; SMALL64-NEXT:    ld 4, L..C3(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    ld 4, L..C8(2)
 ; SMALL64-NEXT:    lwz 3, 0(3)
 ; SMALL64-NEXT:    lwz 4, 0(4)
@@ -444,7 +444,7 @@ define i32 @loadsTGInit() #1 {
 ; LARGE64-NEXT:    addis 4, L..C3 at u(2)
 ; LARGE64-NEXT:    ld 3, L..C2 at l(3)
 ; LARGE64-NEXT:    ld 4, L..C3 at l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    addis 4, L..C8 at u(2)
 ; LARGE64-NEXT:    lwz 3, 0(3)
 ; LARGE64-NEXT:    ld 4, L..C8 at l(4)
@@ -470,7 +470,7 @@ define i32 @loadsTIUninit() #1 {
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    lwz 3, L..C4(2)
 ; SMALL32-NEXT:    lwz 4, L..C5(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    lwz 4, L..C8(2)
 ; SMALL32-NEXT:    lwz 3, 0(3)
 ; SMALL32-NEXT:    lwz 4, 0(4)
@@ -489,7 +489,7 @@ define i32 @loadsTIUninit() #1 {
 ; LARGE32-NEXT:    addis 4, L..C5 at u(2)
 ; LARGE32-NEXT:    lwz 3, L..C4 at l(3)
 ; LARGE32-NEXT:    lwz 4, L..C5 at l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    lwz 3, 0(3)
 ; LARGE32-NEXT:    addis 4, L..C8 at u(2)
 ; LARGE32-NEXT:    lwz 4, L..C8 at l(4)
@@ -507,7 +507,7 @@ define i32 @loadsTIUninit() #1 {
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    ld 3, L..C4(2)
 ; SMALL64-NEXT:    ld 4, L..C5(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    ld 4, L..C8(2)
 ; SMALL64-NEXT:    lwz 3, 0(3)
 ; SMALL64-NEXT:    lwz 4, 0(4)
@@ -526,7 +526,7 @@ define i32 @loadsTIUninit() #1 {
 ; LARGE64-NEXT:    addis 4, L..C5 at u(2)
 ; LARGE64-NEXT:    ld 3, L..C4 at l(3)
 ; LARGE64-NEXT:    ld 4, L..C5 at l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    addis 4, L..C8 at u(2)
 ; LARGE64-NEXT:    lwz 3, 0(3)
 ; LARGE64-NEXT:    ld 4, L..C8 at l(4)
@@ -552,7 +552,7 @@ define i32 @loadsTWUninit() #1 {
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    lwz 3, L..C6(2)
 ; SMALL32-NEXT:    lwz 4, L..C7(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    lwz 4, L..C8(2)
 ; SMALL32-NEXT:    lwz 3, 0(3)
 ; SMALL32-NEXT:    lwz 4, 0(4)
@@ -571,7 +571,7 @@ define i32 @loadsTWUninit() #1 {
 ; LARGE32-NEXT:    addis 4, L..C7 at u(2)
 ; LARGE32-NEXT:    lwz 3, L..C6 at l(3)
 ; LARGE32-NEXT:    lwz 4, L..C7 at l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    lwz 3, 0(3)
 ; LARGE32-NEXT:    addis 4, L..C8 at u(2)
 ; LARGE32-NEXT:    lwz 4, L..C8 at l(4)
@@ -589,7 +589,7 @@ define i32 @loadsTWUninit() #1 {
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    ld 3, L..C6(2)
 ; SMALL64-NEXT:    ld 4, L..C7(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    ld 4, L..C8(2)
 ; SMALL64-NEXT:    lwz 3, 0(3)
 ; SMALL64-NEXT:    lwz 4, 0(4)
@@ -608,7 +608,7 @@ define i32 @loadsTWUninit() #1 {
 ; LARGE64-NEXT:    addis 4, L..C7 at u(2)
 ; LARGE64-NEXT:    ld 3, L..C6 at l(3)
 ; LARGE64-NEXT:    ld 4, L..C7 at l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    addis 4, L..C8 at u(2)
 ; LARGE64-NEXT:    lwz 3, 0(3)
 ; LARGE64-NEXT:    ld 4, L..C8 at l(4)
@@ -625,25 +625,32 @@ entry:
   ret i32 %add
 }
 
+; External symbol reference checks for .__tls_get_addr
+
+; SMALL32: .extern .__tls_get_addr[PR]
+; SMALL64: .extern .__tls_get_addr[PR]
+; LARGE32: .extern .__tls_get_addr[PR]
+; LARGE64: .extern .__tls_get_addr[PR]
+
 ; TOC entry checks
 
 ; SMALL32-LABEL: .toc
 ; SMALL32-LABEL: L..C0:
 ; SMALL32-NEXT:	 .tc .TGUninit[TC],TGUninit[TL]@m
 ; SMALL32-LABEL: L..C1:
-; SMALL32-NEXT:	 .tc TGUninit[TC],TGUninit[TL]
+; SMALL32-NEXT:	 .tc TGUninit[TC],TGUninit[TL]@gd
 ; SMALL32-LABEL: L..C2:
 ; SMALL32-NEXT:	 .tc .TGInit[TC],TGInit[TL]@m
 ; SMALL32-LABEL: L..C3:
-; SMALL32-NEXT:	 .tc TGInit[TC],TGInit[TL]
+; SMALL32-NEXT:	 .tc TGInit[TC],TGInit[TL]@gd
 ; SMALL32-LABEL: L..C4:
 ; SMALL32-NEXT:	 .tc .TIUninit[TC],TIUninit[UL]@m
 ; SMALL32-LABEL: L..C5:
-; SMALL32-NEXT:	 .tc TIUninit[TC],TIUninit[UL]
+; SMALL32-NEXT:	 .tc TIUninit[TC],TIUninit[UL]@gd
 ; SMALL32-LABEL: L..C6:
 ; SMALL32-NEXT:	 .tc .TWUninit[TC],TWUninit[TL]@m
 ; SMALL32-LABEL: L..C7:
-; SMALL32-NEXT:	 .tc TWUninit[TC],TWUninit[TL]
+; SMALL32-NEXT:	 .tc TWUninit[TC],TWUninit[TL]@gd
 ; SMALL32-LABEL: L..C8:
 ; SMALL32-NEXT:	 .tc GInit[TC],GInit[RW]
 
@@ -651,19 +658,19 @@ entry:
 ; LARGE32-LABEL: L..C0:
 ; LARGE32-NEXT:  .tc .TGUninit[TE],TGUninit[TL]@m
 ; LARGE32-LABEL: L..C1:
-; LARGE32-NEXT:  .tc TGUninit[TE],TGUninit[TL]
+; LARGE32-NEXT:  .tc TGUninit[TE],TGUninit[TL]@gd
 ; LARGE32-LABEL: L..C2:
 ; LARGE32-NEXT:  .tc .TGInit[TE],TGInit[TL]@m
 ; LARGE32-LABEL: L..C3:
-; LARGE32-NEXT:  .tc TGInit[TE],TGInit[TL]
+; LARGE32-NEXT:  .tc TGInit[TE],TGInit[TL]@gd
 ; LARGE32-LABEL: L..C4:
 ; LARGE32-NEXT:  .tc .TIUninit[TE],TIUninit[UL]@m
 ; LARGE32-LABEL: L..C5:
-; LARGE32-NEXT:  .tc TIUninit[TE],TIUninit[UL]
+; LARGE32-NEXT:  .tc TIUninit[TE],TIUninit[UL]@gd
 ; LARGE32-LABEL: L..C6:
 ; LARGE32-NEXT:  .tc .TWUninit[TE],TWUninit[TL]@m
 ; LARGE32-LABEL: L..C7:
-; LARGE32-NEXT:  .tc TWUninit[TE],TWUninit[TL]
+; LARGE32-NEXT:  .tc TWUninit[TE],TWUninit[TL]@gd
 ; LARGE32-LABEL: L..C8:
 ; LARGE32-NEXT:  .tc GInit[TE],GInit[RW]
 
@@ -671,19 +678,19 @@ entry:
 ; SMALL64-LABEL:  L..C0:
 ; SMALL64-NEXT:   .tc .TGUninit[TC],TGUninit[TL]@m
 ; SMALL64-LABEL:  L..C1:
-; SMALL64-NEXT:   .tc TGUninit[TC],TGUninit[TL]
+; SMALL64-NEXT:   .tc TGUninit[TC],TGUninit[TL]@gd
 ; SMALL64-LABEL:  L..C2:
 ; SMALL64-NEXT:   .tc .TGInit[TC],TGInit[TL]@m
 ; SMALL64-LABEL:  L..C3:
-; SMALL64-NEXT:   .tc TGInit[TC],TGInit[TL]
+; SMALL64-NEXT:   .tc TGInit[TC],TGInit[TL]@gd
 ; SMALL64-LABEL:  L..C4:
 ; SMALL64-NEXT:   .tc .TIUninit[TC],TIUninit[UL]@m
 ; SMALL64-LABEL:  L..C5:
-; SMALL64-NEXT:   .tc TIUninit[TC],TIUninit[UL]
+; SMALL64-NEXT:   .tc TIUninit[TC],TIUninit[UL]@gd
 ; SMALL64-LABEL:  L..C6:
 ; SMALL64-NEXT:   .tc .TWUninit[TC],TWUninit[TL]@m
 ; SMALL64-LABEL:  L..C7:
-; SMALL64-NEXT:   .tc TWUninit[TC],TWUninit[TL]
+; SMALL64-NEXT:   .tc TWUninit[TC],TWUninit[TL]@gd
 ; SMALL64-LABEL:  L..C8:
 ; SMALL64-NEXT:   .tc GInit[TC],GInit[RW]
 
@@ -691,19 +698,19 @@ entry:
 ; LARGE64-LABEL:  L..C0:
 ; LARGE64-NEXT:  .tc .TGUninit[TE],TGUninit[TL]@m
 ; LARGE64-LABEL:  L..C1:
-; LARGE64-NEXT:  .tc TGUninit[TE],TGUninit[TL]
+; LARGE64-NEXT:  .tc TGUninit[TE],TGUninit[TL]@gd
 ; LARGE64-LABEL:  L..C2:
 ; LARGE64-NEXT:  .tc .TGInit[TE],TGInit[TL]@m
 ; LARGE64-LABEL:  L..C3:
-; LARGE64-NEXT:  .tc TGInit[TE],TGInit[TL]
+; LARGE64-NEXT:  .tc TGInit[TE],TGInit[TL]@gd
 ; LARGE64-LABEL:  L..C4:
 ; LARGE64-NEXT:  .tc .TIUninit[TE],TIUninit[UL]@m
 ; LARGE64-LABEL:  L..C5:
-; LARGE64-NEXT:  .tc TIUninit[TE],TIUninit[UL]
+; LARGE64-NEXT:  .tc TIUninit[TE],TIUninit[UL]@gd
 ; LARGE64-LABEL:  L..C6:
 ; LARGE64-NEXT:  .tc .TWUninit[TE],TWUninit[TL]@m
 ; LARGE64-LABEL:  L..C7:
-; LARGE64-NEXT:  .tc TWUninit[TE],TWUninit[TL]
+; LARGE64-NEXT:  .tc TWUninit[TE],TWUninit[TL]@gd
 ; LARGE64-LABEL:  L..C8:
 ; LARGE64-NEXT:  .tc GInit[TE],GInit[RW]
 

diff  --git a/llvm/test/CodeGen/PowerPC/aix-tls-gd-longlong.ll b/llvm/test/CodeGen/PowerPC/aix-tls-gd-longlong.ll
index 0fdc51216b0c7..f4a7ea122424a 100644
--- a/llvm/test/CodeGen/PowerPC/aix-tls-gd-longlong.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-tls-gd-longlong.ll
@@ -28,7 +28,7 @@ define void @storesTGInit(i64 %Val) #0 {
 ; SMALL32-NEXT:    mr 7, 3
 ; SMALL32-NEXT:    lwz 3, L..C0(2)
 ; SMALL32-NEXT:    lwz 4, L..C1(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    stw 6, 4(3)
 ; SMALL32-NEXT:    stw 7, 0(3)
 ; SMALL32-NEXT:    addi 1, 1, 32
@@ -47,7 +47,7 @@ define void @storesTGInit(i64 %Val) #0 {
 ; LARGE32-NEXT:    addis 4, L..C1 at u(2)
 ; LARGE32-NEXT:    lwz 3, L..C0 at l(3)
 ; LARGE32-NEXT:    lwz 4, L..C1 at l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    stw 6, 4(3)
 ; LARGE32-NEXT:    stw 7, 0(3)
 ; LARGE32-NEXT:    addi 1, 1, 32
@@ -63,7 +63,7 @@ define void @storesTGInit(i64 %Val) #0 {
 ; SMALL64-NEXT:    mr 6, 3
 ; SMALL64-NEXT:    ld 3, L..C0(2)
 ; SMALL64-NEXT:    ld 4, L..C1(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    std 6, 0(3)
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
@@ -80,7 +80,7 @@ define void @storesTGInit(i64 %Val) #0 {
 ; LARGE64-NEXT:    addis 4, L..C1 at u(2)
 ; LARGE64-NEXT:    ld 3, L..C0 at l(3)
 ; LARGE64-NEXT:    ld 4, L..C1 at l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    std 6, 0(3)
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
@@ -102,7 +102,7 @@ define void @storesTIUninit(i64 %Val) #0 {
 ; SMALL32-NEXT:    mr 7, 3
 ; SMALL32-NEXT:    lwz 3, L..C2(2)
 ; SMALL32-NEXT:    lwz 4, L..C3(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    stw 6, 4(3)
 ; SMALL32-NEXT:    stw 7, 0(3)
 ; SMALL32-NEXT:    addi 1, 1, 32
@@ -121,7 +121,7 @@ define void @storesTIUninit(i64 %Val) #0 {
 ; LARGE32-NEXT:    addis 4, L..C3 at u(2)
 ; LARGE32-NEXT:    lwz 3, L..C2 at l(3)
 ; LARGE32-NEXT:    lwz 4, L..C3 at l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    stw 6, 4(3)
 ; LARGE32-NEXT:    stw 7, 0(3)
 ; LARGE32-NEXT:    addi 1, 1, 32
@@ -137,7 +137,7 @@ define void @storesTIUninit(i64 %Val) #0 {
 ; SMALL64-NEXT:    mr 6, 3
 ; SMALL64-NEXT:    ld 3, L..C2(2)
 ; SMALL64-NEXT:    ld 4, L..C3(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    std 6, 0(3)
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
@@ -154,7 +154,7 @@ define void @storesTIUninit(i64 %Val) #0 {
 ; LARGE64-NEXT:    addis 4, L..C3 at u(2)
 ; LARGE64-NEXT:    ld 3, L..C2 at l(3)
 ; LARGE64-NEXT:    ld 4, L..C3 at l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    std 6, 0(3)
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
@@ -176,7 +176,7 @@ define void @storesTIInit(i64 %Val) #0 {
 ; SMALL32-NEXT:    mr 7, 3
 ; SMALL32-NEXT:    lwz 3, L..C4(2)
 ; SMALL32-NEXT:    lwz 4, L..C5(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    stw 6, 4(3)
 ; SMALL32-NEXT:    stw 7, 0(3)
 ; SMALL32-NEXT:    addi 1, 1, 32
@@ -195,7 +195,7 @@ define void @storesTIInit(i64 %Val) #0 {
 ; LARGE32-NEXT:    addis 4, L..C5 at u(2)
 ; LARGE32-NEXT:    lwz 3, L..C4 at l(3)
 ; LARGE32-NEXT:    lwz 4, L..C5 at l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    stw 6, 4(3)
 ; LARGE32-NEXT:    stw 7, 0(3)
 ; LARGE32-NEXT:    addi 1, 1, 32
@@ -211,7 +211,7 @@ define void @storesTIInit(i64 %Val) #0 {
 ; SMALL64-NEXT:    mr 6, 3
 ; SMALL64-NEXT:    ld 3, L..C4(2)
 ; SMALL64-NEXT:    ld 4, L..C5(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    std 6, 0(3)
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
@@ -228,7 +228,7 @@ define void @storesTIInit(i64 %Val) #0 {
 ; LARGE64-NEXT:    addis 4, L..C5 at u(2)
 ; LARGE64-NEXT:    ld 3, L..C4 at l(3)
 ; LARGE64-NEXT:    ld 4, L..C5 at l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    std 6, 0(3)
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
@@ -250,7 +250,7 @@ define void @storesTWInit(i64 %Val) #0 {
 ; SMALL32-NEXT:    mr 7, 3
 ; SMALL32-NEXT:    lwz 3, L..C6(2)
 ; SMALL32-NEXT:    lwz 4, L..C7(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    stw 6, 4(3)
 ; SMALL32-NEXT:    stw 7, 0(3)
 ; SMALL32-NEXT:    addi 1, 1, 32
@@ -269,7 +269,7 @@ define void @storesTWInit(i64 %Val) #0 {
 ; LARGE32-NEXT:    addis 4, L..C7 at u(2)
 ; LARGE32-NEXT:    lwz 3, L..C6 at l(3)
 ; LARGE32-NEXT:    lwz 4, L..C7 at l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    stw 6, 4(3)
 ; LARGE32-NEXT:    stw 7, 0(3)
 ; LARGE32-NEXT:    addi 1, 1, 32
@@ -285,7 +285,7 @@ define void @storesTWInit(i64 %Val) #0 {
 ; SMALL64-NEXT:    mr 6, 3
 ; SMALL64-NEXT:    ld 3, L..C6(2)
 ; SMALL64-NEXT:    ld 4, L..C7(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    std 6, 0(3)
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
@@ -302,7 +302,7 @@ define void @storesTWInit(i64 %Val) #0 {
 ; LARGE64-NEXT:    addis 4, L..C7 at u(2)
 ; LARGE64-NEXT:    ld 3, L..C6 at l(3)
 ; LARGE64-NEXT:    ld 4, L..C7 at l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    std 6, 0(3)
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
@@ -322,7 +322,7 @@ define i64 @loadsTGInit() #1 {
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    lwz 3, L..C0(2)
 ; SMALL32-NEXT:    lwz 4, L..C1(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    lwz 4, L..C8(2)
 ; SMALL32-NEXT:    lwz 5, 4(3)
 ; SMALL32-NEXT:    lwz 6, 4(4)
@@ -344,7 +344,7 @@ define i64 @loadsTGInit() #1 {
 ; LARGE32-NEXT:    addis 4, L..C1 at u(2)
 ; LARGE32-NEXT:    lwz 3, L..C0 at l(3)
 ; LARGE32-NEXT:    lwz 4, L..C1 at l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    lwz 4, 4(3)
 ; LARGE32-NEXT:    lwz 3, 0(3)
 ; LARGE32-NEXT:    addis 5, L..C8 at u(2)
@@ -365,7 +365,7 @@ define i64 @loadsTGInit() #1 {
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    ld 3, L..C0(2)
 ; SMALL64-NEXT:    ld 4, L..C1(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    ld 4, L..C8(2)
 ; SMALL64-NEXT:    ld 3, 0(3)
 ; SMALL64-NEXT:    ld 4, 0(4)
@@ -384,7 +384,7 @@ define i64 @loadsTGInit() #1 {
 ; LARGE64-NEXT:    addis 4, L..C1 at u(2)
 ; LARGE64-NEXT:    ld 3, L..C0 at l(3)
 ; LARGE64-NEXT:    ld 4, L..C1 at l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    addis 4, L..C8 at u(2)
 ; LARGE64-NEXT:    ld 3, 0(3)
 ; LARGE64-NEXT:    ld 4, L..C8 at l(4)
@@ -410,7 +410,7 @@ define i64 @loadsTIUninit() #1 {
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    lwz 3, L..C2(2)
 ; SMALL32-NEXT:    lwz 4, L..C3(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    lwz 4, L..C8(2)
 ; SMALL32-NEXT:    lwz 5, 4(3)
 ; SMALL32-NEXT:    lwz 6, 4(4)
@@ -432,7 +432,7 @@ define i64 @loadsTIUninit() #1 {
 ; LARGE32-NEXT:    addis 4, L..C3 at u(2)
 ; LARGE32-NEXT:    lwz 3, L..C2 at l(3)
 ; LARGE32-NEXT:    lwz 4, L..C3 at l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    lwz 4, 4(3)
 ; LARGE32-NEXT:    lwz 3, 0(3)
 ; LARGE32-NEXT:    addis 5, L..C8 at u(2)
@@ -453,7 +453,7 @@ define i64 @loadsTIUninit() #1 {
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    ld 3, L..C2(2)
 ; SMALL64-NEXT:    ld 4, L..C3(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    ld 4, L..C8(2)
 ; SMALL64-NEXT:    ld 3, 0(3)
 ; SMALL64-NEXT:    ld 4, 0(4)
@@ -472,7 +472,7 @@ define i64 @loadsTIUninit() #1 {
 ; LARGE64-NEXT:    addis 4, L..C3 at u(2)
 ; LARGE64-NEXT:    ld 3, L..C2 at l(3)
 ; LARGE64-NEXT:    ld 4, L..C3 at l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    addis 4, L..C8 at u(2)
 ; LARGE64-NEXT:    ld 3, 0(3)
 ; LARGE64-NEXT:    ld 4, L..C8 at l(4)
@@ -498,7 +498,7 @@ define i64 @loadsTIInit() #1 {
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    lwz 3, L..C4(2)
 ; SMALL32-NEXT:    lwz 4, L..C5(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    lwz 4, L..C8(2)
 ; SMALL32-NEXT:    lwz 5, 4(3)
 ; SMALL32-NEXT:    lwz 6, 4(4)
@@ -520,7 +520,7 @@ define i64 @loadsTIInit() #1 {
 ; LARGE32-NEXT:    addis 4, L..C5 at u(2)
 ; LARGE32-NEXT:    lwz 3, L..C4 at l(3)
 ; LARGE32-NEXT:    lwz 4, L..C5 at l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    lwz 4, 4(3)
 ; LARGE32-NEXT:    lwz 3, 0(3)
 ; LARGE32-NEXT:    addis 5, L..C8 at u(2)
@@ -541,7 +541,7 @@ define i64 @loadsTIInit() #1 {
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    ld 3, L..C4(2)
 ; SMALL64-NEXT:    ld 4, L..C5(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    ld 4, L..C8(2)
 ; SMALL64-NEXT:    ld 3, 0(3)
 ; SMALL64-NEXT:    ld 4, 0(4)
@@ -560,7 +560,7 @@ define i64 @loadsTIInit() #1 {
 ; LARGE64-NEXT:    addis 4, L..C5 at u(2)
 ; LARGE64-NEXT:    ld 3, L..C4 at l(3)
 ; LARGE64-NEXT:    ld 4, L..C5 at l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    addis 4, L..C8 at u(2)
 ; LARGE64-NEXT:    ld 3, 0(3)
 ; LARGE64-NEXT:    ld 4, L..C8 at l(4)
@@ -586,7 +586,7 @@ define i64 @loadsTWInit() #1 {
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    lwz 3, L..C6(2)
 ; SMALL32-NEXT:    lwz 4, L..C7(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    lwz 4, L..C8(2)
 ; SMALL32-NEXT:    lwz 5, 4(3)
 ; SMALL32-NEXT:    lwz 6, 4(4)
@@ -608,7 +608,7 @@ define i64 @loadsTWInit() #1 {
 ; LARGE32-NEXT:    addis 4, L..C7 at u(2)
 ; LARGE32-NEXT:    lwz 3, L..C6 at l(3)
 ; LARGE32-NEXT:    lwz 4, L..C7 at l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    lwz 4, 4(3)
 ; LARGE32-NEXT:    lwz 3, 0(3)
 ; LARGE32-NEXT:    addis 5, L..C8 at u(2)
@@ -629,7 +629,7 @@ define i64 @loadsTWInit() #1 {
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    ld 3, L..C6(2)
 ; SMALL64-NEXT:    ld 4, L..C7(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    ld 4, L..C8(2)
 ; SMALL64-NEXT:    ld 3, 0(3)
 ; SMALL64-NEXT:    ld 4, 0(4)
@@ -648,7 +648,7 @@ define i64 @loadsTWInit() #1 {
 ; LARGE64-NEXT:    addis 4, L..C7 at u(2)
 ; LARGE64-NEXT:    ld 3, L..C6 at l(3)
 ; LARGE64-NEXT:    ld 4, L..C7 at l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    addis 4, L..C8 at u(2)
 ; LARGE64-NEXT:    ld 3, 0(3)
 ; LARGE64-NEXT:    ld 4, L..C8 at l(4)
@@ -665,25 +665,32 @@ entry:
   ret i64 %add
 }
 
+; External symbol reference checks for .__tls_get_addr
+
+; SMALL32: .extern .__tls_get_addr[PR]
+; SMALL64: .extern .__tls_get_addr[PR]
+; LARGE32: .extern .__tls_get_addr[PR]
+; LARGE64: .extern .__tls_get_addr[PR]
+
 ; TOC entry checks
 
 ; SMALL32-LABEL:	.toc
 ; SMALL32-LABEL:  L..C0:
 ; SMALL32-NEXT:  .tc .TGInit[TC],TGInit[TL]@m
 ; SMALL32-LABEL:  L..C1:
-; SMALL32-NEXT:  .tc TGInit[TC],TGInit[TL]
+; SMALL32-NEXT:  .tc TGInit[TC],TGInit[TL]@gd
 ; SMALL32-LABEL:  L..C2:
 ; SMALL32-NEXT:  .tc .TIUninit[TC],TIUninit[UL]@m
 ; SMALL32-LABEL:  L..C3:
-; SMALL32-NEXT:  .tc TIUninit[TC],TIUninit[UL]
+; SMALL32-NEXT:  .tc TIUninit[TC],TIUninit[UL]@gd
 ; SMALL32-LABEL:  L..C4:
 ; SMALL32-NEXT:  .tc .TIInit[TC],TIInit[TL]@m
 ; SMALL32-LABEL:  L..C5:
-; SMALL32-NEXT:  .tc TIInit[TC],TIInit[TL]
+; SMALL32-NEXT:  .tc TIInit[TC],TIInit[TL]@gd
 ; SMALL32-LABEL:  L..C6:
 ; SMALL32-NEXT:  .tc .TWInit[TC],TWInit[TL]@m
 ; SMALL32-LABEL:  L..C7:
-; SMALL32-NEXT:  .tc TWInit[TC],TWInit[TL]
+; SMALL32-NEXT:  .tc TWInit[TC],TWInit[TL]@gd
 ; SMALL32-LABEL:  L..C8:
 ; SMALL32-NEXT:  .tc GInit[TC],GInit[RW]
 
@@ -691,19 +698,19 @@ entry:
 ; LARGE32-LABEL:  L..C0:
 ; LARGE32-NEXT:  .tc .TGInit[TE],TGInit[TL]@m
 ; LARGE32-LABEL:  L..C1:
-; LARGE32-NEXT:  .tc TGInit[TE],TGInit[TL]
+; LARGE32-NEXT:  .tc TGInit[TE],TGInit[TL]@gd
 ; LARGE32-LABEL:  L..C2:
 ; LARGE32-NEXT:  .tc .TIUninit[TE],TIUninit[UL]@m
 ; LARGE32-LABEL:  L..C3:
-; LARGE32-NEXT:  .tc TIUninit[TE],TIUninit[UL]
+; LARGE32-NEXT:  .tc TIUninit[TE],TIUninit[UL]@gd
 ; LARGE32-LABEL:  L..C4:
 ; LARGE32-NEXT:  .tc .TIInit[TE],TIInit[TL]@m
 ; LARGE32-LABEL:  L..C5:
-; LARGE32-NEXT:  .tc TIInit[TE],TIInit[TL]
+; LARGE32-NEXT:  .tc TIInit[TE],TIInit[TL]@gd
 ; LARGE32-LABEL:  L..C6:
 ; LARGE32-NEXT:  .tc .TWInit[TE],TWInit[TL]@m
 ; LARGE32-LABEL:  L..C7:
-; LARGE32-NEXT:  .tc TWInit[TE],TWInit[TL]
+; LARGE32-NEXT:  .tc TWInit[TE],TWInit[TL]@gd
 ; LARGE32-LABEL:  L..C8:
 ; LARGE32-NEXT:  .tc GInit[TE],GInit[RW]
 
@@ -711,19 +718,19 @@ entry:
 ; SMALL64-LABEL:  L..C0:
 ; SMALL64-NEXT:  .tc .TGInit[TC],TGInit[TL]@m
 ; SMALL64-LABEL:  L..C1:
-; SMALL64-NEXT:  .tc TGInit[TC],TGInit[TL]
+; SMALL64-NEXT:  .tc TGInit[TC],TGInit[TL]@gd
 ; SMALL64-LABEL:  L..C2:
 ; SMALL64-NEXT:  .tc .TIUninit[TC],TIUninit[UL]@m
 ; SMALL64-LABEL:  L..C3:
-; SMALL64-NEXT:  .tc TIUninit[TC],TIUninit[UL]
+; SMALL64-NEXT:  .tc TIUninit[TC],TIUninit[UL]@gd
 ; SMALL64-LABEL:  L..C4:
 ; SMALL64-NEXT:  .tc .TIInit[TC],TIInit[TL]@m
 ; SMALL64-LABEL:  L..C5:
-; SMALL64-NEXT:  .tc TIInit[TC],TIInit[TL]
+; SMALL64-NEXT:  .tc TIInit[TC],TIInit[TL]@gd
 ; SMALL64-LABEL:  L..C6:
 ; SMALL64-NEXT:  .tc .TWInit[TC],TWInit[TL]@m
 ; SMALL64-LABEL:  L..C7:
-; SMALL64-NEXT:  .tc TWInit[TC],TWInit[TL]
+; SMALL64-NEXT:  .tc TWInit[TC],TWInit[TL]@gd
 ; SMALL64-LABEL:  L..C8:
 ; SMALL64-NEXT:  .tc GInit[TC],GInit[RW]
 
@@ -731,19 +738,19 @@ entry:
 ; LARGE64-LABEL:  L..C0:
 ; LARGE64-NEXT:  .tc .TGInit[TE],TGInit[TL]@m
 ; LARGE64-LABEL:  L..C1:
-; LARGE64-NEXT:  .tc TGInit[TE],TGInit[TL]
+; LARGE64-NEXT:  .tc TGInit[TE],TGInit[TL]@gd
 ; LARGE64-LABEL:  L..C2:
 ; LARGE64-NEXT:  .tc .TIUninit[TE],TIUninit[UL]@m
 ; LARGE64-LABEL:  L..C3:
-; LARGE64-NEXT:  .tc TIUninit[TE],TIUninit[UL]
+; LARGE64-NEXT:  .tc TIUninit[TE],TIUninit[UL]@gd
 ; LARGE64-LABEL:  L..C4:
 ; LARGE64-NEXT:  .tc .TIInit[TE],TIInit[TL]@m
 ; LARGE64-LABEL:  L..C5:
-; LARGE64-NEXT:  .tc TIInit[TE],TIInit[TL]
+; LARGE64-NEXT:  .tc TIInit[TE],TIInit[TL]@gd
 ; LARGE64-LABEL:  L..C6:
 ; LARGE64-NEXT:  .tc .TWInit[TE],TWInit[TL]@m
 ; LARGE64-LABEL:  L..C7:
-; LARGE64-NEXT:  .tc TWInit[TE],TWInit[TL]
+; LARGE64-NEXT:  .tc TWInit[TE],TWInit[TL]@gd
 ; LARGE64-LABEL:  L..C8:
 ; LARGE64-NEXT:  .tc GInit[TE],GInit[RW]
 


        


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