[PATCH] D101544: [AArch64][SVE] Improve sve.convert.to.svbool lowering

[Peter Waller via Phabricator via llvm-commits]

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The sve.convert.to.svbool intrinsic has the effect of widening a logical
<M x i1> vector representing lanes into a physical <16 x i1> vector
representing bits in a predicate register.

In general if converting to svbool from a narrower vector, the contents of
lanes in the physical register not coming from the original vector may be
non-zero. sve.convert.to.svbool specifies the new lanes to be zero, requiring
an 'and' mask. For lanes coming from a ptrue or a comparison, however, they are
known to be zero and this can be elided.

CodeGen Before:

  ptrue p0.s, vl16
  ptrue p1.s
  ptrue p2.b
  and   p0.b, p2/z, p0.b, p1.b
  ret

After:

  ptrue	p0.s, vl16
  ret


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D101544

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-intrinsics-reinterpret.ll

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