[PATCH] D101543: [AArch64][GlobalISel] Fix width value for G_SBFX/G_UBFX

[Brendon Cahoon via Phabricator via llvm-commits]

bcahoon created this revision.
bcahoon added a reviewer: paquette.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls, rovka.
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When creating G_SBFX/G_UBFX opcodes, specify the last operand
as a width instead of the bit position. The bit position is used for
the AArch64 SBFM and UBFM instructions. Then, the bit position
is converted to a width if the SBFX/UBFX aliases are generated, but
the bit position is used for creating other aliases, such as the shifts.

See https://llvm.org/docs/GlobalISel/GenericOpcode.html#g-sbfx-g-ubfx
for the opcode definition.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D101543

Files:
  llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
  llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/form-bitfield-extract-from-sextinreg.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-sbfx.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-ubfx.mir

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