[PATCH] D100856: [RISCV] Support STEP_VECTOR with a step greater than one

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 added a comment.

I hit this one recently, too!



================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:3774
+      SDValue StepVal =
+          DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT,
+                      DAG.getConstant(Log2_64(StepValImm), DL, XLenVT));
----------------
I used `DAG.getSplatVector` here (I guess makes little difference) but I didn't consider the power-of-two case.

I'm curious that we cannot combine a case like this

```
      t13: nxv1i64 = RISCVISD::VID_VL t12, Register:i64 $x0
      t14: nxv1i64 = splat_vector Constant:i64<2>
    t15: nxv1i64 = mul t13, t14
```

into 

```
      t13: nxv1i64 = RISCVISD::VID_VL t12, Register:i64 $x0
      t16: nxv1i64 = splat_vector Constant:i64<1>
    t15: nxv1i64 = shl t13, t16
```



Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100856/new/

https://reviews.llvm.org/D100856