[PATCH] D101474: [AMDGPU] Make some VOP3 insts commutable
Joe Nash via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 28 10:58:54 PDT 2021
Joe_Nash created this revision.
Joe_Nash added reviewers: foad, rampitec.
Herald added subscribers: wenlei, kerbowa, steven_wu, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl, arsenm.
Joe_Nash requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
Herald added a project: LLVM.
Note, only src0 and src1 will be commuted if the isCommutable flag
is set. This patch does not change that, it just makes it possible
to commute src0 and src1 of some U/I/B vop3 instructions.
This patch revises d35d8da7d6ac6c08578ec0569b072292631691e0 <https://reviews.llvm.org/rGd35d8da7d6ac6c08578ec0569b072292631691e0>.
It contains the commute opportunities excluding float insts
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D101474
Files:
llvm/lib/Target/AMDGPU/VOP3Instructions.td
llvm/test/CodeGen/AMDGPU/GlobalISel/add_shl.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.ltolz.a16.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/roundeven.ll
llvm/test/CodeGen/AMDGPU/commute-vop3.mir
llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll
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