[PATCH] D101414: [AMDGPU] Disable the scalar IR, SDWA and load store vectorizer passes at -O1

Baptiste Saleil via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Apr 28 10:58:43 PDT 2021


bsaleil added a comment.

In D101414#2721285 <https://reviews.llvm.org/D101414#2721285>, @arsenm wrote:

> Needs a testcase. I think we have some pass pipeline tests already to show what's run (maybe not for -O1, I didn't know anyone actually used it)

@arsenm, I think we only had a test case for `opt`, so I added a new test case to show which passes are run for `llc` for all the optimization levels.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D101414/new/

https://reviews.llvm.org/D101414



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