[llvm] 1d4d6a9 - [RISCV] Add explanatory comment to RISCVOp::OPERAND_AVL.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2021-04-28T09:55:36-07:00
New Revision: 1d4d6a96164ea9f7d24103ca6fa1ad500386aff6

URL: https://github.com/llvm/llvm-project/commit/1d4d6a96164ea9f7d24103ca6fa1ad500386aff6
DIFF: https://github.com/llvm/llvm-project/commit/1d4d6a96164ea9f7d24103ca6fa1ad500386aff6.diff

LOG: [RISCV] Add explanatory comment to RISCVOp::OPERAND_AVL.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index f86b65a01523f..1a040a7e2523a 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -118,6 +118,9 @@ enum OperandType : unsigned {
   OPERAND_UIMM20,
   OPERAND_UIMMLOG2XLEN,
   OPERAND_LAST_RISCV_IMM = OPERAND_UIMMLOG2XLEN,
+  // Operand is either a register or uimm5, this is used by V extension pseudo
+  // instructions to represent a value that be passed as AVL to either vsetvli
+  // or vsetivli.
   OPERAND_AVL,
 };
 } // namespace RISCVOp