[PATCH] D101469: [RISCV] Enable interleaved vectorization for RVV

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/test/Transforms/LoopVectorize/RISCV/riscv-interleaved.ll:4
+; CHECK-LABEL: foo
+; CHECK: LV: IC is 2
+
----------------
Why are we not checking the generated IR?


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Comment at: llvm/test/Transforms/LoopVectorize/RISCV/riscv-interleaved.ll:41
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 13.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: NoDebug, enums: !2, splitDebugInlining: false, nameTableKind: None)
+!1 = !DIFile(filename: "riscv-interleaved.c", directory: "llvm-project")
----------------
Do we need the debug info?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101469/new/

https://reviews.llvm.org/D101469