[PATCH] D101215: [RISCV] Use fractional LMULs for fixed length types smaller than riscv-v-vector-bits-min.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1184
+    // We prefer to use LMUL=1 for VLEN sized types. Use fractional lmuls for
+    // narrower types, but we can't go below LMUL=64/SEW.
     unsigned EltsPerBlock = RISCV::RVVBitsPerBlock / EltVT.getSizeInBits();
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Maybe this comment could be corrected/clarified. I see what it's trying to convey but saying we can't go below `LMUL=64/SEW` makes it sound like we can't have fractional types at all since they'd always be at least 1.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1186
     unsigned EltsPerBlock = RISCV::RVVBitsPerBlock / EltVT.getSizeInBits();
-    return MVT::getScalableVectorVT(EltVT, LMul * EltsPerBlock);
+    unsigned NumElts = divideCeil(VT.getSizeInBits() * EltsPerBlock, MinVLen);
+    return MVT::getScalableVectorVT(EltVT, NumElts);
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Is `VT.getSizeInBits() * EltsPerBlock` just `VT.getVectorNumElements() * RISCV::RVVBitsPerBlock`?


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  https://reviews.llvm.org/D101215/new/

https://reviews.llvm.org/D101215