[llvm] d5c2492 - [PowerPC] Fix SELECT_CC with i64 operand on PPC32

[Qiu Chaofan via llvm-commits]

Author: Qiu Chaofan
Date: 2021-04-28T17:48:33+08:00
New Revision: d5c24924552a16868c9a99379e6fdb60cd8f77de

URL: https://github.com/llvm/llvm-project/commit/d5c24924552a16868c9a99379e6fdb60cd8f77de
DIFF: https://github.com/llvm/llvm-project/commit/d5c24924552a16868c9a99379e6fdb60cd8f77de.diff

LOG: [PowerPC] Fix SELECT_CC with i64 operand on PPC32

This patch fixes the infinite loop in legalization of PPC32 SELECT_CC
with 64-bit operand.

Added: 
    llvm/test/CodeGen/PowerPC/ppc32-selectcc-i64.ll

Modified: 
    llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 4ccabb05b7796..7e6b45e51867b 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1219,7 +1219,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
 
       // We need to handle f128 SELECT_CC with integer result type.
       setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
-      setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
+      setOperationAction(ISD::SELECT_CC, MVT::i64, isPPC64 ? Custom : Expand);
     }
 
     if (Subtarget.hasP9Altivec()) {

diff  --git a/llvm/test/CodeGen/PowerPC/ppc32-selectcc-i64.ll b/llvm/test/CodeGen/PowerPC/ppc32-selectcc-i64.ll
new file mode 100644
index 0000000000000..801944315de00
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/ppc32-selectcc-i64.ll
@@ -0,0 +1,63 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc -mcpu=pwr7 < %s | FileCheck %s
+
+; This piece of IR is expanded from memcmp.
+define i1 @cmp(i8* %a, i8* %b) {
+; CHECK-LABEL: cmp:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lwz 5, 4(3)
+; CHECK-NEXT:    lwz 7, 0(3)
+; CHECK-NEXT:    lwz 6, 4(4)
+; CHECK-NEXT:    lwz 8, 0(4)
+; CHECK-NEXT:    xor 9, 7, 8
+; CHECK-NEXT:    xor 10, 5, 6
+; CHECK-NEXT:    or. 9, 10, 9
+; CHECK-NEXT:    bne 0, .LBB0_2
+; CHECK-NEXT:  # %bb.1: # %loadbb1
+; CHECK-NEXT:    lbz 3, 8(3)
+; CHECK-NEXT:    lbz 4, 8(4)
+; CHECK-NEXT:    sub 3, 3, 4
+; CHECK-NEXT:    srwi 3, 3, 31
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB0_2: # %res_block
+; CHECK-NEXT:    cmplw 7, 8
+; CHECK-NEXT:    cmplw 1, 5, 6
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    li 4, -1
+; CHECK-NEXT:    crandc 20, 0, 2
+; CHECK-NEXT:    crand 21, 2, 4
+; CHECK-NEXT:    cror 20, 21, 20
+; CHECK-NEXT:    isel 3, 4, 3, 20
+; CHECK-NEXT:    srwi 3, 3, 31
+; CHECK-NEXT:    blr
+entry:
+  br label %loadbb
+
+res_block:
+  %0 = icmp ult i64 %4, %5
+  %1 = select i1 %0, i32 -1, i32 1
+  br label %endblock
+
+loadbb:
+  %2 = bitcast i8* %a to i64*
+  %3 = bitcast i8* %b to i64*
+  %4 = load i64, i64* %2, align 1
+  %5 = load i64, i64* %3, align 1
+  %6 = icmp eq i64 %4, %5
+  br i1 %6, label %loadbb1, label %res_block
+
+loadbb1:
+  %7 = getelementptr i8, i8* %a, i64 8
+  %8 = getelementptr i8, i8* %b, i64 8
+  %9 = load i8, i8* %7, align 1
+  %10 = load i8, i8* %8, align 1
+  %11 = zext i8 %9 to i32
+  %12 = zext i8 %10 to i32
+  %13 = sub i32 %11, %12
+  br label %endblock
+
+endblock:
+  %phi.res = phi i32 [ %13, %loadbb1 ], [ %1, %res_block ]
+  %icmp = icmp slt i32 %phi.res, 0
+  ret i1 %icmp
+}