[PATCH] D101414: [AMDGPU] Disable the scalar IR, SDWA and load store vectorizer passes at -O1

Baptiste Saleil via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Apr 27 16:55:49 PDT 2021


bsaleil created this revision.
bsaleil added reviewers: piotr, rampitec, foad.
bsaleil added projects: LLVM, AMDGPU.
Herald added subscribers: kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl, arsenm.
bsaleil requested review of this revision.
Herald added subscribers: llvm-commits, wdng.

This patch disables some of the passes at -O1. These passes have a significant impact on compilation time, so we only want them to be enabled starting from -O2.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D101414

Files:
  llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp


Index: llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -901,7 +901,7 @@
     if (EnableSROA)
       addPass(createSROAPass());
 
-    if (EnableScalarIRPasses)
+    if (EnableScalarIRPasses && TM.getOptLevel() > CodeGenOpt::Less)
       addStraightLineScalarOptimizationPasses();
 
     if (EnableAMDGPUAliasAnalysis) {
@@ -933,7 +933,7 @@
   //   %1 = shl %a, 2
   //
   // but EarlyCSE can do neither of them.
-  if (getOptLevel() != CodeGenOpt::None && EnableScalarIRPasses)
+  if (EnableScalarIRPasses && getOptLevel() > CodeGenOpt::Less)
     addEarlyCSEOrGVNPass();
 }
 
@@ -949,7 +949,7 @@
 
   TargetPassConfig::addCodeGenPrepare();
 
-  if (EnableLoadStoreVectorizer)
+  if (EnableLoadStoreVectorizer && TM->getOptLevel() > CodeGenOpt::Less)
     addPass(createLoadStoreVectorizerPass());
 
   // LowerSwitch pass may introduce unreachable blocks that can
@@ -1072,7 +1072,7 @@
   if (EnableDPPCombine)
     addPass(&GCNDPPCombineID);
   addPass(&SILoadStoreOptimizerID);
-  if (EnableSDWAPeephole) {
+  if (EnableSDWAPeephole && getOptLevel() > CodeGenOpt::Less) {
     addPass(&SIPeepholeSDWAID);
     addPass(&EarlyMachineLICMID);
     addPass(&MachineCSEID);


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