[PATCH] D101369: [AArch64][SVE] Fold insert(zero, extract(X, 0), 0) -> X, when X is known to zero lanes 1-N

[Bradley Smith via Phabricator via llvm-commits]

bsmith created this revision.
bsmith added reviewers: paulwalker-arm, peterwaller-arm, joechrisellis, david-arm.
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Specifically, this allow us to rely on the lane zero'ing behaviour of
SVE reduce instructions.

Co-authored-by: Paul Walker <paul.walker at arm.com>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D101369

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-implicit-zero-filling.ll

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