[llvm] 029e41e - [X86] Ensure multiclass ATOMIC_RMW_BINOP is tagged as MayLoad and MayStore

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2021-04-27T14:11:22+01:00
New Revision: 029e41ec98009b76c5d2aa9e616a1646c0e2c21b

URL: https://github.com/llvm/llvm-project/commit/029e41ec98009b76c5d2aa9e616a1646c0e2c21b
DIFF: https://github.com/llvm/llvm-project/commit/029e41ec98009b76c5d2aa9e616a1646c0e2c21b.diff

LOG: [X86] Ensure multiclass ATOMIC_RMW_BINOP is tagged as MayLoad and MayStore

These are RMW ops and should be tagged as both loads and stores.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86InstrCompiler.td

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86InstrCompiler.td b/llvm/lib/Target/X86/X86InstrCompiler.td
index e9dedf130a38..8cd47abbb30e 100644
--- a/llvm/lib/Target/X86/X86InstrCompiler.td
+++ b/llvm/lib/Target/X86/X86InstrCompiler.td
@@ -934,8 +934,8 @@ defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg", X86cas>;
 // Atomic exchange and add
 multiclass ATOMIC_RMW_BINOP<bits<8> opc8, bits<8> opc, string mnemonic,
                             string frag> {
-  let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1,
-      SchedRW = [WriteALURMW] in {
+  let Constraints = "$val = $dst", Defs = [EFLAGS], mayLoad = 1, mayStore = 1,
+      isCodeGenOnly = 1, SchedRW = [WriteALURMW] in {
     def NAME#8  : I<opc8, MRMSrcMem, (outs GR8:$dst),
                     (ins GR8:$val, i8mem:$ptr),
                     !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),