[PATCH] D101342: [SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach computeKnownBits/ComputeNumSignBits about atomics

[Jessica Clarke via Phabricator via llvm-commits]

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Unlike normal loads these don't have an extension field, but we know
from TargetLowering whether these are sign-extending or zero-extending,
and so can optimise away unnecessary extensions.

This was noticed on RISC-V, where sign extensions in the calling
convention would result in unnecessary explicit extension instructions,
but this also fixes some Mips inefficiencies. PowerPC sees churn in the
tests as all the zero extensions are only for promoting 32-bit to
64-bit, but these zero extensions are still not optimised away as they
should be, likely due to i32 being a legal type.

This also simplifies the WebAssembly code somewhat, which currently
works around the lack of target-independent combines with some ugly
patterns that break once they're optimised away.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D101342

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td
  llvm/test/CodeGen/Mips/atomic.ll
  llvm/test/CodeGen/PowerPC/atomics-i16-ldst.ll
  llvm/test/CodeGen/PowerPC/atomics-i32-ldst.ll
  llvm/test/CodeGen/PowerPC/atomics-i64-ldst.ll
  llvm/test/CodeGen/PowerPC/atomics-i8-ldst.ll
  llvm/test/CodeGen/RISCV/atomic-signext.ll

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