[PATCH] D101246: [RISCV] Select 5 bit immediate for VSETIVLI during isel rather than peepholing in the custom inserter.

[Zakk Chen via Phabricator via llvm-commits]

khchen added a comment.

Select the immediate during isel does make sense to me, but unfortunately there are some cases have a slower result.
Do you know is there any cases which have better instruction order and reduce register spilling when apply the new scheme?
I'm just afraid of the new one would be always generate the slower instruction order.


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https://reviews.llvm.org/D101246