[llvm] 9579af2 - [AMDGPU] Fix autogenerated wwm-reserved-spill.ll

[Sebastian Neubauer via llvm-commits]

Author: Sebastian Neubauer
Date: 2021-04-26T19:09:09+02:00
New Revision: 9579af2bd7f39b2118039b66b1a762cf05e7b102

URL: https://github.com/llvm/llvm-project/commit/9579af2bd7f39b2118039b66b1a762cf05e7b102
DIFF: https://github.com/llvm/llvm-project/commit/9579af2bd7f39b2118039b66b1a762cf05e7b102.diff

LOG: [AMDGPU] Fix autogenerated wwm-reserved-spill.ll

Due to a bug in update_llc_test_checks.py, the test is wrongly
coalesced between run lines. Remove common check prefix to fix that.
NFC.

Added: 
    

Modified: 
    llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll b/llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
index 3b9d455d6fbc..127b083be839 100644
--- a/llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
+++ b/llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O0 -mtriple=amdgcn- -mcpu=gfx900 -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GFX9-O0 %s
-; RUN: llc -mtriple=amdgcn- -mcpu=gfx900 -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GFX9-O3 %s
+; RUN: llc -O0 -mtriple=amdgcn- -mcpu=gfx900 -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9-O0 %s
+; RUN: llc -mtriple=amdgcn- -mcpu=gfx900 -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9-O3 %s
 
 define amdgpu_gfx void @strict_wwm_no_cfg(<4 x i32> inreg %tmp14) {
 ; GFX9-O0-LABEL: strict_wwm_no_cfg:
@@ -320,13 +320,23 @@ merge:
 }
 
 define hidden i32 @strict_wwm_called(i32 %a) noinline {
-; GFX9-LABEL: strict_wwm_called:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_add_u32_e32 v1, v0, v0
-; GFX9:         v_mul_lo_u32 v0, v1, v0
-; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v1
-; GFX9-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-O0-LABEL: strict_wwm_called:
+; GFX9-O0:       ; %bb.0:
+; GFX9-O0-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-O0-NEXT:    v_add_u32_e32 v1, v0, v0
+; GFX9-O0-NEXT:    ; implicit-def: $sgpr4
+; GFX9-O0-NEXT:    ; implicit-def: $sgpr4
+; GFX9-O0-NEXT:    v_mul_lo_u32 v0, v1, v0
+; GFX9-O0-NEXT:    v_sub_u32_e32 v0, v0, v1
+; GFX9-O0-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-O3-LABEL: strict_wwm_called:
+; GFX9-O3:       ; %bb.0:
+; GFX9-O3-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-O3-NEXT:    v_add_u32_e32 v1, v0, v0
+; GFX9-O3-NEXT:    v_mul_lo_u32 v0, v1, v0
+; GFX9-O3-NEXT:    v_sub_u32_e32 v0, v0, v1
+; GFX9-O3-NEXT:    s_setpc_b64 s[30:31]
   %add = add i32 %a, %a
   %mul = mul i32 %add, %a
   %sub = sub i32 %mul, %add