[PATCH] D101062: [AArch64][SVE] Better utilisation of immediate forms for bitwise intrinsics

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:4994
+  SDValue &Op = N;
+  while (Op.getOpcode() == AArch64ISD::REINTERPRET_CAST) {
+    Op = Op.getOperand(0);
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I had expected there to be only a single REINTERPRET_CAST when it gets to the instruction selection phase, but I guess there are no combines that remove successive REINTERPRET_CASTs at the moment?


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Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:346
                                   ZPRRegOp zprty, ValueType it, ComplexPattern cpx, Instruction inst>
   : Pat<(vt (op (pt (AArch64ptrue 31)), (vt zprty:$Op1), (vt (AArch64dup (it (cpx i32:$imm)))))),
         (inst $Op1, i32:$imm)>;
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should this pattern also use SVEAllActive?


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Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:354
 
+class SVE_1_Op_Imm_Log_Pred_Pat<ValueType vt, ValueType pt, SDPatternOperator op,
+                                ZPRRegOp zprty, ValueType it, ComplexPattern cpx, Instruction inst>
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You're probably just following precedent, but I find the naming here a bit confusing since I'd think `_Pat` suggests the pattern takes a predicate. In this case, my preference would be to pass the `(SVEAllActive)` as operand/patfrag to the pattern class.


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  https://reviews.llvm.org/D101062/new/

https://reviews.llvm.org/D101062