[PATCH] D101215: [RISCV] Use fractional LMULs for fixed length types smaller than riscv-v-vector-bits-min.

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 added a comment.

The rationale looks reasonable to me.



================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1183
   case MVT::f64: {
-    unsigned LMul = divideCeil(VT.getSizeInBits(), MinVLen);
+    // We prefer to use LMUL=1 for VLEN sized types. Use fractonal lmuls for
+    // narrower types, but we can't below LMUL=64/SEW.
----------------
Typo


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  https://reviews.llvm.org/D101215/new/

https://reviews.llvm.org/D101215