[PATCH] D101177: [AMDGPU] Avoid adding nullptr keys to hash table

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp:987
+            // Conservatively add the s_waitcnt in the absence of memop data.
+            addWait(Wait, LGKM_CNT, 0);
+          } else if (SLoadAddresses.count(Ptr)) {
----------------
arsenm wrote:
> Doesn't this normally use a register value based dependency? Why does it need to be conservative?
This isn't handling a register dependency, it's D71934 "need to insert wait between the scalar load and vector store to the same address to avoid WAR conflict".


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101177/new/

https://reviews.llvm.org/D101177