[PATCH] D101262: [SelectionDAG] Use a VTSDNode to store the saturation width for FP_TO_SINT_SAT/FP_TO_UINT_SAT

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 340404.
craig.topper added a comment.

-Use scalar type to avoid vector type legalization changes and changes to UnrollVectorOp.
-Add code to getNode to check the rules.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101262/new/

https://reviews.llvm.org/D101262

Files:
  llvm/include/llvm/CodeGen/ISDOpcodes.h
  llvm/include/llvm/Target/TargetSelectionDAG.td
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
  llvm/lib/Target/WebAssembly/WebAssemblyInstrConv.td
  llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
  llvm/lib/Target/X86/X86ISelLowering.cpp

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