[PATCH] D101143: [RISCV] [1/2] Add IR intrinsic for Zbe extension

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoB.td:36
 def riscv_unshflw: SDNode<"RISCVISD::UNSHFLW",SDT_RISCVIntBinOpW>;
+def riscv_bcompress    : SDNode<"RISCVISD::BCOMPRESS",   SDTIntBinOp>;
+def riscv_bcompressw   : SDNode<"RISCVISD::BCOMPRESSW",   SDT_RISCVIntBinOpW>;
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Can you line up the start of the SDT* argument on each of these lines so that they're in columns like the ones above. I don't care that they don't line up with the ones above. I just want these 4 new ones to be lined up.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101143/new/

https://reviews.llvm.org/D101143