[PATCH] D101163: [AArch64] Prevent spilling between ldxr/stxr pairs

[LemonBoy via Phabricator via llvm-commits]

LemonBoy created this revision.
LemonBoy added reviewers: t.p.northover, aemerson, arsenm.
Herald added subscribers: tmatheson, danielkiss, jfb, hiraditya, kristof.beyls.
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Apply the same logic used to check if CMPXCHG nodes should be expanded at `-O0`: the register allocator may end up spilling some register in between the atomic load/store pairs, breaking the atomicity and possibly stalling the execution.

Fixes PR48017


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D101163

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/atomicrmw-O0.ll

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