[llvm] b1f463d - [AArch64] Fix for BTI landing pad insertion with PAC-RET+bkey.

[Daniel Kiss via llvm-commits]

Author: Daniel Kiss
Date: 2021-04-23T10:07:25+02:00
New Revision: b1f463dcae3aafadac2b6a36583f38dea6a7136e

URL: https://github.com/llvm/llvm-project/commit/b1f463dcae3aafadac2b6a36583f38dea6a7136e
DIFF: https://github.com/llvm/llvm-project/commit/b1f463dcae3aafadac2b6a36583f38dea6a7136e.diff

LOG: [AArch64] Fix for BTI landing pad insertion with PAC-RET+bkey.

EMITBKEY is emitted for PAC-RET+bkey, which is a non machine instructions.

PR: 49957

Reviewed By: eugenis

Differential Revision: https://reviews.llvm.org/D100996

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
    llvm/test/CodeGen/AArch64/sign-return-address.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64BranchTargets.cpp b/llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
index 6506180bee56..d2acd1de74c8 100644
--- a/llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
+++ b/llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
@@ -121,8 +121,10 @@ void AArch64BranchTargets::addBTI(MachineBasicBlock &MBB, bool CouldCall,
 
   auto MBBI = MBB.begin();
 
-  // Skip the meta instuctions, those will be removed anyway.
-  for (; MBBI != MBB.end() && MBBI->isMetaInstruction(); ++MBBI)
+  // Skip the meta instructions, those will be removed anyway.
+  for (; MBBI != MBB.end() &&
+         (MBBI->isMetaInstruction() || MBBI->getOpcode() == AArch64::EMITBKEY);
+       ++MBBI)
     ;
 
   // SCTLR_EL1.BT[01] is set to 0 by default which means

diff  --git a/llvm/test/CodeGen/AArch64/sign-return-address.ll b/llvm/test/CodeGen/AArch64/sign-return-address.ll
index 51df38aa5dfc..68af27d01d76 100644
--- a/llvm/test/CodeGen/AArch64/sign-return-address.ll
+++ b/llvm/test/CodeGen/AArch64/sign-return-address.ll
@@ -122,3 +122,33 @@ define i32 @leaf_sign_all_b_key(i32 %x) "sign-return-address"="all" "sign-return
 define i32 @leaf_sign_all_v83_b_key(i32 %x) "sign-return-address"="all" "target-features"="+v8.3a" "sign-return-address-key"="b_key" {
   ret i32 %x
 }
+
+; CHECK-LABEL: @leaf_sign_all_a_key_bti
+; CHECK-NOT:   hint #34
+; CHECK:       hint #25
+; CHECK:       hint #29
+; CHECK-V83A:  paciasp
+; CHECK-V83A:  retaa
+define i32 @leaf_sign_all_a_key_bti(i32 %x) "sign-return-address"="all" "sign-return-address-key"="a_key" "branch-target-enforcement"="true"{
+  ret i32 %x
+}
+
+; CHECK-LABEL: @leaf_sign_all_b_key_bti
+; CHECK-NOT:   hint #34
+; CHECK:       hint #27
+; CHECK:       hint #31
+; CHECK-V83A:  pacibsp
+; CHECK-V83A:  retab
+define i32 @leaf_sign_all_b_key_bti(i32 %x) "sign-return-address"="all" "sign-return-address-key"="b_key" "branch-target-enforcement"="true"{
+  ret i32 %x
+}
+
+; CHECK-LABEL: @leaf_sign_all_v83_b_key_bti
+; CHECK-NOT:   hint #34
+; CHECK: pacibsp
+; CHECK-NOT: ret
+; CHECK: retab
+; CHECK-NOT: ret
+define i32 @leaf_sign_all_v83_b_key_bti(i32 %x) "sign-return-address"="all" "target-features"="+v8.3a" "sign-return-address-key"="b_key" "branch-target-enforcement"="true" {
+  ret i32 %x
+}