[llvm] 914c832 - [InlineSpiller] Clean-up isSpillCandBB

[Serguei Katkov via llvm-commits]

Author: Serguei Katkov
Date: 2021-04-23T10:16:02+07:00
New Revision: 914c8328244477d68043f36107e98794e3b9dab7

URL: https://github.com/llvm/llvm-project/commit/914c8328244477d68043f36107e98794e3b9dab7
DIFF: https://github.com/llvm/llvm-project/commit/914c8328244477d68043f36107e98794e3b9dab7.diff

LOG: [InlineSpiller] Clean-up isSpillCandBB

This is mostly NFC except that for end of BB not previous slot is used.
Idx is used to find a def of sibling live interval in that slot.
The def on end of MBB and on previous slot of end MBB should be the same,
so it should be NFC.

Reviewers: reames, qcolombet, MatzeB, wmi, rnk
Reviewed By: rnk
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D100922

Added: 
    

Modified: 
    llvm/lib/CodeGen/InlineSpiller.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/InlineSpiller.cpp b/llvm/lib/CodeGen/InlineSpiller.cpp
index 4635daf71e54..5f1cac49c4ef 100644
--- a/llvm/lib/CodeGen/InlineSpiller.cpp
+++ b/llvm/lib/CodeGen/InlineSpiller.cpp
@@ -1245,13 +1245,8 @@ bool HoistSpillHelper::rmFromMergeableSpills(MachineInstr &Spill,
 /// i.e., there should be a living sibling of OrigReg at the insert point.
 bool HoistSpillHelper::isSpillCandBB(LiveInterval &OrigLI, VNInfo &OrigVNI,
                                      MachineBasicBlock &BB, Register &LiveReg) {
-  SlotIndex Idx;
+  SlotIndex Idx = IPA.getLastInsertPoint(OrigLI, BB);
   Register OrigReg = OrigLI.reg();
-  MachineBasicBlock::iterator MI = IPA.getLastInsertPointIter(OrigLI, BB);
-  if (MI != BB.end())
-    Idx = LIS.getInstructionIndex(*MI);
-  else
-    Idx = LIS.getMBBEndIdx(&BB).getPrevSlot();
   SmallSetVector<Register, 16> &Siblings = Virt2SiblingsMap[OrigReg];
   assert(OrigLI.getVNInfoAt(Idx) == &OrigVNI && "Unexpected VNI");